WO2012101840A1 - Semiconductor integrated circuit - Google Patents

Abstract

A semiconductor integrated circuit (100) including a local oscillator (109) capable of oscillating at a plurality of oscillation frequencies, a reference signal oscillator (107) that oscillates at a prescribed reference frequency, and a variable frequency divider (110) that divides the output signal of the local oscillator by a multiple of n times the reference frequency, is further equipped with: first dividing ratio setting units (103, 104, 118) that control the dividing ratio of the variable frequency divider in accordance with a supplied DC potential; and a second dividing ratio setting units (104, 105, 118) that control the dividing ratio of the variable frequency divider in accordance with the presence or absence of a supplied pulse signal. The oscillation frequency of the local oscillator is set to a desired frequency by the control of the dividing ratio of the variable frequency divider by the first dividing ratio setting units or the second dividing ratio setting units.

Description

Semiconductor integrated circuit

The present invention relates to a semiconductor integrated circuit incorporating a PLL (Phase Locked Loop) used in an LNB (Low Noise Block Down Converter).

FIG. 9 shows a satellite broadcast receiving system including a conventional LNB 201 mounted on a satellite broadcast antenna and a satellite broadcast tuner 301 connected to the LNB 201, which is used in Patent Document 1. The configuration and operation related to frequency conversion in the LNB 201 will be described below.

The LNB 201 includes a mixer 202 that converts the frequency of a broadcast signal from a satellite into a reception frequency of a satellite broadcast tuner, and local oscillators 203 and 204 that excite the mixer 202.

The signal S201 of 10.7 GHz to 12.75 GHz sent from the satellite is frequency-converted by the mixer 202 into a signal S202 of 950 MHz to 2150 MHz, which is the reception frequency of the satellite broadcast tuner 301.

The LNB 201 includes a plurality of local oscillators 203 and 204 having different oscillation frequencies. The local oscillators 203 and 204 receive the above-mentioned signal S201 of 10.7 GHz to 12.75 GHz by dividing the frequency into 10.7 GHz to 11.7 GHz and 11.7 GHz to 12.75 GHz, respectively. It corresponds to the frequency band.

And about the switching of the frequency band for division | segmentation reception, the switching circuit 205 is switching the some local oscillator 203,204 according to each frequency band. The switching circuit 205 is controlled by a pulse signal S203 on which a frequency band switching signal sent from the satellite broadcast tuner 301 is superimposed.

As mentioned above, LNB has a relatively high processing frequency. For this reason, interference between circuits is likely to occur, and it is difficult to integrate main circuits.

However, in recent years, due to improved transistor performance, a semiconductor integrated circuit for LNB in which a frequency conversion circuit and a PLL for controlling local oscillation frequency are mounted on the same semiconductor substrate has been proposed.

FIG. 10 shows a semiconductor integrated circuit for LNB proposed in Non-Patent Document 1, and the operation related to frequency conversion will be described below together with the configuration.

In the semiconductor integrated circuit 401, the PLL circuit 404 is controlled based on a multi-bit channel selection signal S403 from the external channel selection unit 406. By this control, the PLL circuit 404 varies the oscillation frequency of the local oscillator 403 by a DC voltage that passes through the low-pass filter 405 provided outside.

Then, the signal S401 of 10.7 GHz to 12.75 GHz sent from the satellite is frequency-converted by the mixer 402 into a signal S402 of 950 MHz to 2150 MHz, which is a reception frequency of a satellite broadcast tuner (not shown).

Thus, the use of a plurality of local oscillators as in Patent Document 1 is avoided.

Japanese Patent Publication “JP-A-8-293812” (published on November 5, 1996)

IEEE Custom Integrated Circuits Conference 2004 28-3-1 pp613-pp616 “A Ku-Band Monotonic Tuner-LNB for Satellite Applications”

The frequency of 10.7 GHz to 12.75 GHz described above is a broadcast frequency in Europe. Besides this, satellite broadcasts are broadcast at various frequencies around the world. Therefore, in LNB, for frequency conversion It was necessary to cope with the local oscillation frequency of each country.

However, since the LNB 201 shown in FIG. 9 corresponds to a broadcast frequency of 10.7 GHz to 12.75 GHz, the local oscillators 203 and 204 use frequencies of 9.75 GHz and 10.6 GHz, respectively. As frequencies other than these frequencies, for example, BS for Japan and 110 ° CS broadcasting are 10.678 GHz, CS broadcasting is 10.7 GHz, and local oscillators cannot be shared for Europe and Japan. .

Further, in the case of the semiconductor integrated circuit 401 shown in FIG. 10, it is shown that the oscillation frequency of the local oscillator 403 is set by controlling the PLL circuit 404 with the serial data from the channel selection unit 406.

However, in consideration of adoption in an actual LNB, mounting a control bus that requires a large number of bits in order to cope with local oscillation frequencies in various countries around the world is due to the increase in circuit scale. Increases the size of the LNB and hinders the size reduction of the LNB body.

In general, the LNB and the satellite broadcast receiver (satellite broadcast tuner) are connected by a single coaxial cable. A large control bus can be incorporated to switch between 9.75 GHz and 10.6 GHz depending on whether a pulse signal superimposed with a frequency band switching signal is applied to the LNB via this coaxial cable. Absent.

Moreover, since the above frequency is a frequency only in a region called universal in Europe, it is necessary to provide a fixed frequency at the manufacturing stage at 10.678 GHz, which is a local oscillation frequency of other products such as those for Japan. There is.

Therefore, when the frequency setting for each destination is not set at the manufacturing stage, the local oscillation frequency setting of the LNB is performed by the user when the reception environment such as the installation of a satellite broadcasting antenna is set, and the convenience is impaired. May be.

In view of the above-described problems, the present invention provides a simple and low-cost semiconductor integrated circuit for LNB that can obtain a local oscillation signal corresponding to satellite broadcasting in each country.

A semiconductor integrated circuit according to the present invention includes a local oscillator that can oscillate at a plurality of oscillation frequencies, a reference signal oscillator that oscillates at a predetermined reference frequency, and divides the output signal of the local oscillator by n times the reference frequency. A variable frequency divider, a semiconductor integrated circuit including the first frequency division ratio setting unit for controlling a frequency division ratio of the variable frequency divider corresponding to a supplied DC potential, and a supplied pulse signal A second frequency division ratio setting unit that controls a frequency division ratio of the variable frequency divider corresponding to the presence or absence of the first frequency division ratio setting unit or the second frequency division ratio setting unit. The oscillation frequency of the local oscillator is set to a desired frequency by dividing ratio control of the variable frequency divider.

In the semiconductor integrated circuit according to the present invention, the first frequency division ratio setting unit includes an AD converter that converts the DC potential into a binarized signal, a memory that stores frequency division ratio setting data, and the 2 And a frequency division ratio setting device for generating a frequency division ratio control signal for the variable frequency divider from the digitized signal and the frequency division ratio setting data.

In the semiconductor integrated circuit according to the present invention, the second frequency division ratio setting unit includes a detector that detects the pulse signal, a memory that stores frequency division ratio setting data, and a detection output signal of the detector. And a frequency division ratio setting device for generating a frequency division ratio control signal for the variable frequency divider from the frequency division ratio setting data.

The semiconductor integrated circuit according to the present invention is characterized in that the DC potential is supplied to the first frequency division ratio setting unit via a current mirror circuit.

The semiconductor integrated circuit according to the present invention is characterized in that the DC potential is supplied to the first frequency division ratio setting unit via a buffer circuit.

The semiconductor integrated circuit according to the present invention is characterized in that the DC potential is a voltage corresponding to a resistance value between a supply terminal of the DC potential and a ground potential.

The semiconductor integrated circuit according to the present invention is characterized in that the frequency division ratio setting unit supplies a reference frequency control signal to a predetermined circuit in accordance with the change of the reference frequency.

According to the present invention, it is possible to realize a semiconductor integrated circuit for LNB that supports satellite broadcasting of countries around the world with a simple configuration.

1 is a block diagram showing a semiconductor integrated circuit according to Embodiment 1 of the present invention. FIG. 6 is a block diagram illustrating a first modification of the first embodiment. FIG. 6 is a block diagram illustrating a second modification of the first embodiment. FIG. 10 is a block diagram illustrating a third modification of the first embodiment. It is a block diagram which shows the semiconductor integrated circuit which concerns on Example 2 of this invention. FIG. 10 is a block diagram illustrating a modification of the second embodiment. It is a block diagram which shows the semiconductor integrated circuit which concerns on Example 3 of this invention. It is a block diagram which shows the semiconductor integrated circuit which concerns on Example 4 of this invention. It is a block diagram which shows the conventional LNB. It is a block diagram which shows the conventional semiconductor integrated circuit.

[Example 1]
A semiconductor integrated circuit according to a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram of a semiconductor integrated circuit 100 according to the first embodiment, and FIGS. 2 to 4 are block diagrams showing modifications 1 to 3 of the first embodiment. First, the configuration and operation will be described below with reference to FIG.

The semiconductor integrated circuit 100 includes a frequency division ratio setting voltage terminal 101, an AD converter 103, a frequency division ratio setting device 104, a detector 105, a PLL circuit 108, and a memory 118.

The AD converter 103, the division ratio setting unit 104, and the memory 118 constitute a first division ratio setting unit, and the detector 105, the division ratio setting unit 104, and the memory 118 constitute a second division ratio setting. Part.

The PLL circuit 108 includes a local oscillator 109, a variable frequency divider 110, a phase comparator 111, a charge pump 112, and a loop filter 113. As in the prior art document, the local oscillator 109 is connected to a mixer (not shown).

The local oscillator 109 is a local oscillator that can oscillate at a plurality of oscillation frequencies. The variable frequency divider 110 divides the output signal of the local oscillator 109 by n times a reference frequency described later.

Next, the operation until the semiconductor integrated circuit 100 obtains a desired local oscillation frequency will be described. The semiconductor integrated circuit 100 obtains a desired local oscillation frequency in two ways: using the first frequency division ratio setting unit and using the second frequency division ratio setting unit. We will explain in order.

When the first frequency division ratio setting unit is used, the frequency division ratio setting voltage terminal 101 is connected to the power source 102 via the current source 114, and between the frequency division ratio setting voltage terminal 101 and the ground potential. A resistor 115 is connected to.

The resistor 115 has one end connected to the input of the AD converter 103 and the other end electrically grounded.

In addition, the frequency division ratio setting voltage terminal 101 may be connected to the power source 102 (that is, the voltage source 102) without passing through the current source 114, or may be connected to the ground potential without passing through the resistor 115. It doesn't matter.

Further, as shown in Modification 1 of FIG. 2, the resistor 115 in FIG. 1 may be replaced with a variable resistor 123, or may be replaced with a switch 124 as shown in Modification 2 of FIG.

Furthermore, the power source and the division ratio setting voltage terminal 101 may be connected by a resistor 125 as shown in Modification 3 of FIG.

With these configurations, a voltage corresponding to the resistance value between the reference potential (that is, the ground potential) is generated at the frequency division ratio setting voltage terminal 101 which is the supply terminal of the DC potential.

The voltage generated at the division ratio setting voltage terminal 101 is input to the AD converter 103 and then converted into a binarized signal (binarized signal). The binarized signal is input to the frequency division ratio setting unit 104.

The division ratio setting unit 104 generates a division ratio control signal that controls the division ratio of the variable frequency divider 110. The frequency division ratio setting unit 104 collates the signal binarized by the AD converter 103 with the frequency division ratio setting data stored in the memory 118. As a result of the collation, frequency division ratio setting data corresponding to the binarized signal is selected, and a frequency division ratio control signal corresponding to the desired frequency division ratio is transmitted to the variable frequency divider 110.

Next, consider the case where the second frequency division ratio setting unit is used. In this case, a pulse signal S101 from a satellite broadcast tuner (not shown) is applied to the terminal 126, the pulse signal S101 is detected by the detector 105, and a detection output signal corresponding to the presence / absence of the pulse signal S101 is divided by the frequency division ratio setting unit 104. Transmit to. The satellite broadcast tuner is a tuner provided outside the semiconductor integrated circuit 100, for example.

The frequency division ratio setting unit 104 collates the detection output signal from the detector 105 with the frequency division ratio setting data stored in the memory 118, and varies the frequency division ratio control signal corresponding to the presence or absence of the pulse signal S101. Transmit to the frequency divider 110.

When the frequency division ratio is set by the second frequency division ratio setting unit, the voltage of the frequency division ratio setting voltage terminal 101 and the frequency division ratio by the first frequency division ratio setting unit stored in the memory 118 are used. Associate setting data that invalidates the setting. By doing so, the division ratio setting by the second division ratio setting unit may be selected.

After passing through the first or second division ratio setting, the variable frequency divider 110 divides the frequency based on the division ratio control signal obtained by either the first or second division ratio setting. The output signal is transmitted to the phase comparator 111.

The phase comparator 111 uses the output signal of the variable frequency divider 110 and the signal of the reference signal oscillator 107 that generates a predetermined reference frequency using the crystal resonator 106 connected to the outside via the terminals 116 and 117. Compare the phase difference. Then, an output signal indicating the comparison result is transmitted to the charge pump 112.

The charge pump 112 generates a current corresponding to the output signal of the phase comparator. The loop filter 113 converts the signal from the charge pump 112 into a control voltage for the local oscillator 109. As a result, the local oscillator 109 oscillates at an oscillation frequency corresponding to the control signal from the charge pump 112, thereby obtaining a desired local oscillation frequency.

The above is a series of operations until a desired local oscillation frequency is obtained in the semiconductor integrated circuit 100. Here, consider the case of frequency division ratio setting by the first frequency division ratio setting unit. In this case, in the Integrer-N type PLL that controls the local oscillator at an integer multiple of the reference frequency, the frequency division ratio of the variable frequency 110 is determined by how many times the reference frequency is set in advance. The relationship between the reference frequency and the frequency division ratio will be described below.

For example, when the reference frequency is generated at 25 MHz, an oscillation frequency of 9.75 GHz is obtained by setting the frequency division ratio of the variable frequency divider 110 to 390 times by the frequency division ratio setting signal of the frequency division ratio setting unit 104. be able to.

Also, an oscillation frequency of 10.6 GHz can be obtained by setting the frequency division ratio of the variable frequency divider 110 to 424 times by the frequency division ratio control signal of the frequency division ratio setting unit 104.

Furthermore, the explanation will be based on the specific local oscillation frequency used in each country. When the local oscillation frequency of CS broadcasting in Japan is 25 MHz, 10.7 GHz is set by setting the frequency division ratio of the variable frequency divider 110 to 428 times by the frequency division ratio division ratio control signal of the frequency division ratio setting unit 104. Can be obtained.

Also, consider the case where a local oscillation frequency of 10.75 GHz in Chinese satellite broadcasting is set. In this case, 10.75 GHz can be obtained by setting the frequency division ratio of the variable frequency divider 110 to 430 times by the frequency division ratio control signal of the frequency division ratio setting unit 104 with respect to the reference frequency of 25 MHz. it can.

In a setting involving switching of the local oscillation frequencies of 9.75 GHz and 10.6 GHz in European satellite broadcasting, the frequency division ratio is set by the second frequency division ratio setting unit. Regarding the operation, that is, the frequency division ratio setting by the second frequency division ratio setting unit, first, the detector 105 detects the presence or absence of a pulse signal S101 from a satellite broadcast tuner (not shown).

Here, when there is no pulse signal S101, the frequency division ratio control signal corresponding to the local oscillation frequency of 9.75 GHz is transferred from the frequency division ratio setting unit 104 to the variable frequency divider 110. On the other hand, when the pulse signal S101 is present, the frequency division ratio control signal corresponding to the local oscillation frequency of 10.6 GHz is transferred from the frequency division ratio setting unit 104 to the variable frequency divider 110.

In the above description, the Integer-N type PLL has been described as an example, but it can also be used for a Fractional-N type PLL.

As described above, according to the first embodiment, it is possible to realize a semiconductor integrated circuit for LNB corresponding to destinations around the world with a single circuit specification. In such a semiconductor integrated circuit, the frequency division ratio of the variable frequency divider 110 is controlled by setting the terminal voltage of the frequency division ratio setting voltage terminal 101, and the variable frequency divider 110 is controlled by the pulse signal S101 sent from an external satellite broadcast tuner. This can be realized by frequency division ratio control.

[Example 2]
Next, a second embodiment of the semiconductor integrated circuit of the present invention will be described with reference to FIGS.

FIG. 5 is a block diagram of the semiconductor integrated circuit 200 according to the second embodiment, and FIG. 6 shows a modification thereof. The configuration and operation will be described below. 5 and 6, the same parts as those in the first embodiment are denoted by the same reference numerals, and the description of the same parts as those in the first embodiment will not be repeated.

5 differs from the first embodiment of FIG. 1 in that a potential is applied from the current source 114 to the frequency division ratio setting voltage terminal 101 via the current mirror circuit 119. FIG. Here, by connecting the resistor 115 between the division ratio setting voltage terminal 101 and the reference potential, the potential of the division ratio setting voltage terminal 101 can be set as in the first embodiment.

In this embodiment, since the potential is applied to the division ratio setting voltage 101 via the current mirror circuit 119, the division ratio setting voltage terminal 101 is directly connected to the division ratio setting voltage terminal 101 as shown in FIG. It is also possible to connect to a power source.

In the modification of FIG. 6, the voltage of the division ratio setting voltage terminal 101 can be set to the power supply voltage by eliminating the resistor 115 in FIG. As a result, in addition to the voltage value corresponding to the resistance value between the division ratio setting voltage terminal 101 and the reference potential, the power supply voltage itself can be used as the voltage of the division ratio setting voltage terminal 101, so the voltage setting range is expanded. can do. Accordingly, the frequency division ratio setting range of the frequency division ratio setting unit 102 can be expanded.

Example 3
Next, a third embodiment of the semiconductor integrated circuit according to the present invention will be described with reference to FIG.

FIG. 7 shows a block diagram of a semiconductor integrated circuit 300 according to the third embodiment. In FIG. 7, the same parts as those in the first and second embodiments are denoted by the same reference numerals, and the description of the same parts as those in the first and second embodiments will not be repeated.

7 is different from the first embodiment in FIG. 1 and the second embodiment in FIG. 2 in that a buffer circuit 121 is provided between the frequency division ratio setting voltage terminal 101 and the AD converter 103. Providing the buffer circuit 121 has the following operational advantages.

When the input impedance of the AD converter 103 becomes extremely low due to some cause (for example, a failure of the AD converter 103), the voltage of the frequency division ratio setting voltage terminal 101 is lowered to an unintended voltage. That is, the input voltage to the AD converter 103 is lowered, and the frequency division ratio setting unit 104 controls the variable frequency divider 110 with an unintended frequency division ratio setting signal. As a result, a desired local oscillation frequency is obtained. It can no longer be obtained. Assuming such a case, the AD converter 103 and the division ratio setting unit 104 can be stably operated by driving the AD converter 103 via the buffer circuit 121 having a low output impedance.

Example 4
A semiconductor integrated circuit according to a fourth embodiment of the present invention will be described with reference to FIG.

FIG. 8 shows a block diagram of a semiconductor integrated circuit 400 according to the fourth embodiment. In FIG. 8, the same parts as those in the first, second, and third embodiments are denoted by the same reference numerals, and the description of the same parts as those in the first, second, and third embodiments will not be repeated.

8 differs from the first embodiment in FIG. 1, the second embodiment in FIG. 5, and the third embodiment in FIG. 7 in that the frequency division ratio setting unit 104 is connected to another circuit 122 (a predetermined circuit, for example, the frequency is 22 kHz. The reference frequency control signal S102 is supplied to a switched capacitor or a band-pass filter circuit for selecting a pulse signal. The use of the reference frequency control signal S102 has the following manufacturing advantages.

In a semiconductor integrated circuit, an internal reference frequency for operation may be shared by a plurality of circuits. That is, in FIG. 8, the other circuit 122 shares the reference frequency of the reference signal oscillator 107 using the crystal resonator 106.

In such a case, a case is considered in which the reference frequency is changed by changing the frequency of the crystal resonator 106 to be different from the initially set frequency for some reason (for example, partial damage of the crystal resonator 106). In this case, the desired oscillation frequency of the local oscillator 109 can be dealt with by setting the division ratio of the variable frequency divider 110, but the other circuit 122 malfunctions due to the changed reference frequency.

As a specific example, the local oscillation frequency of domestic BS and 110 ° CS broadcasting is 10.678 GHz. In this case, the reference frequency of the reference signal oscillator 107 is set to 19 MHz, and a reference signal is generated by the crystal resonator 106 corresponding thereto, and the frequency division ratio setting unit 104 increases the frequency division ratio of the variable frequency divider 110 by 562 times. Control to be By doing so, 10.678 GHz which is a desired local oscillation frequency can be obtained.

On the other hand, when the other circuit 122 is set to operate at a reference frequency of 25 MHz, it malfunctions when the reference frequency becomes 19 MHz. Therefore, the frequency division ratio setting unit 104 changes the operation reference frequency of the other circuit 122 to 19 MHz by supplying the reference frequency control signal S102 to the other circuit 122 so that such a malfunction does not occur. The other circuit 122 is set to operate at the changed reference frequency.

Thus, in the fourth embodiment, since the reference frequency of the reference signal oscillator 107 can be determined in accordance with the frequency division ratio setting of the variable frequency divider 110, the degree of freedom in selecting a crystal resonator can be improved.

As described above, the semiconductor integrated circuit according to the present invention can be suitably used for LNBs corresponding to broadcast frequencies in countries around the world with a simple configuration. Further, the present invention can be widely applied to all frequency synthesizer type semiconductor integrated circuits using a PLL.

100, 200, 300, 400, 401 Semiconductor integrated circuit 101 Dividing ratio setting voltage terminal 102 Power supply 103 AD converter 104 Dividing ratio setter 105 Detector 106 Crystal oscillator 107 Reference signal oscillator 108, 404 PLL circuit 109, 203 , 204, 403 Local oscillator 110 Variable frequency divider 111 Phase comparator 112 Charge pump 113 Loop filter 114, 120 Current source 115, 125 Resistance 116, 117, 126, 127 Terminal 118 Memory 119 Current mirror circuit 121 Buffer circuit 122 Other Circuit 123 Variable resistance 124 Switch 201 LNB
202, 402 Mixer 205 Switching circuit 301 Satellite broadcast tuner 405 Low-pass filter 406 Channel selection unit S101, S203 Pulse signal S102 Reference frequency control signal

Claims (9)

A local oscillator capable of oscillating at multiple oscillation frequencies;
A reference signal oscillator that oscillates at a predetermined reference frequency;
A variable frequency divider that divides the output signal of the local oscillator by n times the reference frequency;
A semiconductor integrated circuit comprising:
A first frequency division ratio setting unit for controlling a frequency division ratio of the variable frequency divider corresponding to a supplied DC potential;
A second frequency division ratio setting unit that controls the frequency division ratio of the variable frequency divider corresponding to the presence or absence of the supplied pulse signal;
The oscillation frequency of the local oscillator is set to a desired frequency by frequency division ratio control of the variable frequency divider by the first frequency division ratio setting unit or the second frequency division ratio setting unit. A semiconductor integrated circuit. The first frequency division ratio setting unit includes:
An AD converter that converts the DC potential into a binary signal;
A memory storing division ratio setting data;
2. The semiconductor integrated circuit according to claim 1, further comprising: a frequency division ratio setting unit that generates a frequency division ratio control signal of the variable frequency divider from the binarized signal and the frequency division ratio setting data. circuit. The second frequency division ratio setting unit includes:
A detector for detecting the pulse signal;
A memory storing division ratio setting data;
2. The frequency division ratio setting device according to claim 1, further comprising: a frequency division ratio setting device that generates a frequency division ratio control signal of the variable frequency divider from the detection output signal of the detector and the frequency division ratio setting data. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the DC potential is supplied to the first frequency division ratio setting unit via a current mirror circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the DC potential is supplied to the first frequency division ratio setting unit via a buffer circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the DC potential is a voltage corresponding to a resistance value between a supply terminal of the DC potential and a ground potential. The first frequency division ratio setting unit or the second frequency division ratio setting unit supplies a reference frequency control signal to a predetermined circuit in accordance with the change of the reference frequency. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the pulse signal is supplied from a tuner provided outside the semiconductor integrated circuit. A resistor having one end connected to the input of the AD converter and the other end electrically grounded;
The semiconductor integrated circuit according to claim 2, further comprising: a current source connected to a voltage source at an input and an output connected to an input of the AD converter.

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