201233051 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體積體電路，其係用於LNB(低 雜訊降頻器）’且内建有PLL(相位鎖定迴路）者。 【先前技術】 圖9係顯示專利文獻1所使用之包含搭載於衛星播放用天 線之先前之LNB 201、及連接於該LNB 201之衛星播放調 s皆器301之衛星播放接收系統。以下予以說明關於lnb 201 中之頻率轉換之構成與動作。 LNB 201包含：將自衛星之播放信號之頻率轉換成衛星 播放調諧器之接收頻率之混頻器202 ;及激盪該混頻器202 之局部振盛器203、204。 自衛星送達之10.7 GHz至12.75 GHz之信號S201係藉由 混頻器202頻率轉換成衛星播放調諧器301之接收頻率之 950 MHz至 2150 MHz之信號 S202。 又’ LNB 2 01係包含有振盪頻率不同之複數個局部振盈 器203、204。局部振盪器203、204係將上述10.7 GHz至 12·75 GHz之信號S201以分割頻率為10.7 GHz至11.7 GHz與 11.7 GHz至12.75 GHz且接收之方式，對應於各自之頻率 帶域。 且，關於切換用以分割接收之頻率帶域，切換電路 係對應各自之頻率帶域切換複數個局部振盪器2〇3、2〇4。 切換電路205係藉由重疊自衛星播放調諧器3〇1傳送來之頻 率帶域切換用信號之脈衝信號S203而控制。 156876.doc 201233051 如上所述，LNB處理之頻率比較高。因此，容易引起電 路相互之干擾等而難以使主要電路積體化。 然而，近年來，藉由電晶體性能之提高，亦有人提出有 將頻率轉換電路與用以控制局部振盪頻率之PLL搭載於同 一半導體基板上之LNB用之半導體積體電路。 圖1 〇係顯示非專利文獻1所提出之LNB用之半導體積體 電路’予以說明如下構成及關於頻率轉換之動作。 半導體積體電路401，係基於來自外部之通道選擇部4〇6 之多位元通道選擇信號S4 03而控制PLL電路404。藉由該 控制’ PLL電路404係藉由經由設置於外部之低通濾波器 405之直流電壓，使局部振盪器403之振盪頻率可變。 且’自衛星送達之10.7 GHz至12.75 GHz之信號S401係 以混頻器402頻率轉換為未圖示之衛星播放調諸器之接收 頻率之950 MHz至2150 MHz之信號S402。 藉此，避免使用如專利文獻1之複數之局部振盪器。 [先前技術文獻] [專利文獻] [專利文獻1]曰本公開專利公報「特開平8_293812號公報 (1996年11月5日公開）」 [非專利文獻1] IEEE客戶式積體電路會議2004 28-3-1第 613 頁至第 616 頁「A Ku-Band Monolithic Tuner-LNB for Satellite Applications」 【發明内容】 [發明所欲解決之問題] 156876.doc 201233051 上述之10_7 GHz至12.75 GHz之頻率係歐洲之播放頻 率，除此以外，衛星播放亦於世界各國以各種頻率播放， 故LNB t，用以頻率轉換’有必要對應各國之局部振盈頻 率。 因此’如圖9所示之LNB 201係為對應於1 〇. 7 GHz至 12.75 GHz之播放頻率’局部振盪器203、204係分別使用 9.75 GHz與10.6 GHz之頻率。作為該等頻率以外之頻率， 例如，日本用之BS及110。CS播放之情形係1〇 678 GHz， CS播放係10.7 GHz，歐洲用與日本用之局部振盪器未出現 共用。 又，如圖10所示之半導體積體電路4〇1之情形，顯示有 以來自通道選擇部406之串列資料控制PLL電路4〇4，且設 定局部振盪器403之振盤頻率。 考慮知用於實際之LNB之情$，為冑應於世界各國 之局部振錢率，將需要多位元之控制用匯流排安裝於 LNB本體上，會因電路規模之增大使電路安裝用之基板大 型化，而妨礙LNB本體之小型化。 又> —201233051 VI. TECHNOLOGICAL FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit for use in an LNB (Low Noise Downconverter) and in which a PLL (Phase Locked Loop) is built in. [Prior Art] Fig. 9 shows a satellite broadcast receiving system including a previous LNB 201 mounted on a satellite broadcasting antenna and a satellite broadcast 301 connected to the LNB 201, which is used in Patent Document 1. The configuration and operation of the frequency conversion in the lnb 201 will be described below. The LNB 201 includes a mixer 202 that converts the frequency of the broadcast signal from the satellite into a reception frequency of the satellite broadcast tuner, and a local oscillator 203, 204 that agitates the mixer 202. The signal S201 transmitted from the satellite from 10.7 GHz to 12.75 GHz is frequency converted by the mixer 202 into a signal S202 of 950 MHz to 2150 MHz at the reception frequency of the satellite broadcast tuner 301. Further, the LNB 2 01 includes a plurality of local oscillators 203 and 204 having different oscillation frequencies. The local oscillators 203 and 204 correspond to the respective frequency bands in such a manner that the signal S201 of 10.7 GHz to 12·75 GHz is divided into frequencies of 10.7 GHz to 11.7 GHz and 11.7 GHz to 12.75 GHz and received. Further, regarding switching the frequency band for dividing the reception, the switching circuit switches the plurality of local oscillators 2〇3, 2〇4 corresponding to the respective frequency bands. The switching circuit 205 is controlled by a pulse signal S203 of a frequency band switching signal superimposed from the satellite broadcast tuner 3.1. 156876.doc 201233051 As mentioned above, the frequency of LNB processing is relatively high. Therefore, it is easy to cause mutual interference of circuits and the like, and it is difficult to integrate the main circuits. However, in recent years, a semiconductor integrated circuit for an LNB in which a frequency conversion circuit and a PLL for controlling a local oscillation frequency are mounted on the same semiconductor substrate has been proposed by the improvement of the performance of the transistor. Fig. 1 shows a semiconductor integrated circuit for an LNB proposed in Non-Patent Document 1. The following configuration and operation regarding frequency conversion will be described. The semiconductor integrated circuit 401 controls the PLL circuit 404 based on the multi-bit channel selection signal S304 from the external channel selecting portion 〇6. By the control, the PLL circuit 404 changes the oscillation frequency of the local oscillator 403 by the DC voltage supplied through the external low-pass filter 405. And the signal S401 of 10.7 GHz to 12.75 GHz delivered from the satellite is converted into a signal S402 of 950 MHz to 2150 MHz at the reception frequency of the satellite playback modulator, which is not converted by the mixer 402. Thereby, the use of a plurality of local oscillators as disclosed in Patent Document 1 is avoided. [PRIOR ART DOCUMENT] [Patent Document 1] [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei 8-293812 (published on Nov. 5, 1996) [Non-Patent Document 1] IEEE Customer Integrated Circuit Conference 2004 28 -3-1, pp. 613 to 616, "A Ku-Band Monolithic Tuner-LNB for Satellite Applications" [Disclosure] [Problems to be Solved by the Invention] 156876.doc 201233051 The above-mentioned frequency system of 10_7 GHz to 12.75 GHz In addition to the broadcasting frequency in Europe, satellite broadcasting is also played at various frequencies in various countries around the world. Therefore, LNB t is used for frequency conversion. It is necessary to correspond to the local vibration frequency of each country. Therefore, the LNB 201 shown in Fig. 9 is a playback frequency corresponding to 1 GHz. 7 GHz to 12.75 GHz. The local oscillators 203 and 204 use frequencies of 9.75 GHz and 10.6 GHz, respectively. As frequencies other than these frequencies, for example, BS and 110 used in Japan. The CS playback is 1 〇 678 GHz, and the CS playback system is 10.7 GHz. It is not shared between the European and local oscillators used in Japan. Further, in the case of the semiconductor integrated circuit 4〇1 shown in Fig. 10, the PLL circuit 4〇4 is controlled by the serial data from the channel selecting unit 406, and the oscillating disk frequency of the local oscillator 403 is set. Considering the fact that it is used in the actual LNB, it is necessary to install a multi-bit control bus on the LNB body for the local vibration rate in all countries of the world, which will be used for circuit installation due to the increase in circuit scale. The size of the substrate is increased, which hinders the miniaturization of the LNB body. And > —
叔而言，LNB與衛星播放接收機（衛星播放調諧 幻係以一根同轴_連接。且，根據經由該同軸電纜 將重疊有頻率帶域切換用信號之脈衝信號是否提供至LNB 、'頻率因僅於歐洲被稱為通用地域之頻率者，In the uncle, the LNB is connected to the satellite broadcast receiver (the satellite broadcast tuning phantom is connected by a coaxial _.), and according to whether the pulse signal of the signal for overlapping the frequency band switching is supplied to the LNB via the coaxial cable, the frequency Because it is called the frequency of the general area in Europe alone,
故該以外，例如針對日本箄之肅D 本#之商m之局部振盪頻率之 156876.doc 201233051 10.678 GHz ’有必要於製造階段固定設定而提供。 因此，於製造階段未設定各發送地之頻率之情形，衛星 播放用天線設置等之接收環境構築時，LNB之局部振盪頻 率設定係由使用者而進行，存在損失便利性之情形。 本發明係鑒於上述問題，提供一種簡便且低成本之 用之半導體積體電路，其能夠取得對應於各國之衛星播放 之局部振盪信號。 [解決問題之技術手段] 藉由本發明之半導體積體電路，其特徵在於，其係包含 以下者：能夠以複數個振盪頻率進行振盪動作之局部振盪 器；以特定之基準頻率振盪之基準信號振盪器；及將上述 局部振盪器之輸出信號以上述基準頻率之n倍分頻之可變 分頻器；且具備：對應於所供給之直流電位，控制上述可 變分頻器之分頻比之第丨分頻比設定部；及對應於所供給 之脈衝信號之有無，控制上述可變分頻器之分頻比之第2 分頻比設定部；根據藉由上述第卜分頻比設定部或上述第2 分頻比設定部之上述可變分頻器之分頻比控制，將上述局 部振盪器之上述振盪頻率設定為所期望之頻率。 又，本發明之半導體積體電路，其特徵在於，上述第1 分頻比設定部具備：AD轉換器，其係將上述直流電位轉 換為2值化信號；記憶||，其係儲存分頻比設定資料；及 ^頻比設定器，其係自上述2值化信號與上述分頻比設定 資料，生成上述可變分頻器之分頻比控制信號。 又’本發明之半導體積體電路，其特徵在於，上述第2 156876.doc 201233051 分頻比設定部具備：檢波器，其係檢波上述脈衝信號·記 憶體’其係儲存分頻比狀資料；及分頻比設定器，其係 自上述檢波器之檢波輸出信號與上述分頻比設定資料，生 成上述可變分頻器之分頻比控制信號。 又’本發明之半導體積體電路，其特徵在於上述直流電 位經由電流鏡電路供給至上述第i分頻比設定部。 又’本發明之半導體積體電路，其特徵在於上述直流電 位經由緩衝電路供給至上述^分頻比設定部。 又：本發明之半導體積體電路，其特徵在於上述直流電 位係對應上述直流電位之供給端與接地電位之間之電阻值 又’本發明之半導體積體 鼓疋部係伴隨上述基準頻率 準頻率控制信號。 [發明效果] 電路，其特徵在於上述分頻比 之變更而朝特定之電路供給基 世界各國之衛星 根據本發明，能夠以簡便構造實現對應 播放之LNB用半導體積體電路。 【實施方式】 [實施例1] 之半導體積體電路之實施例 參照圖1至4說明關於本發明 圖1係實施例1之丰藤科接触+ y 牛導體積體電路100之方塊圖，圖2至4 係分別顯示實施例1之變形例 βΒΒ 例1至3之方塊圖。首先參照圖1 說明下述之構成與動作。. 156876.doc 201233051 半導體積體電路100係包含分頻比設定電壓端子101、 AD轉換器103、分頻比設定器1〇4、檢波器1〇5、pLL電路 108、及記憶體118。 又’藉由AD轉換器1〇3、分頻比設定器ι〇4與記憶體118 而構成第1分頻比设定部’且’藉由檢波器1 〇 5、分頻比設 定器104與記憶體118構成第2分頻比設定部。 PLL電路108係包含局部振盪器1〇9、可變分頻器11〇、相 位比較器111、電荷泵112與迴路濾波器113而構成。另， 與先前技術文獻相同’局部振盪器1〇9連接於未圖示之混 頻器。 局部振盪器109係可以複數之振盪頻率進行振盪動作之 局部振盤器。又，可變分頻器11〇係將局部振盪器1〇9之輸 出信號以後述之基準頻率之η倍而分頻。 其次’說明半導體積體電路100至取得所期望之局部發 送頻率之動作。另，半導體積體電路1〇〇取得所期望之局 部發送頻率之過程，有使用第1分頻比設定部之情形與使 用第2分頻比設定部之情形之二種，下述按順序予以說 明。 使用第1分頻比設定部之情形，分頻比設定電壓端子1 〇 i 係經由電流源114連接於電源1〇2，又，分頻比設定電壓端 子101與接地電位之間連接有電阻115。 電阻115係一端連接於ad轉換器103之輸入，另一端電 性接地。 又’不限於此，分頻比設定電壓端子1〇1係不經由電流 156876.doc 201233051 源114連接電源102(即電壓源102)亦可，不經由電阻115連 接接地電位亦可。 又，如圖2之變形例1所示，將圖丨中電阻115替換為可變 電阻123亦可，如圖3之變形例2所示替換為開關i24亦可。 再者，如圖4之變形例3所示將電源與分頻比設定電壓端 子101以電阻125連接亦可。 藉由該等之構成，在直流電位之供給端即分頻比設定電 壓端子101，產生對應與基準電位（即接地電位）之間之電阻 值之電壓。 於分頻比設定電壓端子101產生之電壓朝AD轉換器1〇3 被輸入後，轉換為經2值化之信號（2值化信號）。該2值化信 號係輸入至分頻比設定器丨04。 分頻比設定器104係生成控制可變分頻器11〇之分頻比之 分頻比控制信號。於分頻比設定器1〇4中，進行藉由ad轉 換器10 3而2值化之信號與儲存於記憶體丨丨8之分頻比設定 資料的對照。對照之結果，選擇對應於2值化信號之分頻 比《又定-貝料，且將對應於所期望之分頻比之分頻比控制信 號傳送向可變分頻器11〇。 其次，考慮使用第2分頻比設定部之情形。該情形，來 自未圖不之衛星播放調諧器之脈衝信號si〇l被提供至端子 126，由檢波器丨〇5檢波該脈衝信號31〇1，且將對應於脈衝 仏號S101之有無之檢波輸出信號傳送向分頻比設定器 104。上述衛星播放調諧器係例如設置於半導體積體電路 100之外部之調諧器。 156S76.doc 201233051 分頻比設定器1〇4係進行來自檢波器1〇5之檢波輸出信號 與儲存於記憶體Π8之分頻比設定資料之對照，將對應於 脈衝信號S101之有無之分頻比控制信號傳送向可變分頻器 110。 另，藉由第2分頻比設定部進行分頻比設定之情形係 預先將分㈣歧電壓料1()1之„、與料於記憶體 π 8之由第i分頻比設定部將分頻比設定設為無效之設定資 料建立關聯。藉此，亦可預先選擇第2分頻比設定部之分 頻比設定。 經由上述第i或第2分頻比設定後，可變分頻器ιι〇基於 上述第1或第2分頻比設定之任_者所得到之分頻比控制信 號，將分頻輸出信號傳送至相位比較sU1。 相位比較器m係比較可變分頻器11〇之輸出信號、盘使 用經由端子116、117連接於外部之水晶振動子iq6產生特 定之基準頻率之基準信號振1||lG7之信號的相位差。 且’將表示比較後之結果之輪出信號傳送向電荷果ιΐ2。 在電何泵112中’生成對應相位比較器之輸出信號之電 流。迴路濾波器113將自電荷泵112之信號轉換成局部振盪 器⑽之控制電壓。藉此’局部振盪器1〇9以對應來自電荷 泵112之控制信號之振盪頻率而振盪，藉此取得所期望之 局部振盪頻率。 上述係半導體積體電路⑽中，截至取得所期望之局部 振盧頻率為止之-連串之動作。此處，考慮由第ι分頻比 設定部進行之分頻比設定之情形。該情形下，在一般以基 156876.doc •10· 201233051 準頻率之整數倍控制局部振盪器之Integer_N型PLL中，可 變頻率110之分頻比係藉由預先以基準頻率之幾倍設定而 決定。以下，針對基準頻率與分頻比之關係進行說明。 例如，以25 MHz生成基準頻率之情形，藉由分頻比設 定器104之分頻比設定信號，將可變分頻器丨1〇之分頻比設 定為390倍，藉此能夠取得9.75 GHz之振盪頻率。 又，藉由为頻比ax疋器104之分頻比控制信號，將可變 分頻器110之分頻比設定為424倍，藉此能夠取得10.6 GHz 之振盪頻率。 再者，基於各國使用之局部振盪頻率進行具體說明。若 將曰本之CS播放之局部振盪頻率設為25 MHz，則藉由分 周比设定器104之分頻比控制信號，將可變分頻器1丨〇之分 頻比設定為428倍，藉此可取得1〇 7 ghz。 又，考慮設定中國之衛星播放之1〇.75 GHz之局部振盪 頻率之情形。該情形下，相對於基準頻率之25 MHz，藉由 分頻比設定器104之分頻比控制信號，將可變分頻器n〇之 分頻比設定為430倍’藉此能夠取得1〇 75 ghz。 伴隨歐洲之衛星播放之9.75 GHz與10.6 GHz之局部振盪 頻率之切換之設定，則是進行藉由第2分頻比設定部之分 頻比設定。關於該動作，即藉由第2分頻比設定部之分頻 比汉疋，首先，藉由檢波器1〇5檢波自未圖示之衛星播放 調諧器之脈衝信號S101之有無。 此處，無脈衝信號S101之情形，將對應於9 75 GHz之局 部振盪頻率之分頻比控制信號自分頻比設定器104傳送至 156876.doc 201233051 可變分頻器110。另一方面，有脈衝信號81〇1之情形將 對應於10.6 GHz之局部振盪頻率之分頻比控制信號自分頻 比設定器1〇4傳送至可變分頻器u〇。 另，上述說明中’雖以1nteger-N型PLL為例予以說明， 但亦可用於Fractional-Ν型PLL 〇 如上述說明，根據實施例丨，能夠實現以單一之電路規 格對應於世界各國之發送地之LNB帛之半導體積體電路。 如此之半導體積體電路可藉由分頻比設定電壓端子之 知子電壓設定所進行之可變分頻器削之分頻比控制、與 自外之彳《•星播放調谐H傳送來之脈衝信號㈣1所進行之 可變分頻器11 0之分頻比控制而實現。 [實施例2] 其次，參照圖5、6，說明關於本發明之半導體積體電路 之實施例2。 圖5係顯示關於實施例2之半導體積體電路·之方塊 圖’圖6係顯不其變形例，以下說明構成與動作。另，圖 5 6中與實施例丨相同部份係以相同符號表示，又，關於 與實施例1相同部份之說明亦省略。 圖5與圖1之實施例1不同點，係自電流源114經由電流鏡 電路119將電位提供至分頻比設定電壓端子ΗΠ之點。此 處’藉由將電阻115連接於分頻比較電Μ端子ΠΗ與基準 1 〃實施例1同樣能夠設定分頻比設定電壓端子1〇1 又，本實施例中 乃經由電流鏡電路119將電位提供至 156876.doc 201233051 刀頻比6又定電壓101 ’故如變形例之圖6所示亦可直接將分 頻比設定電壓端子1〇1與電源連接。 圖6之變形例之情形，藉由廢除圖5中之電阻丨丨5而能夠 將分頻比设定電壓端子1〇1之電壓設定為電源電壓之電 壓。藉此，除了對應分頻比設定電壓端子1〇1與基準電位 之間之電阻值之電壓值之外，並能夠使電源電壓本身成為 分頻比設定電壓端子1〇1之電壓，故能夠將電壓設定範圍 擴大。因此，能夠擴大分頻比設定部1〇2之分頻比設定範 圍。 [實施例3] 其次，參照圖7說明關於本發明之半導體積體電路之實 施例3。 圖7係顯示實施例3之半導體積體電路3〇〇之方塊圖。 另，圖7中與實施例1、2相同部份係以相同符號表示， 又’關於與實施例1、2相同部份之說明亦省略。 圖7與圖1之實施例1、圖2之實施例2不同點，係將緩衝 電路121設置於分頻比設定電壓端子1〇1與AD轉換器1〇3之 間之點。藉由設置緩衝電路121，存在下述動作狀之有利 點。 若由於任何原因（例如AD轉換器1 〇3之一部份之故障）使 得AD轉換器103之輸入阻抗極端變低之情形，分頻比設定 電壓端子ιοί之電壓會降低至非預期之電壓。即，送往ad 轉換器103之輸入電壓下降，分頻比設定器1〇4以非預期之 分頻比設定信號控制可變分頻器11〇，結果便無法取得所 156876.doc 13 201233051 期望之局部振盪頻率。假設如此之情形’藉由經由輸出阻 抗較低之緩衝電路121驅動AD轉換器1〇3 ’能使AD轉換器 103、分頻比設定器104穩定地動作。 [實施例4] 關於本發明之半導體積體電路之實施例4參照圖8予以說 明。 。 圖8係顯示實施例4之半導體積體電路4〇〇之方塊圖。 另’圖8中與實施例卜2、3相同部份係以相同符號表示， 又，關於與實施例丨、2、3相同部份之說明亦省略。 圖8與圖1之實施例丨、圖5之實施例2、圖了之實施例3不 同點係，自分頻比設定器i 04向其他電路丨22(特定之電 路例如選擇頻率係22 kHz之脈衝信號之切換式電容器或 帶通濾波器電路）供給基準頻率控制信號81〇2之點。藉由 使用基準頻率控制信號3102，存在如下所述之製造上I優 點。 半導體積體電路中，有以複數個電路共用内部之動作用 基準頻率。即，圖8中係其他電㈣2共用使用水晶振動子 106之基準信號振盪器1〇7之基準頻率之情形。 如此情形下，以任一之理由（例如水晶振動子1〇6之一部 伤破損）’考慮將水晶振動子丨〇6之頻率變更至與當初設定 之頻率不同者，使基準頻率變化之情形。該情形，局部= 盪器1 0 9之所期望之振盪頻率雖能夠對應可變分頻器11 〇之 分頻比設定，但其他電路122係藉由變化後之基準頻率而 產生誤動作。 156876.doc 201233051 具體例所示，國内33及110。CS播放之局部振盪頻率係 10.678 GHz。該情形，將基準信號振盪器1〇7之基準頻率 設為19 MHz，以對應此之水晶振動子1〇6生成基準信號， 且分頻比設定器104係將可變分頻器110之分頻比控制為 562倍《藉此，能夠得到所期望之局部振盪頻率之1〇 678 GHz。 另一方面，其他電路122係設定成以25 MHz之基準頻率 動作之情形，藉由基準頻率變為19 MHz*誤動作。因此， 為不發生如此之誤動作，分頻比設定器1〇4係藉由朝其他 電路I22供給基準頻率控制信號S102，而將其他電路122之 動作基準頻率變更至19 MHz，且設定其他電路122係以變 更後之基準頻率動作。 如此之實施例4，因能夠配合可變分頻器丨1〇之分頻比設 定而決定基準信號振盪器107之基準頻率，故能夠提升水 晶振動子選擇之自由度。 [產業上之可利用性] 如上所說明，本發明之半導體積體電路可以簡便之構成 較佳適用於對應世界各國之播放頻率之LNB。又，亦能夠 廣泛適用於全體使用PLL之頻率合成器方式之半導體積體 電路。 【圖式簡單說明】 圖1係顯示本發明之實施例丨之半導體積體電路之方塊 圖。 圖2係顯示貫施例1之變形例1之方塊圖。 156876.doc 15 201233051 圖3係顯示實施例1之變形例2之方塊圖 圖4係顯示實施例1之變形例3之方塊圖 導體積體電路之方塊 圖5係顯示本發明之實施例2之半Therefore, for example, 156876.doc 201233051 10.678 GHz of the local oscillation frequency of the quotient of the Japanese 箄 本 本 本 本 有 有 330 330 330 330 330 330 330 330 330 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Therefore, when the frequency of each transmission destination is not set in the manufacturing stage, and the reception environment of the satellite broadcasting antenna is set up, the local oscillation frequency setting of the LNB is performed by the user, and there is a case where the loss is convenient. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a semiconductor integrated circuit which is simple and low-cost, and which is capable of obtaining a local oscillation signal corresponding to satellite broadcasting in various countries. [Means for Solving the Problem] The semiconductor integrated circuit of the present invention includes the following: a local oscillator capable of performing an oscillation operation at a plurality of oscillation frequencies; and a reference signal oscillating at a specific reference frequency oscillation And a variable frequency divider that divides an output signal of the local oscillator by n times the reference frequency; and: controls a frequency division ratio of the variable frequency divider corresponding to the supplied DC potential a first frequency division ratio setting unit; and a second frequency division ratio setting unit that controls a frequency division ratio of the variable frequency divider corresponding to the presence or absence of the supplied pulse signal; and the second division ratio setting unit Or the frequency division ratio control of the variable frequency divider of the second frequency division ratio setting unit sets the oscillation frequency of the local oscillator to a desired frequency. Further, in the semiconductor integrated circuit of the present invention, the first frequency division ratio setting unit includes an AD converter that converts the DC potential into a binary signal, and stores || The ratio data and the frequency ratio setting unit generate the frequency division ratio control signal of the variable frequency divider from the binarized signal and the frequency division ratio setting data. Further, the semiconductor integrated circuit of the present invention is characterized in that the second 156876.doc 201233051 frequency division ratio setting unit includes a detector that detects the pulse signal and the memory unit to store the frequency division ratio data; And a frequency division ratio setting unit that generates a frequency division ratio control signal of the variable frequency divider from the detection output signal of the detector and the frequency division ratio setting data. Further, the semiconductor integrated circuit of the present invention is characterized in that the DC potential is supplied to the ith division ratio setting unit via a current mirror circuit. Further, in the semiconductor integrated circuit of the present invention, the DC potential is supplied to the division ratio setting unit via a buffer circuit. Further, the semiconductor integrated circuit of the present invention is characterized in that the DC potential corresponds to a resistance value between the supply terminal of the DC potential and a ground potential, and the semiconductor integrated body drum portion of the present invention is accompanied by the reference frequency quasi frequency. control signal. [Effect of the Invention] The circuit is characterized in that the satellite is supplied to a specific circuit in accordance with the change of the frequency dividing ratio. According to the present invention, the semiconductor integrated circuit for LNB corresponding to the playback can be realized in a simple configuration. [Embodiment] Embodiment of a semiconductor integrated circuit of Embodiment 1 Referring to Figs. 1 to 4, a block diagram of a Toyoko contact + y bovine volume body circuit 100 of Embodiment 1 of the present invention will be described. 2 to 4 are block diagrams showing the modifications of the first embodiment of Examples 1 to 3, respectively. First, the following configuration and operation will be described with reference to Fig. 1 . 156876.doc 201233051 The semiconductor integrated circuit 100 includes a frequency division ratio setting voltage terminal 101, an AD converter 103, a frequency dividing ratio setter 1〇4, a detector 1〇5, a pLL circuit 108, and a memory 118. Further, 'the first frequency division ratio setting unit' is formed by the AD converter 1〇3, the frequency division ratio setter ι〇4, and the memory 118, and 'by the detector 1 〇5, the frequency division ratio setter 104 The memory 118 constitutes a second frequency division ratio setting unit. The PLL circuit 108 includes a local oscillator 1〇9, a variable frequency divider 11A, a phase comparator 111, a charge pump 112, and a loop filter 113. Further, the same as the prior art document, the local oscillator 1〇9 is connected to a mixer not shown. The local oscillator 109 is a local vibrator that can oscillate at a plurality of oscillation frequencies. Further, the variable frequency divider 11 is divided by dividing the output frequency of the local oscillator 1 〇 9 by n times the reference frequency described later. Next, the operation of the semiconductor integrated circuit 100 to obtain a desired partial transmission frequency will be described. In addition, the process of obtaining the desired partial transmission frequency by the semiconductor integrated circuit 1 is used in the case of using the first division ratio setting unit and the case of using the second division ratio setting unit, and the following is sequentially performed. Description. When the first frequency division ratio setting unit is used, the frequency division ratio setting voltage terminal 1 〇i is connected to the power source 1〇2 via the current source 114, and a resistor 115 is connected between the frequency dividing ratio setting voltage terminal 101 and the ground potential. . The resistor 115 has one end connected to the input of the ad converter 103 and the other end electrically grounded. Further, the present invention is not limited thereto, and the frequency dividing ratio setting voltage terminal 1〇1 does not pass through the current source 156876.doc 201233051. The source 114 may be connected to the power source 102 (that is, the voltage source 102), and may be connected to the ground potential without the resistor 115. Further, as shown in the first modification of Fig. 2, the resistor 115 may be replaced with the variable resistor 123, and may be replaced with the switch i24 as shown in the second modification of Fig. 3. Further, as shown in the third modification of Fig. 4, the power supply and the frequency division ratio setting voltage terminal 101 may be connected by the resistor 125. With these configurations, the voltage terminal 101 is set at the frequency-dividing ratio of the supply terminal of the DC potential, and a voltage corresponding to the resistance value between the reference potential (i.e., the ground potential) is generated. The voltage generated by the frequency dividing ratio setting voltage terminal 101 is input to the AD converter 1〇3, and then converted into a binarized signal (binarized signal). The binary signal is input to the division ratio setter 丨04. The frequency division ratio setter 104 generates a frequency division ratio control signal that controls the frequency division ratio of the variable frequency divider 11A. In the frequency division ratio setter 1 to 4, the signal binarized by the ad converter 103 is compared with the frequency division ratio setting data stored in the memory port 8. As a result of the comparison, the frequency division ratio corresponding to the binary signal is selected, and the frequency division ratio control signal corresponding to the desired frequency division ratio is transmitted to the variable frequency divider 11A. Next, consider the case where the second division ratio setting unit is used. In this case, the pulse signal si〇1 from the satellite playback tuner, which is not shown, is supplied to the terminal 126, and the pulse signal 31〇1 is detected by the detector 丨〇5, and the detection corresponding to the presence or absence of the pulse number S101 is detected. The output signal is transmitted to the division ratio setter 104. The satellite broadcast tuner described above is, for example, a tuner provided outside the semiconductor integrated circuit 100. 156S76.doc 201233051 The division ratio setter 1〇4 compares the detection output signal from the detector 1〇5 with the division ratio setting data stored in the memoryΠ8, and divides the frequency corresponding to the presence or absence of the pulse signal S101. The ratio control signal is transmitted to the variable frequency divider 110. In the case where the frequency division ratio setting unit is set by the second frequency division ratio setting unit, the (i)th voltage material 1()1 is prepared in advance, and the ith frequency division ratio setting unit of the memory π 8 is used. The setting of the frequency division ratio setting is invalid, and the frequency division ratio setting of the second frequency division ratio setting unit can be selected in advance. After the setting of the ith or second frequency division ratio, the variable frequency division is performed. The ιι 传送 transmits the divided output signal to the phase comparison sU1 based on the frequency division ratio control signal obtained by any of the first or second frequency division ratio settings. The phase comparator m is a comparison variable frequency divider 11 The output signal of the cymbal and the disk use the crystal vibrator iq6 connected to the outside via the terminals 116 and 117 to generate a phase difference of the signal of the reference signal 1_|1G7 of the specific reference frequency. And 'will show the result of the comparison. The signal is transmitted to the charge ΐ2. In the electric pump 112, a current corresponding to the output signal of the phase comparator is generated. The loop filter 113 converts the signal from the charge pump 112 into a control voltage of the local oscillator (10). Oscillator 1〇9 to correspond to charge pump 112 The oscillation frequency of the control signal is oscillated to obtain a desired local oscillation frequency. In the above-described semiconductor integrated circuit (10), a series of operations up to the desired local oscillation frequency is obtained. The case where the division ratio is set by the ι division ratio setting unit. In this case, the variable frequency 110 is used in the Integer_N type PLL which generally controls the local oscillator with an integral multiple of the basis 156876.doc •10·201233051 The frequency division ratio is determined by setting the reference frequency several times in advance. Hereinafter, the relationship between the reference frequency and the frequency division ratio will be described. For example, when the reference frequency is generated at 25 MHz, the frequency division ratio setter 104 is used. The frequency division ratio setting signal sets the frequency division ratio of the variable frequency divider 3901〇 to 390 times, thereby obtaining an oscillation frequency of 9.75 GHz. Moreover, by dividing the frequency ratio of the frequency ratio ax processor 104 The control signal is set to 424 times the division ratio of the variable frequency divider 110, whereby an oscillation frequency of 10.6 GHz can be obtained. Further, the local oscillation frequency used in each country will be specifically described. When the local oscillation frequency of the playback is set to 25 MHz, the division ratio of the variable frequency divider 1丨〇 is set to 428 times by the division ratio control signal of the peripheral ratio setter 104, thereby obtaining 1 〇7 ghz. Also, consider setting the local oscillation frequency of 1〇.75 GHz played by satellites in China. In this case, the division ratio of the division ratio setter 104 is controlled with respect to 25 MHz of the reference frequency. The signal, the division ratio of the variable frequency divider n〇 is set to 430 times', thereby achieving 1〇75 ghz. The setting of the switching between the local oscillation frequencies of 9.75 GHz and 10.6 GHz accompanying the satellite broadcasting in Europe is The division ratio setting by the second frequency division ratio setting unit is performed. With regard to this operation, that is, by the frequency division ratio of the second frequency division ratio setting unit, first, the presence or absence of the pulse signal S101 of the tuner is detected by the detector 1〇5 from the satellite (not shown). Here, in the case of the pulseless signal S101, the frequency division ratio control signal corresponding to the local oscillation frequency of 9 75 GHz is transmitted from the frequency division ratio setter 104 to the 156876.doc 201233051 variable frequency divider 110. On the other hand, in the case of the pulse signal 81〇1, the division ratio control signal corresponding to the local oscillation frequency of 10.6 GHz is transmitted from the division ratio setter 1〇4 to the variable frequency divider u〇. In the above description, the 1Nteger-N type PLL is described as an example, but it can also be applied to a Fractional-Ν type PLL. As described above, according to the embodiment, it is possible to transmit to a world by a single circuit specification. The semiconductor integrated circuit of LNB帛. Such a semiconductor integrated circuit can be controlled by a frequency divider ratio of a frequency divider which is set by a voltage divider of a frequency dividing ratio setting terminal, and a pulse signal transmitted from a star to the "Star playback tuning H". (4) The frequency division ratio control of the variable frequency divider 110 performed by one is realized. [Embodiment 2] Next, a second embodiment of a semiconductor integrated circuit according to the present invention will be described with reference to Figs. Fig. 5 is a block diagram showing a semiconductor integrated circuit of the second embodiment. Fig. 6 shows a modification thereof. The configuration and operation will be described below. In addition, the same portions as those in the embodiment are denoted by the same reference numerals in Fig. 56, and the description of the same portions as those in the first embodiment is also omitted. Fig. 5 differs from the first embodiment of Fig. 1 in that a potential is supplied from the current source 114 via the current mirror circuit 119 to the point of the division ratio setting voltage terminal ΗΠ. Here, by connecting the resistor 115 to the frequency division comparator terminal ΠΗ, the frequency division ratio setting voltage terminal 1〇1 can be set in the same manner as in the first embodiment. In the present embodiment, the potential is set via the current mirror circuit 119. Provided to 156876.doc 201233051 The tool-to-frequency ratio is 6 and the voltage is 101'. Therefore, as shown in FIG. 6 of the modification, the frequency-divided ratio setting voltage terminal 1〇1 can be directly connected to the power source. In the case of the modification of Fig. 6, the voltage of the frequency division ratio setting voltage terminal 1?1 can be set to the voltage of the power source voltage by abolishing the resistor 丨丨5 in Fig. 5. Thereby, in addition to the voltage value of the resistance value between the voltage terminal 1〇1 and the reference potential corresponding to the frequency division ratio setting, the power supply voltage itself can be set to the voltage of the frequency division ratio setting voltage terminal 1〇1, so that it is possible to The voltage setting range is expanded. Therefore, the division ratio setting range of the division ratio setting unit 1〇2 can be expanded. [Embodiment 3] Next, Embodiment 3 of the semiconductor integrated circuit of the present invention will be described with reference to Fig. 7 . Fig. 7 is a block diagram showing a semiconductor integrated circuit 3 of the embodiment 3. In the same manner as in the first and second embodiments, the same portions as those in the first and second embodiments are denoted by the same reference numerals, and the description of the same portions as those in the first and second embodiments will be omitted. Fig. 7 differs from the first embodiment of Fig. 1 and the second embodiment of Fig. 2 in that the buffer circuit 121 is provided between the division ratio setting voltage terminal 1〇1 and the AD converter 1〇3. By providing the buffer circuit 121, there is an advantage of the following operation. If the input impedance of the AD converter 103 is extremely low for any reason (e.g., failure of one of the AD converters 1 〇 3), the voltage of the frequency division setting voltage terminal ιοί is lowered to an unexpected voltage. That is, the input voltage to the ad converter 103 drops, and the frequency division ratio setter 1〇4 controls the variable frequency divider 11〇 with an unexpected frequency division ratio setting signal, and as a result, the 156876.doc 13 201233051 expectation cannot be obtained. The local oscillation frequency. It is assumed that the AD converter 103 and the frequency division ratio setter 104 can be stably operated by driving the AD converter 1?3' via the buffer circuit 121 having a lower output impedance. [Embodiment 4] Embodiment 4 of the semiconductor integrated circuit of the present invention will be described with reference to Fig. 8. . Fig. 8 is a block diagram showing the semiconductor integrated circuit 4 of the fourth embodiment. In the same manner, the same portions as those in the embodiments 2 and 3 are denoted by the same reference numerals, and the descriptions of the same portions as those in the embodiments 丨, 2, and 3 are also omitted. 8 is different from the embodiment of FIG. 1, the embodiment 2 of FIG. 5, and the third embodiment of the embodiment, and the self-dividing ratio setting unit i 04 is connected to the other circuit 22 (the specific circuit, for example, the frequency system 22 kHz is selected. The switching capacitor or band pass filter circuit of the pulse signal is supplied to the point of the reference frequency control signal 81〇2. By using the reference frequency control signal 3102, there is a manufacturing I advantage as described below. In the semiconductor integrated circuit, a plurality of circuits share an internal operational reference frequency. That is, in Fig. 8, the other electric (four) 2 shares the reference frequency of the reference signal oscillator 1〇7 of the crystal vibrator 106. In such a case, for any reason (for example, one of the crystal vibrators 1〇6 is damaged), consider changing the frequency of the crystal vibrator 丨〇6 to a frequency different from the originally set frequency, and changing the reference frequency. . In this case, the desired oscillation frequency of the local = sigma 1 0 9 can be set corresponding to the division ratio of the variable frequency divider 11 ,, but the other circuit 122 generates a malfunction by the changed reference frequency. 156876.doc 201233051 Specific examples show domestic 33 and 110. The local oscillation frequency of CS playback is 10.678 GHz. In this case, the reference frequency of the reference signal oscillator 1〇7 is set to 19 MHz, the reference signal is generated corresponding to the crystal vibrator 1〇6, and the frequency division ratio setter 104 divides the variable frequency divider 110. The frequency ratio control is 562 times. Thereby, the desired local oscillation frequency of 1 〇 678 GHz can be obtained. On the other hand, the other circuit 122 is set to operate at a reference frequency of 25 MHz, and the reference frequency becomes 19 MHz* malfunction. Therefore, in order not to cause such a malfunction, the frequency division ratio setter 1〇4 changes the operation reference frequency of the other circuit 122 to 19 MHz by supplying the reference frequency control signal S102 to the other circuit I22, and sets other circuits 122. It operates with the changed reference frequency. In the fourth embodiment as described above, since the reference frequency of the reference signal oscillator 107 can be determined in accordance with the frequency division ratio setting of the variable frequency divider ,1, the degree of freedom in selecting the crystal oscillator can be improved. [Industrial Applicability] As described above, the semiconductor integrated circuit of the present invention can be easily configured to be suitably applied to LNBs corresponding to the broadcasting frequencies of countries in the world. Further, it can be widely applied to a semiconductor integrated circuit in which a frequency synthesizer system using a PLL is used. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a semiconductor integrated circuit of an embodiment of the present invention. Fig. 2 is a block diagram showing a modification 1 of the first embodiment. FIG. 3 is a block diagram showing a modified example 2 of the first embodiment. FIG. 4 is a block diagram showing a block diagram of a modified example 3 of the first embodiment. FIG. 5 is a view showing a second embodiment of the present invention. half
圖6係顯示實施例2之變形例之方塊圖。Fig. 6 is a block diagram showing a modification of the second embodiment.
圖7係顯示本發明之實施例3之 半導體積體電路之方塊 導體積體電路之方塊 圖8係顯示本發明之實施例4之半Figure 7 is a block diagram showing a block conductor circuit of a semiconductor integrated circuit of Embodiment 3 of the present invention. Figure 8 is a half of Embodiment 4 of the present invention.
圖9係顯示先前之LNB之方塊圖。 圖10係顯示先前之半導體積體電路之方塊圖。 【主要元件符號說明】 100 半導體積體電路 101 分頻比設定電壓端子 102 電源 103 AD轉換器 104 分頻比設定器 105 檢波器 106 水晶振動子 107 基準彳§破振盈器 108 PLL電路 109 局部振盪器 110 可變分頻器 111 相位比較器 I56876.doc 201233051 112 電荷泵 113 迴路濾波器 114 電流源 115 電阻 116 端子 117 端子 118 記憶體 119 電流鏡電路 120 電流源 121 緩衝電路 122 其他電路 123 可變電阻 124 開關 125 電阻 126 端子 127 端子 200 半導體積體電路 201 LNB 202 混頻器 203 局部振盪器 204 局部振盪器 205 切換電路 300 半導體積體電路 301 衛星播放調諧器 156876.doc -17- 201233051 400 半導體積體電路 401 半導體積體電路 402 混頻益 403 局部振盪器 404 PLL電路 405 低通遽波器 406 通道選擇部 S101 脈衝信號 S102 基準頻率控制信號 S203 脈衝信號 156876.doc -18-Figure 9 is a block diagram showing the previous LNB. Figure 10 is a block diagram showing a prior semiconductor integrated circuit. [Main component symbol description] 100 Semiconductor integrated circuit 101 Frequency division ratio setting voltage terminal 102 Power supply 103 AD converter 104 Frequency division ratio setter 105 Detector 106 Crystal vibrator 107 Reference 彳 破 振 振 108 108 108 109 109 109 109 Oscillator 110 Variable Frequency Divider 111 Phase Comparator I56876.doc 201233051 112 Charge Pump 113 Loop Filter 114 Current Source 115 Resistor 116 Terminal 117 Terminal 118 Memory 119 Current Mirror Circuit 120 Current Source 121 Buffer Circuit 122 Other Circuit 123 Variable Resistor 124 Switch 125 Resistor 126 Terminal 127 Terminal 200 Semiconductor Integral Circuit 201 LNB 202 Mixer 203 Local Oscillator 204 Local Oscillator 205 Switching Circuit 300 Semiconductor Integral Circuit 301 Satellite Play Tuner 156876.doc -17- 201233051 400 Semiconductor integrated circuit 401 semiconductor integrated circuit 402 mixed frequency 403 local oscillator 404 PLL circuit 405 low pass chopper 406 channel selection unit S101 pulse signal S102 reference frequency control signal S203 pulse signal 156876.doc -18-