WO2012086288A1 - Exception control method, system, and program - Google Patents

Abstract

In order to realise exceptions which can be controlled by means of software, the present invention provides a method for implementing program control of exceptions, said method including a processor executing the following steps: a step in which a control specification command for specifying exception control with regard to whether or not an exception is enabled is executed, and an exception control specification value is set in a register; a step in which a control execution command for executing exception control with regard to whether or not an exception is generated is executed, it is determined whether or not the control specification value set in the register is a value that enables an exception, and an exception is generated when the control specification value is a value that enables an exception; and a step in which an exception is not generated when the control specification value set in the register is not a value that enables an exception.

Description

Exception control method, system and program

The present invention relates to exception control, and more particularly, to a method, system, and computer program for program-controlling exceptions.

In the current CPU, when a hardware error occurs or an access violation occurs during execution of a CPU instruction, a CPU exception occurs. When a CPU exception occurs, an interrupt occurs and the exception handling code at the specified address is executed. When the exception processing is completed, execution returns to the position of the CPU instruction where the exception occurred. However, in the case of a fatal error or special case, it may not return to the position where the exception occurred.

There are various types of CPU exceptions, such as runtime errors, TLB (Translation Look-aside Buffer) errors, timer interrupts, etc., but the usage and exception conditions are all determined in advance. Conditions cannot be changed flexibly in terms of software, that is, program control cannot be performed. That is, most exceptions are not intentionally generated at the location specified by the programmer.

System call used to call privileged mode code from non-privileged mode code, or PowerPC that determines whether an exception is generated by comparing the values of two registers, for example (PowerPC is a registered trademark of IBM Corporation) The trap command (tw command) can raise an exception at the specified position. However, in the case of a system call, an exception always occurs, and the exception cannot be invalidated. In the case of the trap instruction described above, processing for obtaining the values of two registers before execution and execution A register comparison / determination process is required.

Besides, there is a conditional branch instruction as a CPU instruction. This reflects the state to be determined as a register value before calling a branch instruction. Whether or not to branch depends on the value. Therefore, a conditional branch instruction requires an operation on a volatile register in advance, and the conditional branch instruction itself is always executed even if it does not branch.

In computer programs, it is often desirable to perform special processing only when certain conditions are met. In that case, conditional branch instructions are usually used. That is, a procedure is performed in which some operation is performed by the CPU instruction to update the value of the register, and the jump to the processing code is performed by the conditional branch instruction according to the value. However, it is inefficient to check the condition that is met only rarely by software.

FIG. 1 illustrates a conditional branch instruction 10 of a condition that is rarely established according to the prior art. In task A, it is rarely necessary to call the initialization function init () only for the first time and at the time of calling func () after reset (), and init () can only be called from the same process space as task B. . As described above, it is necessary to check whether the reset state is performed before performing a certain process, and if so, an initialization process must be performed. The time spent is wasted every time. In particular, when the process for determining whether or not the task B is in the reset state is viewed at the assembler language level shown on the right side, it can be seen that even a slight determination consumes a considerable amount of time due to memory access. For example, the rst_f variable is the variable at the address pointed to by the pointer variable of the structure member, that is, the memory is referred to many times, and the conditional expression is if or (A or B or C ...) If connected with or, the consumption time will be longer.

Patent Document 1 scans an exception handling handler registration list registered by an exception handling handler registration means in an exception handling control system that shifts the process to an exception handling procedure indicated by “CALL” or another instruction word. Thus, it is described that the exception processing is transferred to the exception processing handler corresponding to the exception condition identifier directly, thereby speeding up the exception processing by speeding up the propagation to the exception processing.

In Patent Document 2, an address setting means for setting an interrupt address for each interrupt factor in an area other than the instruction memory, and a factor detected by the interrupt detection circuit as a selection signal, the output of the address setting unit is input to a program counter. To reduce the consumption of program memory required for branch instructions, eliminate invalid space in the program memory, improve the efficiency of the program memory, and shorten the interrupt processing time A microprocessor capable of being described is described.

In Patent Document 3, a normal processing program and a plurality of exception processing handler programs, as well as the execution state and exception status of a normal processing program that needs to be selected and executed in advance, are coded in advance for each exception processing handler. Prepared for each exception handler and added as information in the program code. When an exception is detected, the execution status of the normal program when the exception is detected and the execution of the normal processing program attached to each exception handler Describes an exception handling mechanism in which the presence or absence of an exception handling handler does not affect the processing amount of a normal processing program by selecting an exception handling handler and performing execution control by comparing with status information .

JP-A-62-212732 Japanese Patent Laid-Open No. 4-169937 JP 7-44398 A

So far, if preset, exceptions always occur and conditional branch instructions themselves are always executed. In other words, no exceptions are generated or conditional branch instructions themselves are not executed, and they are not controlled by software, and processing operations that are not actually required are also performed. It is done by the program.

The present invention aims to realize an exception that can be controlled by software. Objects of the present invention include providing methods, systems and computer programs for programmatic control of exceptions.

The exceptional program control method according to an embodiment of the present invention includes a processor executing the following steps. In other words, a step of executing a control designation command for designating an exception control whether or not to enable an exception, setting an exception control designation value in a register, and executing an exception control whether or not to generate an exception A control execution instruction for determining whether or not the specified control value set in the register is a value that enables the exception, and generating an exception if the specified control value is a value that enables the exception It is. In addition, when the control designation value set in the register is not a value that enables the exception, a step that does not cause an exception is executed.

Preferably, the control designation instruction has a bitmap index part and a control designation part, the register includes a bitmap register, and the step of setting the control designation value is the bitmap specified by the value of the bitmap index part Executing a step of setting a value of the control designating part to a bit of the register.

Preferably, the control execution instruction has a bitmap index portion, and in the step of generating an exception, the value of the control designation portion set in the bit of the bitmap register specified by the value of the bitmap index portion causes an exception. Including executing an exception-generating step when the value is valid.

Preferably, the register includes a return address register, and the step of generating an exception includes executing a step of setting a next address of the control execution instruction in the return address register.

Preferably, the control execution instruction has a key code part, the register has a key register, and the step of generating an exception sets the value of the key code part in the key register for use in the exception to be generated Performing the step of performing.

Preferably, the register includes a vector base register, and the step of generating an exception includes an exception held in the vector base register associated with the bit of the bitmap register specified by the value of the bitmap index part of the control execution instruction. It includes the step of referring to the address of the handler and jumping to the exception handler at that address.

Preferably, in the step of not generating an exception, when the value of the control designation part set to the bit of the bitmap register specified by the value of the bitmap index part of the control execution instruction is not a value that enables the exception, the exception is Performing non-occurring steps. The step of not generating an exception includes executing a step of discarding the control execution instruction in the instruction queue.

According to one embodiment of the present invention, there is provided a computer program for controlling an exception program that causes a processor to execute each step of the above method.

In an exception program control system according to an embodiment of the present invention, a processor controls a control designation instruction for designating an exception control whether to enable an exception and a control for executing exception control whether to generate an exception. An exception control unit that executes an execution instruction and controls an exception is included. The exception control unit executes a register, a control designation instruction, sets a control designation value of the exception in the register, and executes a control execution instruction, and the control designation value set in the register A control execution instruction processing unit that determines whether or not the exception is valid, and generates an exception when the specified control value is a value that validates the exception. The control execution instruction processing unit does not generate an exception when the control designation value set in the register is not a value that enables the exception.

Preferably, the control designation instruction has a bitmap index part and a control designation part, the register includes a bitmap register, and the control designation instruction processing part is stored in the bitmap register specified by the value of the bitmap index part. Set the value of the corresponding control specification part in the bit.

Preferably, the control execution instruction has a bitmap index section, and the control execution instruction processing section has an exception when the value of the control designation section set in the bit of the bitmap register specified by the value of the bitmap index section is an exception. Raise an exception when the value is valid.

Preferably, the register includes a return address register, and the control execution instruction processing unit sets the next address of the control execution instruction in the return address register.

Preferably, the control execution instruction has a key code part, the register includes a key register, and the control execution instruction processing part sets the value of the key code part in the key register for use in the generated exception. To do.

Preferably, the register includes a vector base register, and the control execution instruction processing unit includes an exception held in the vector base register associated with the bit of the bitmap register specified by the value of the bitmap index part of the control execution instruction. Refers to the handler address and jumps to the exception handler at that address.

Preferably, the control execution instruction processing unit outputs an exception when the value of the control designation unit set in the bit of the bitmap register specified by the value of the bitmap index part of the control execution instruction is not a value that enables the exception. Do not generate.

According to the present invention, an exception that cannot be generated or controlled by software is realized, and a method, a system, and a computer program for program-controlling the exception are provided. In particular, the occurrence of an exception can be controlled flexibly, that is, at a place set by a program, unnecessary processing operations by the CPU can be suppressed, and the processing efficiency of the CPU can be improved.

It is the schematic of the program which illustrates the conditional branch instruction of the condition which is satisfied very rarely by the prior art. FIG. 1 is a schematic configuration diagram of two types of CPU instructions newly provided for realizing software-controllable exceptions, a bitmap register indexed by the CPU instructions, and three types of registers corresponding to each exception in an embodiment of the present invention. It is. 1 is a block diagram schematically showing a processor having an exception program control system according to an embodiment of the present invention. FIG. It is a flowchart figure which shows schematically the exception program control method which concerns on one Embodiment of this invention. It is the schematic of the example of a program produced in order to implement the exception program control method concerning one Embodiment of this invention. It is the schematic of another example of a program created in order to implement the exception program control method concerning one embodiment of the present invention. It is the schematic of another example of a program created in order to implement the exception program control method concerning one embodiment of the present invention. It is the schematic of another example of a program created in order to implement the exception program control method concerning one embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. However, the following embodiments do not limit the invention according to the claims, and are described in the embodiments. Not all combinations of features that are present are essential to the solution of the invention. The present invention may be implemented in many different ways and should not be construed as limited to the details of the described embodiments. Note that the same reference numerals are given to the same components or components throughout the description of the embodiment.

First, FIG. 2 shows two types of CPU instructions newly provided for realizing software-controllable exceptions in one embodiment of the present invention, a bitmap register indexed to the CPU instructions, and three types corresponding to each exception. 1 shows a schematic configuration of the register. Of the two types of CPU instructions, the control designation instruction 11 indicated as one of the expand instructions is provided to enable or disable (invalidate) exceptions, that is, to specify exception control. The control execution instruction 12 indicated as the other expc instruction is provided to cause an exception not to be generated according to the exception validity / invalidity condition, that is, to execute the exception control. A bitmap register 20 indicated as a BM register is provided to define conditions for occurrence of an exception by being indexed by two types of CPU instructions.

Of the three types of registers, a plurality of vector base registers 21 indicated as VEC registers respectively hold exception handler addresses addr for handling exceptions generated by two types of CPU instructions, Support startup. A return address register 22 indicated as a RET register holds a return address raddr next to the CPU instruction in which the exception has occurred, and supports return from exception processing by the CPU. Each of the key registers 23 indicated as the KEY register holds a value kc designated by the program when the exception occurs, for example, the KC value of the expc instruction, and supports use in exception processing by the CPU. The number of VEC registers 21 corresponding to the number of exceptions processed by two types of CPU instructions is provided. In FIG. 2, 256 VEC registers 21 are provided. On the other hand, one RET register 22 and one KEY register 23 are provided as long as they can handle two types of CPU instructions.

The control instruction 11 is shown in a 32-bit configuration, but is not limited to a 32-bit configuration. The opcode part written as OP of bits 0 to 5 indicates that this CPU instruction is an instruction that does not enable (invalidate) an exception or designates exception control. A bitmap index portion labeled BM of bits 8 to 15 indicates an index to the 256-bit BM register 20 provided for determining whether or not to generate an exception for each of 256 ways that can be represented by 8 bits. For example, if all the bits 8 to 15 of the BM are 0, the first bit of the BM register 20 is indicated, and if all the bits 8 to 15 of the BM are 1, the last 256 bits of the BM register 20 are indicated. The control specification part marked as EN in bit 31 does not enable (disable) the exception, that is, when EN is 1, the exception is enabled, and when EN is 0, the exception is enabled. Indicates a value that is not to be set (disabled). Of course, the EN value can be reversed so that the exception is enabled when EN is 0 and is not enabled (disabled) when EN is 1. The value of this EN is set in the bit of the BM register 20 that is associated with the value specified by the BM, that is, indexed. For example, expen 20, 1 which is an execution example of this instruction has BM = 20 and EN = 1, and therefore EN = 1 which enables the exception is set in the 21st bit of the BM register 20.

The control execution instruction 12 is also shown in a 32-bit configuration, but is not limited to a 32-bit configuration. The opcode portion labeled OP of bits 0 to 5 indicates that this CPU instruction is an instruction that does not cause an exception or executes an exception control. The bitmap index part indicated as BM of bits 8 to 15 is provided with 256 bits for determining whether or not to generate an exception for each of 256 ways represented by 8 bits, as in the case of the control designation instruction 11. The index to the BM register 20 is shown. When EN = 1 is set to the indexed bit of the BM register 20 by the expand instruction of the control designation instruction 11, an address addr of the VEC register 21 associated with the indexed bit in the BM register 20 is generated. Is jumped to the address addr of the exception handler specified there, and exception processing is executed. Further, the address next to this instruction is set in the RET register 22 as a return address raddr for returning from exception processing. The key code part written as KC in bits 16 to 31 is a data field that is set and used in the program, and the value of KC is stored in the KEY register 23.

For example, expc 20, 512, which is an execution example of this instruction, refers to the 21st bit of the BM register 20 because BM = 20 and KC = 512. If EN = 0, do nothing. If there is EN = 1, an exception is generated. In particular, in order to transfer the execution to the exception handler, the program jumps to the exception handler address addr designated by the 21st VEC register 21. Further, the next address of the expc instruction, that is, the return address raddr is set in the RET register 22. Further, 512 is set as a kc value in bits 16 to 31 of the KEY register 23. The designated exception handler performs processing according to the kc value 512. Since the value of kc can be freely set by a program, not only does not cause an exception, but also the processing of the exception handler itself can be flexibly controlled. When the processing by the exception handler is completed, it is possible to return to the processing immediately after the occurrence of the exception by referring to the return address raddr stored in the RET register 22 using a CPU instruction for returning from the exception provided by the CPU architecture. it can.

FIG. 3 is a block diagram schematically showing a processor 100 having an exceptional program control system according to an embodiment of the present invention. The processor 100 includes a cache 110 and an MMU (Memory Management Unit) 120, and the MMU 120 includes a TLB 125. In addition to the branch processing unit 130 for branch processing and the instruction queue 140 for storing instructions, the processor 100 is provided with an exception control unit 135 that newly controls an exception. In addition to the registers including the BM register 20, the VEC register 21, the RET register 22, and the KEY register 23, the exception control unit 135 is provided in the control designation instruction processing unit 30 that processes the control designation instruction 11 provided in the program and also in the program. A control execution instruction processing unit 40 for processing the control execution instruction 12 to be executed.

The control designation command processing unit 30 includes a BM processing unit 31 and an EN processing unit 32. The BM processing unit 31 acquires a value designated by the BM from the control designation instruction 11 and specifies a bit of the BM register 20 that is associated with, or indexed to, the value. The EN processing unit 32 acquires the value specified by EN from the control specifying instruction 11 and sets the value to the bit of the BM register 20 specified by the BM processing unit 31.

The control execution command processing unit 40 includes a BM processing unit 41, an EN determination unit 42, and a KC processing unit 43. The BM processing unit 41 acquires a value specified by the BM of the control execution instruction 12 and specifies a bit of the BM register 20 that is associated with the value, that is, indexed. The EN determination unit 42 determines the value of EN set in the bit of the BM register 20 specified by the BM processing unit 41. When EN is 0 that does not enable (invalidate) an exception, control execution is performed. The instruction processing unit 40 ends the process. Therefore, the exception processing is not executed, and the control execution instruction 12 is removed from the instruction queue 140. When EN is 1 to enable the exception, the control execution instruction processing unit 40 refers to the address addr of the VEC register 21 associated with the bit of the BM register 20 specified by the BM processing unit 41, and performs branch processing. The unit 130 jumps to the exception handler at the address addr and executes exception processing. Further, the control execution instruction processing unit 40 adds the address obtained by adding 4 to the address of the control execution instruction 12 to the address of the control execution instruction 12, for example, to the RET register 22 as a return address raddr for return from exception processing. set. When returning from exception processing, the exception control unit 135 provides the return address raddr to the branch processing unit 130. Further, in the control execution instruction processing unit 40, the KC processing unit 43 stores the KC value of the control execution instruction 12 in the KEY register 23. The exception control unit 135 provides the value of kc stored in the KEY register 23 to the exception handler, and the exception handler performs processing according to the value of kc.

FIG. 4 is a flowchart (200) schematically showing the exceptional program control method according to the embodiment of the present invention. This method can be implemented in a processor 100 in which exceptions as shown in FIG. 3 are controlled by software. The processor 100 starts when the control designation instruction 11 is provided to the instruction queue 140 (step 201). The processor 100 acquires BM and EN from the control designation instruction 11 (step 202), sets the value of EN to the bit of the BM register 20 specified by BM (step 203), and ends (step 204). Also, the processor 100 starts when the control execution instruction 12 is provided to the instruction queue 140 (step 205). The processor 100 acquires BM and KC from the control execution instruction 12 (step 206), and determines whether or not the value of EN in the bit of the BM register 20 specified by BM is 1 (step 207). When the determination is “No”, that is, when the value of EN is not 1, the control execution instruction 12 is not executed and discarded in the instruction queue 140 (step 208). When the determination is “Yes”, that is, when the value of EN is 1, the processor 100 sets the next address obtained by adding 4 to the address of the control execution instruction 12 in the 32-bit RISC CPU as the return address raddr, It is set in the RET register 22 (step 209). Further, the processor 100 sets KC in the KEY register 23 as kc (step 210). Further, the processor 100 refers to the address addr of the VEC register 21 associated with the bit of the BM register 20 specified by the BM, and jumps to the exception handler of the address addr by the branch processing unit 130, that is, shifts execution. (Step 211).

FIG. 5 schematically shows an example program 50 created to implement the exceptional program control method according to one embodiment of the present invention. The program 50 is provided with an expc instruction for the control execution instruction 12. When the expc instruction of the control designation instruction 11 is designated to enable an exception, execution of the expc instruction moves to the exception handler that handles the exception. When the exception handler handles the exception, the expc instruction is followed by the expc instruction. Execution returns. However, when the expc instruction of the control designation instruction 11 is designated not to enable (invalidate) the exception, the expc instruction is passed without doing anything and execution proceeds to the next instruction.

FIG. 6 schematically shows another example program 60 created to implement the exceptional program control method according to one embodiment of the present invention. The program 60 corresponds to the program shown in FIG. The if statement in task B is no longer necessary and has not been initialized in the initial state (uninitialized), so the function that initializes the exception with the expenexp20 and 1 instructions of the control specification instruction 11 is called first. It is. In the assembler language level shown on the right side, the control execution instruction 12 expc 20, 512 instruction is provided, and in most cases, this instruction is discarded in the instruction queue without consuming a CPU cycle. It is executed as an instruction to jump to the exception handler only when is valid. The second operand 512 of the expc 20, 512 instruction is used to identify in what condition or purpose the caller caused an exception in the called program. Here, it is used to specify the function number 512, and the initialization function init () is called. In the exception handler, since it is initialized (initialized) behind the initialization function, it is specified to invalidate the exception by the “expen 20,0” instruction of the control specifying instruction 11. In this manner, an exception interrupt can be generated only in the reset state and the initialization process can be performed without executing the code for the confirmation process in the prior art.

FIG. 7 schematically shows still another example of a program 70 created to implement the exceptional program control method according to one embodiment of the present invention. This is an example in which an arbitrary software object is allocated by generalizing demand paging for allocating memory when necessary. In the prior art on the left, when the CPU tries to access an area where no page exists, a page fault occurs and memory is allocated in exception handling. In the program 70, the expc exp1, 0 instruction of the control execution instruction 12 is provided immediately after start :, and an exception is generated in the first execution, and a necessary object, for example, a memory heap is instantiated and initialized. After that, in the exception call by the second expc instruction, the memory heap has already been materialized (the exception is invalidated by the expen instruction of the control designation instruction 11), so no exception occurs. This example relates to the memory heap. However, not only the memory but also arbitrary software resources, for example, synchronization objects such as semaphores and mutexes can be allocated and initialized as necessary.

FIG. 8 schematically shows still another example of a program 80 created to implement the exceptional program control method according to one embodiment of the present invention. This is an example of a generalized code protection mechanism that protects code from unauthorized code execution. In the prior art on the left side, an exception interrupt is generated for an access violation that executes a privileged mode code in the non-privileged mode, but this can only protect the code in units of memory pages. In the program 80, the control execution instruction 12 can be provided at a necessary place to generate a pinpoint exception, and a part of the code can be a protection area when a certain condition is satisfied, that is, in an arbitrary code unit. Can handle exceptions for illegal execution. However, in order to make it equivalent to the prior art, the expand instruction and the BM register are expanded and associated with the privileged mode and the non-privileged mode, the state is kept separately, or an attribute such as whether or not it is readable can be separately registered. It is necessary to hold in. In the case of the present invention, it is assumed that an arbitrary condition is defined as an access violation in a program to enable or disable the occurrence of an exception. In the program 80, the expc 領域 3, 0 instruction of the control execution instruction 12 is provided at the head of the program execution path, thereby making the designated code area (when cond == B) an exception occurrence area. By making an exception valid with expen 3, 1 of the control designation instruction 11, all code areas including expc 3, x of the control execution instruction 12 become exception generation areas all at once.

In addition, the exceptional program control method according to the embodiment of the present invention can be implemented in various ways. For example, tracing program execution for debugging purposes. An expc instruction of the control execution instruction 12 is provided at a place where the program is to be traced, and a log code is described in the exception handler. When it is desired to start tracing, an exception is validated by the expand instruction of the control designation instruction 11, and the execution of the program is traced by the provided expc instruction. In the case of an example used as a means for inter-process communication, an expc command is provided in the task on the receiving side, and the expen command is executed on the transmitting side. When the expc instruction provided in the execution starts the exception handler, the receiving side knows that the message has been sent. Furthermore, as an application example of the system call, a system call that is executed only when a condition is satisfied can be realized. For example, a read system call that executes a system call only when it is in an open state can be created using the present invention. Various applications are possible depending on the program.

As for the expen instruction of the control designation instruction 11 and the expc instruction of the control execution instruction 12 provided in the program, when no exception occurs, the expc instruction has a dependency relationship with other CPU instructions via the register file in addition to the expen instruction. Since there is nothing, the expc instruction may be deleted from the instruction queue before reaching the execution stage in the instruction pipeline. In this case, the CPU instruction can be executed without consuming extra CPU cycles as compared with the case where the expc instruction is not provided. In the case of a conditional branch instruction, it is not possible to determine whether or not to branch until the execution of the instruction that updates the condition register is completed. On the other hand, since the expc instruction has no dependency on such a register, if there is no expen instruction immediately before, it can be determined immediately after being read into the instruction queue whether or not an exception is generated.

As described above, when compared with a conditional branch instruction, preprocessing for branch determination is unnecessary, and therefore, when no exception occurs, the expc instruction of the control execution instruction 12 is processed at high speed. If an exception occurs, it may be a slow process due to the context synchronization process. Therefore, when high-speed processing is required, context synchronization processing is not performed, and the same operation as an unconditional branch instruction may be performed so as not to return to the position where the exception occurred. In the case of the above example, there are 256 ways, but since many exception handling can be handled, it is assumed that some require context synchronization processing, and some do branch processing at high speed. Can be assigned.

As mentioned above, although the present invention was explained using the embodiment, the technical scope of the present invention is not limited to the range described about the embodiment. Various modifications or improvements can be added to the embodiments, and the modes with such modifications or improvements are naturally included in the technical scope of the present invention.

Claims (18)

A method of programmatically controlling an exception, wherein a processor
Executing a control specification instruction for specifying whether to enable an exception or not, and setting a control specification value of the exception in a register;
Execute a control execution instruction for exception control execution to determine whether or not to generate an exception, determine whether the control specified value set in the register is a value that enables the exception, and specify the control Generating the exception if the value is a value that enables the exception; and
An exception program control method including executing The method according to claim 1, further comprising: executing the step of not generating the exception when the control designation value set in the register is not a value that enables the exception. The control designation command has a bitmap index part and a control designation part, the register includes a bitmap register, and the step of setting the control designation value is the bitmap specified by the value of the bitmap index part The method according to claim 1, comprising performing a step of setting a value of the control designating part in a bit of the register. The control execution instruction has a bitmap index part, and the step of generating the exception includes the step of generating the exception in which the value of the control designation part set in the bit of the bitmap register specified by the value of the bitmap index part is 4. The method of claim 3, comprising performing the step of raising the exception when the value enables the exception. The method according to claim 4, wherein the register includes a return address register, and the step of generating the exception includes executing a step of setting a next address of the control execution instruction in the return address register. The control execution instruction includes a key code part, the register includes a key register, and the step of generating the exception includes the key register value for use in the exception to be generated. 6. The method according to claim 4 or 5, comprising performing the step of setting to: The register includes a vector base register, and the step of generating the exception is held in the vector base register associated with the bit of the bitmap register specified by the value of the bitmap index portion of the control execution instruction. The method according to any one of claims 4 to 6, comprising executing a step of referring to an address of an exception handler to be executed and jumping to the exception handler at the address. The step of not generating the exception is when the value of the control designation unit set in the bit of the bitmap register specified by the value of the bitmap index unit of the control execution instruction is not a value that enables the exception. 5. The method of claim 4, comprising performing the step of not causing the exception. The method according to claim 8, wherein the step of not generating the exception includes executing a step of discarding the control execution instruction in an instruction queue. A computer program for controlling an exception program that causes a processor to execute each step of the method according to any one of claims 1 to 9. A system for programmatic control of exceptions,
Exception control for controlling an exception by executing a control specification instruction for specifying an exception control whether or not to enable an exception and a control execution instruction for executing an exception control whether or not to generate an exception. Part
The exception control unit
Registers,
A control designation instruction processing unit for executing the control designation instruction and setting the control designation value of the exception in the register;
The control execution instruction is executed to determine whether the control specified value set in the register is a value that enables the exception. When the control specified value is a value that enables the exception, Including a control execution instruction processing unit that generates an exception,
Exception program control system. 12. The system according to claim 11, wherein the control execution instruction processing unit does not generate the exception when the control designation value set in the register is not a value that enables the exception. The control designation instruction includes a bitmap index part and a control designation part, the register includes a bitmap register, and the control designation instruction processing part includes a bitmap register part identified by a value of the bitmap index part. The system according to claim 11 or 12, wherein a value of the control designation unit is set in a bit. The control execution instruction has a bitmap index section, and the control execution instruction processing section has a value of the control designation section set to a bit of the bitmap register specified by a value of the bitmap index section. The system of claim 13, wherein the exception is generated at a value that enables the exception. 15. The system according to claim 14, wherein the register includes a return address register, and the control execution instruction processing unit sets a next address of the control execution instruction in the return address register. The control execution instruction has a key code part, the register includes a key register, and the control execution instruction processing part stores the value of the key code part in the key register for use in the exception to be generated. The system according to claim 14 or 15, wherein the system is set. The register includes a vector base register, and the control execution instruction processing unit holds in the vector base register associated with the bit of the bitmap register specified by the value of the bitmap index unit of the control execution instruction The system according to any one of claims 14 to 16, wherein an address of an exception handler to be referred to is referred to and a jump is made to the exception handler at the address. When the value of the control designating unit set in the bit of the bitmap register specified by the value of the bitmap index part of the control execution instruction is not a value that enables the exception, 15. The system of claim 14, wherein the system does not raise the exception.

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