JP2010092273A - Information processor - Google Patents

Abstract

When register expansion of an information processing apparatus such as a microcomputer is performed, an operation for adding / changing an instruction code or switching a register is required to access the extension register.
An instruction memory, a data memory, an instruction control unit for generating a control signal according to an instruction read from the instruction memory, and a load for accessing the data memory according to a control signal from the instruction control unit A store unit 10, arithmetic units 5 and 6 that perform arithmetic operations according to control signals from the instruction control unit, a standard register group 7 that stores data used by the arithmetic unit 5, and an extended register group that stores data used by the arithmetic unit 6 8 and a selection means 12 for selecting one of the standard register group 7 and the extension register group 8 by a selection signal A3, and a selection condition determination means 13 for outputting a selection signal A3 to the selection means 12, and a selection condition The determination unit 13 generates a selection signal A3 based on a specific state signal inside the apparatus.
[Selection] Figure 1

Description

  The present invention relates to an information processing apparatus in which the number of registers is expanded to meet the demand for performance improvement and function improvement. In particular, the access to the extension registers can be performed with the same number of execution cycles and instructions as the access to the standard registers. It is related to technology.

  In information processing devices represented by microcomputers (microcomputers), CPUs (Central Processing Units), DSPs (Digital Signal Processors), etc., existing information processing devices are used in order to meet the demand for further performance improvement and function improvement. In addition to the arithmetic functions and standard registers that are originally provided, there are cases where an additional arithmetic function and extension registers are additionally added. However, greatly changing the instruction format of an existing information processing apparatus in order to handle this expanded resource has a problem of deterioration of compatibility and a problem that requires an assembler / compiler to cope with it. In particular, it is generally difficult to extend the bit width of the register specification field in the instruction code format, and it is difficult to explicitly specify the extension register in the instruction code.

  If the register to be used is a standard register or an extension register depending on the type of operation instruction, use the extension register implicitly without extending the bit width of the register specification field in the instruction code format. Is possible. Such a configuration can be found in a MIPS instruction set architecture, such as a multi instruction (multiplication instruction) and a Hi / Lo register (see Non-Patent Document 1, for example).

  As described above, the extension register can be handled by the extension operation instruction, but separately, data transfer to the extension register is required for reading the extension register or writing to the extension register. As methods for realizing data transfer to such an extension register, the following three methods are mainly known.

  First, a prefix instruction is added, and an extension register is accessed instead of a standard register in an instruction immediately after the prefix instruction (see, for example, Patent Document 1: Prefix instruction = an instruction including a prefix). A prefix is a code that is used in front of an opcode to change or indicate a function, and is also called an instruction prefix.

  Second, a control register is provided to enable switching between a standard register and an extension register, and by setting the control register before register access, it is possible to access a desired register among the standard register and the extension register (for example, (See Patent Document 2: Control register = extended register replacement means).

Third, a data transfer instruction between the standard register and the extension register is added (for example, the mfhi / mflo instruction in Non-Patent Document 1). Also in this instruction, the extension register is implicitly used as a source (data source) or a destination (data destination).
John L. Hennessy / David A. Patterson, “Computer Configuration and Design 2nd edition [top]” Nikkei BP, May 17, 1999 (Page M-1) Japanese translation of PCT publication No. 2004-506263 (page 11-15, FIG. 7-10) JP-A-2-146625 (page 2-3, FIG. 1-2)

  Each of the above conventional techniques has the following problems.

1. <When adding a prefix instruction>
When adding a prefix instruction, there are problems such as an increase in code size due to having to execute the prefix instruction, an increase in the execution cycle, and assembler and compiler support, which increases the total development man-hours. . An example of an assembler program for adding a prefix instruction is as follows.

LD R0, (address of first operand of multiplication)
PFX
LD R0, (address of second operand of multiplication)
MUL R0
PFX
STR0, (multiplication result address)
Here, “PFX” is a prefix instruction. In the load instruction / store instruction immediately after this instruction, the extension register ERn (n = 0, 1,...) Is accessed instead of the standard register Rn (n = 0, 1,...). Switch to the target. “LD Rn, (address)” represents a (load) instruction for reading data at a specified address in the data memory into the value of the standard register Rn. Since the second LD instruction (load instruction) is immediately after the PFX instruction, it is actually loaded into the extension register ER0. “ST Rn, (address)” represents a (store) instruction for writing the value of the standard register Rn to a specified address in the data memory. Since it is immediately after the PFX instruction here, the extension register ER0 is actually stored. “MUL Rn” is a multiplication instruction, and the result of multiplication (Rn × ER0) is stored in the extension register ER0. The extension register ER0 is fixedly used as a multiplication-dedicated register and cannot be specified in the instruction. According to this method, the PFX instruction is required immediately before the load instruction / store instruction to the extension register ER0 used in the MUL instruction (multiplication instruction), and the problem is that the code size for this instruction increases and the execution cycle increases. There is.

2. <When providing a control register>
When the control register is provided, it is necessary to set the control register before accessing the register, which increases the execution cycle. An example of an assembler program for providing a control register is as follows.

LD R0, (address of first operand of multiplication)
MOV R1, 1
STR1, (control register address)
LD R0, (address of second operand of multiplication)
MUL R0
STR0, (multiplication result address)
Here, “MOV Rn, value” represents an instruction for substituting the value specified in the standard register Rn. The control register takes a value of “0” or “1”. When the control register is “1”, the LD register or ST instruction (store instruction) accesses the extension register ERn instead of the standard register Rn. Indicates. According to this method, before loading the multiplication second operand into the extension register ER0, an instruction for setting “1” in the control register is required, which means that the code size for this instruction is increased and the execution cycle is increased. There's a problem.

3. <Add data transfer instruction between standard register and extension register>
When adding a data transfer instruction between a standard register and an extension register, when you want to load / store to the extension register, it is necessary to load / store to the standard register. There is a problem that the value of the standard register is destroyed. An example of an assembler program for providing a control register is as follows.

LD R0, (address of first operand of multiplication)
LD R1, (address of second operand of multiplication)
STER0 R1
MUL R0
LDER0 R0
STR0, (multiplication result address)
“LDER0 Rn” represents an instruction for assigning the value of the standard register Rn to the extension register ER0. “STER0 Rn” represents an instruction for assigning the value of the extension register R0 to the standard register Rn. According to this method, since the address of the second operand of multiplication needs to be once loaded into the standard register R1, the value of the standard register R1 is destroyed (the value of the standard register R0 is also destroyed by LDER0), and the STER0 and LDER0 instructions There is a problem that the code size of the minute increases and the execution cycle increases.

  The present invention was created in view of such circumstances, and does not add an instruction or change an instruction format, and does not explicitly set a control register. An object of the present invention is to provide an information processing apparatus capable of accessing an extension register.

(1) An information processing apparatus according to the present invention
An instruction memory for storing instructions;
Data memory for storing data;
An instruction control unit that generates a control signal according to an instruction read from the instruction memory;
A load / store unit that accesses the data memory in accordance with the control signal by the instruction control unit;
An arithmetic unit that performs an operation according to the control signal by the instruction control unit;
A group of standard registers for storing data used in the computing unit;
An extension register group for storing data used in the arithmetic unit;
A selection means for selecting one of the standard register group and the extension register group by a selection signal;
Selection condition determination means for outputting the selection signal to the selection means,
The selection condition determination means is configured to generate the selection signal based on a specific state signal inside the apparatus.

  That is, selection means for selecting either the standard register group or the extension register group is provided, and further, selection condition determination means for generating and outputting a selection signal for controlling the selection means is provided. It is characterized in that it is configured to generate a selection signal based on an internal specific state signal.

  According to this configuration, the selection condition determination unit generates a selection signal for the selection unit from a specific state signal inside the apparatus, and the selection unit selects either the standard register group or the extension register group according to the selection signal. Will do. In this case, it is not necessary to add or extend the instruction code. Also, it is not necessary to consume additional execution cycles for explicit register switching. Therefore, it is possible to access the extension register with an execution cycle and the number of instructions equivalent to the standard register access.

  (2) In the information processing apparatus having the configuration of (1), the selection condition determination unit generates the selection signal using an address generated by the load / store unit when executing an instruction that causes a memory access. There are aspects. According to this configuration, it is possible to select either the standard register group or the extension register group in accordance with the address where the data is located by an instruction that causes access to the data memory. In other words, access to extension registers with the same number of execution cycles and number of instructions as standard register access, without adding or extending instruction codes or consuming additional execution cycles for explicit register switching. Is possible.

  (3) In the information processing apparatus having the configuration of (1), the selection condition determination unit includes a command history holding unit that holds history information of a command executed in the past, and the command held by the command history holding unit There is a mode in which the selection signal is generated based on the history information. For example, the instruction history holding means is composed of a state machine, and generates a selection signal according to the state of the state machine when the state machine changes using an arbitrary bit of the loaded instruction code. According to this configuration, it is possible to select either the standard register group or the extended register group depending on whether or not the instruction sequence arranged one or more instructions before the instruction whose register is to be switched is in a specific sequence. Become.

  By the way, in the configuration of (3) above, even if an instruction code is arranged so that a specific instruction sequence is generated, when an interrupt process occurs, the instruction code of the interrupt process is executed in the middle. Cannot be detected. Therefore, the following measures are taken.

  (4) In the information processing apparatus having the configuration of (3), the instruction history holding unit saves the history information of instructions executed in the past at the start of interrupt processing, and restores the instruction history information at the time of interrupt return. There is an aspect of making it. According to this configuration, even if an interrupt process occurs, it is guaranteed that a specific instruction sequence arranged before the instruction for which register switching is to be performed is detected. Therefore, the register is automatically detected by detecting the specific instruction sequence. Can be selected automatically.

  (5) The information processing apparatus having the configuration (1) is configured as an information processing apparatus that operates in a pipeline manner, and the instruction control unit is configured to generate instruction information, and further corresponds to each pipeline stage. Command information holding means for holding the command information, and the selection condition determining means is configured to generate the selection signal using the command information held in the command information holding means. There are aspects. According to this configuration, the information processing apparatus is an instruction pipeline method, and the selection condition determining means selects using the instruction information (instruction code or instruction decode result) held in the instruction information holding means of each pipeline stage. Generate a signal. Therefore, it is possible to select either the standard register group or the extension register group depending on whether or not the instruction sequence arranged after one or more instructions of the instruction whose register is to be switched is in a specific sequence. In the case of (3) above, “1 instruction or more before”, whereas in this item (5), “1 instruction or more after”.

  By the way, in the configuration of (5) above, even if an instruction code is arranged so that a specific instruction sequence is generated, when an interrupt process occurs, the instruction code of the interrupt process is held in the instruction pipeline. The instruction sequence cannot be detected. Therefore, the following measures are taken.

  (6) The information processing apparatus having the configuration of (5) further includes instruction history holding means for holding history information of instructions executed in the past, wherein the instruction history holding means stores instructions executed in the past. There is a mode in which a specific sequence is detected and interrupt processing is prohibited. According to this configuration, interrupt processing is prohibited while detecting that an instruction in each pipeline stage is a specific instruction sequence, so interrupts are not generated until a specific instruction sequence that triggers register switching is reached. It is possible to prohibit and guarantee that a specific instruction sequence is finally detected. Therefore, it is possible to automatically select a register by detecting a specific instruction sequence arranged after an instruction for which register switching is to be performed.

  According to the present invention, there is provided selection means for selecting either the standard register group or the extension register group, and further, selection condition determination means for generating a selection signal for controlling the selection means from a specific state signal inside the apparatus. Therefore, without adding or extending the instruction code, and without consuming additional execution cycles for explicit register switching, the extension registers can be used with the same number of execution cycles and number of instructions as standard register access. Can be accessed.

  Embodiments of an information processing apparatus according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
<Configuration>
FIG. 1 is a block diagram showing an internal configuration of a microcomputer as an information processing apparatus according to Embodiment 1 of the present invention. In the figure, 1 is an instruction memory for storing an instruction, 2 is an instruction register for temporarily holding an instruction read from the instruction memory 1, and 3 is for decoding an instruction register 2 value to generate an appropriate control signal. The instruction decoder 4 includes an instruction control unit having the instruction register 2 and the instruction decoder 3 as constituent elements, A1 indicates an instruction decoding result including a control signal, and 5 performs an operation according to the control signal from the instruction control unit 4, and the standard register group 7 Is used, but the extended register group 8 is not used. 6 is an arithmetic unit that operates according to the control signal from the instruction control unit 4 and uses the standard register group 7 and the extended register group 8. 7 is a standard register group. 8 is an extension register group, 9 is a data memory for storing data, and 10 is a row for accessing the data memory 9 in accordance with a control signal from the instruction control unit 4. A store unit, A2 is a memory address when a data memory access occurs, 11 is an operation result, memory data, a data bus for exchanging register values between functional blocks, and 12 is a standard register group 7 according to a selection signal A3 Selection means for selecting one of the extension register groups 8, 13 is a selection condition determination means for generating a selection signal A3 from the address A2 when the load / store unit 10 accesses the data memory 9, and A3 is a standard register group 7 A4 is a selection signal indicating that one of the extension register group 8 is selected and A4 is a read enable signal / read data / write enable signal / write data to each register.

  In this example, the standard register group 7 is composed of four standard registers R0 to R3, and the extension register group 8 is composed of four extension registers ER0 to ER3. Basically, the standard registers R0 to R3 are designated by the register designation field in the instruction code. In the instruction to access the data memory 9, the extension register side is designated by the selection signal A3. The selection unit 12 selects the extension register ER0 when the standard register R0 is designated in the register designation field in the instruction code, and selects the extension register ER1 when the standard register R1 is designated. It is configured to select an extension register. The number of registers included in the extended register group 8 may be larger or smaller than the number of registers included in the standard register group 7. When there are two or more extension register groups 8 corresponding to the standard register group 7, the selection signal A3 is a signal capable of expressing three or more states, and the selection means 12 includes one standard register group 7 and two or more state registers. One is selected from the extension register group 8.

  When the instruction loaded in the instruction register 2 is an instruction that causes data memory access, the data memory 9 is accessed by appropriately controlling the load / store unit 10. Is output. The instruction memory 1 and the data memory 9 may be two independent memories or one common memory.

  The selection condition determination means 13 receives an address A2 when the load / store unit 10 accesses the data memory, and generates a selection signal A3 using a part or all of the bits of the address A2. The selection unit 12 receives the selection signal A3 from the selection condition determination unit 13, and selects one of the standard registers R0 to R3 and the extension registers ER0 to ER3 according to the value of the selection signal A3. At the time of register reading, the selection unit 12 validates one of the read enable signals A4 of the standard register group 7 and the extension register group 8. As a result, the data read from the register designated by the instruction is output to the data bus 11. At the time of register write, the selection unit 12 validates the write enable signal A4 of either the standard register group 7 or the extension register group 8. As a result, the data on the data bus 11 is written to the register designated by the instruction.

  By configuring as above, instruction execution that causes memory access to other addresses is performed when an instruction that causes memory access to a specific range of addresses (load instruction, store instruction, etc.) is executed. Sometimes it becomes possible to access standard registers.

<Operation>
When accessing addresses after address “0x8000” in the memory address space (addresses “0x0000” to “0xFFFF”), the extension register is accessed. An assembler program that multiplies data on the data memory 9 and stores the result in the data memory 9 is as follows.

LD R0, (0x0000)
LD R0, (0x9000)
MUL R0
ST R0, (0x9000)
An example of operation waveforms in this case will be described with reference to FIG. In this example, the selection signal A3 is 1 bit, and the selection signal A3 is set to “1” when the extension register is selected.

  At time t = t1, the instruction “LD R0, (0x0000)” is loaded into the instruction register 2, and at time t = t2, “0x0000” which is the load address is output to the address A2. Since the value of the address A2 is less than “0x8000”, “0” is output as the selection signal A3, and the standard register group 7 side is enabled by the write enable signal A4 to the register. Since data at the address “0x0000” of the data memory 9 is output to the data bus 11, as a result, the data at the address “0x0000” of the data memory 9 is loaded into the standard register R0.

  At time t = t2, the instruction “LD R0, (0x9000)” is loaded into the instruction register 2, and at time t = t3, the load address “0x9000” is output to the address A2. Since the value of the address A2 is “0x8000” or more, “1” is output as the selection signal A3, and the extension register group 8 side is enabled by the write enable signal A4 to the register. Since data at the address “0x9000” in the data memory 9 is output to the data bus 11, as a result, the data at the address “0x9000” in the data memory 9 is loaded into the extension register ER0.

  At time t = t3, the instruction “MUL R0” is loaded into the instruction register 2, and at time t = t4, the result of multiplication (R0 × ER0) is assigned to the extension register ER0.

  At time t = t4, the instruction “STR 0, (0x9000)” is loaded into the instruction register 2, and at time t = t5, “0x9000”, which is a store destination address, is output to the address A2. Since the value of the address A2 is “0x8000” or more, “1” is output as the selection signal A3, the value of the extension register ER0 is output to the data bus 11, and the value of the extension register ER0 is stored in the data memory 9 Is done.

  As in this example, although the standard register R0 is specified in the instruction code, the extension register ER0 can actually be accessed. This is a major point of the present invention. That is, the extension register can be accessed without adding a new instruction or changing the instruction format in the microcomputer.

  However, even if it is desired to load the data at the address “0x9000” into the standard register, this cannot be done within the scope of this embodiment. This method is suitable when the same data on the memory is mirrored to two or more different CPU address areas. Mirroring is a method for mapping the same physical memory to a plurality of address spaces. In this embodiment, if the same data as the addresses “0x0000” to “0x7FFF” is mirrored to the addresses “0x8000” to “0xFFFF”, the data at the address “0x9000” is “LD R0, (0x1000)”. The standard register R0 can be loaded.

(Embodiment 2)
<Configuration>
FIG. 3 is a block diagram showing an internal configuration of the microcomputer as the information processing apparatus according to the second embodiment. Since reference numerals 1 to 13 are the same as those in the first embodiment, description thereof is omitted. Reference numeral 14 denotes instruction history holding means for holding history information of instructions executed in the past. The selection condition determination means 13 is configured to generate the selection signal A3 based on the history information of the instruction held by the instruction history holding means 14.

  In this embodiment, the instruction history holding means 14 receives the instruction decode result A1 from the instruction decoder 3, the instruction history holding means 14 holds the history of instructions executed in the past, and the selection condition judging means 13 The selection signal A3 is generated based on the history information of the instructions held in the history holding means 14. There is no transmission of the address A2 from the load / store unit 10 to the selection condition judging means 13 in the first embodiment. As an implementation mode of the instruction history holding unit 14, a state machine or simply holding instruction information of the previous instruction can be considered. The instruction here is not limited to a special instruction such as a prefix instruction but also includes a normal instruction such as an operation / data transfer instruction.

  With this configuration, it is possible to detect a specific instruction sequence of an instruction positioned before an instruction to be switched, and generate a selection signal A3 based on the result. This is suitable when an operation instruction (for example, multiplication / division) implicitly uses an extension register. For the ST instruction that is executed first after execution of a multiplication / division instruction, the extension register (for multiplication / division) is set. It can be stored.

<Operation>
In the second embodiment,
Instruction 1
Instruction 2
MUL R0
Instruction 3
Command 4
ST R0, (0x0000)
Instruction 5
Examples of operation waveforms in the case of continuously executing instructions expressed by assembler instructions will be described with reference to FIGS.

  “Instruction n” (n = 0, 1,...) Is a meaningful instruction other than the MUL instruction (multiplication instruction) and the ST instruction (store instruction). Although not necessary for a series of multiplication processes, it is provided for convenience of explanation. Since other instructions have already been described, the description thereof will be omitted.

  The purpose of this instruction sequence is “perform multiplication and store the result at memory address“ 0x0000 ””. Although the extension register ER0 cannot be directly specified in the ST instruction, in this example, the extension instruction is selected instead of the standard register in the ST instruction that is executed first after the MUL instruction is executed.

  Under this condition, the selection condition determination means 13 can be implemented by the state machine shown in FIG. This state machine is initially in the S0 state and remains in the S0 state until a MUL instruction is detected. When the MUL instruction is detected in the S0 state, the state transits to the S1 state and remains in the S1 state until the ST instruction is detected. When the ST instruction is detected in the S1 state, the state transits to the S0 state. The selection signal A3 outputs “1” when “state is S1 and ST instruction”.

  The operation waveform at this time will be described with reference to FIG.

  At time t = t1, t2, since the instruction loaded into the instruction register 2 is not a MUL instruction, the state remains S0.

  At time t = t3, since the MUL instruction is loaded into the instruction register 2, the state transitions to S1 at the next clock.

  At time t = t4, t5, since the instruction loaded into the instruction register 2 is not the ST instruction, the state remains S1.

  When the instruction “STR 0, (0x0000)” is loaded into the instruction register 2 at time t = t6, the selection condition determination unit 13 detects that “state is S1 and ST instruction”. “1” is output as the selection signal A3, and the value of the extension register ER0 is output to the data bus 11 (time t7). As a result, the value of the extension register ER0 is written to the address “0x0000” of the data memory 9. The state transitions to S0.

  Although the standard register R0 is specified in the instruction code like the ST instruction in this example, the extension register ER0 can actually be accessed.

  An operation waveform when an interrupt process is inserted between the ST instruction and the MUL instruction and the ST instruction is executed several times in the interrupted process will be described with reference to FIG.

  At time t = t1, t2, since it is not a MUL instruction, the state remains S0.

  Since a MUL instruction is detected at time t = t3, the state transitions to S1 at t = t4.

  Since it is not an ST instruction at time t = t4, the state remains S1.

  When interrupt processing is started at time t = t5, the current state S1 is saved and the state is set to S0. Thereafter, the ST instruction is executed from time t = t5 to t7, but since the state is S0, the “state is S1 and ST instruction” is not established, and the selection unit 12 selects the standard register group 7 side.

  When returning from the interrupt process at time t = t8, the state value S1 saved at time t = t5 is restored.

  When the instruction “STR 0, (0x0000)” is loaded into the instruction register 2 at time t = t9, the selection condition determination unit 13 detects that the “state is S1 and ST instruction”. Therefore, “1” is output as the selection signal A3 at the next clock, and the value of the extension register ER0 is output to the data bus 11. As a result, the value of the extension register ER0 is written to the address “0x0000” of the data memory 9 (time t10). The state transitions to S0.

  As described above, even if an additional instruction is executed by interrupt processing between the MUL instruction and the ST instruction, it is possible to detect the instruction sequence of “ST instruction executed first after the MUL instruction is executed”. .

(Embodiment 3)
<Configuration>
FIG. 7 is a block diagram showing an internal configuration of a microcomputer as a pipeline type information processing apparatus according to the third embodiment. In this example, a general five-stage pipeline type microcomputer is assumed, and IF (Instruction Fetch: Instruction Fetch Stage), ID (Instruction Decode: Instruction Decode Stage), EX (Instruction Execution: Execution Stage), MA ( Memory Access: memory access stage) and WB (Write / store Back: write back stage). Since reference numerals 1 to 13 are the same as those in the first embodiment, description thereof is omitted. 21-23 are instruction decode result registers held at each stage, 20 is instruction information holding means comprising three instruction decode result registers 21-23, 24 is a register holding data used for calculation, and 25 is an arithmetic unit 5 is a register for holding the calculation result of 5, the register 26 is for holding either the calculation result 25 or the read data of the data memory 9, and A5 is an interrupt enabling / disabling signal output by the instruction history holding means 14.

  The operation of each pipeline stage will be described.

  In the instruction fetch stage (IF), an instruction code is fetched (taken out) from the instruction memory 1 and stored in the instruction register 2.

  In the instruction decode stage (ID), the instruction code in the instruction register 2 is decoded by the instruction decoder 3 and the result is stored in the decoded instruction 21 in the instruction information holding means 20. In addition, an operand used for an operation in the subsequent execution stage (EX) is stored in the operation operand 24.

  In the execution stage (EX), the calculation is performed using the calculator 5 or the calculator 6 and stored in the calculation result 25. Address operations with load and store instructions are also performed at this stage. The operation to be performed is instructed by the decoded instruction 21. The content of the decoded instruction 21 is passed to the decoded instruction 22.

  In the memory access stage (MA), the data memory 9 is loaded / stored. The address is stored in the calculation result 25. In the case of a load instruction, the read data from the data memory 9 is stored in the write-back data 26, and in other instructions (such as arithmetic operations), the data of the operation result 25 is held in the write-back data 26. The content of the decoded instruction 22 is passed to the decoded instruction 23.

  In the write back stage (WB), the data of the write-back data 26 is written into either the standard register or the extension register.

  The number of pipeline stages of the microcomputer is not necessarily five, and the selection condition determination means 13 is not necessarily located in the write back stage (WB). The selection means 12 can control reading as well as writing to the standard register group 7 and the extension register group 8.

  With this configuration, the selection condition determination unit 13 can obtain an instruction to be executed in the write back stage (WB) from the instruction decode result 23, and an instruction to be executed after the 1-2 instruction can be obtained from the instruction decode result 21 to 21. 22 can be obtained. For this reason, it is possible to detect a specific instruction sequence of an instruction located after the instruction for which register switching is to be performed, and to generate the selection signal A3 based on the result (in the second embodiment, register switching is performed). (Note that it detects a specific instruction sequence for the instruction located "before" the instruction you want.)

  This is suitable when a certain arithmetic instruction (for example, multiplication / division) implicitly uses an extension register. For a load instruction executed one or two instructions before the multiplication / division instruction (for multiplication / division) It becomes possible to load an extension register.

<Operation>
In the third embodiment,
LD R0, (0x0000)
Instruction 1
MUL R0
An operation waveform example in the case of continuously executing the instruction expressed by the assembler instruction will be described with reference to FIG.

  “Instruction n” is a meaningful instruction other than the MUL instruction and the LD instruction. Although not necessary for a series of multiplication processes, it is provided for convenience of explanation. Since the operation of other instructions has already been described, the description thereof is omitted.

  The purpose of this instruction sequence is “load data at memory address“ 0x0000 ”to extension register ER0 before multiplication”. Although the extension register ER0 cannot be directly specified in the LD instruction, in this example, the extension register is selected instead of the standard register in the LD instruction executed one or two instructions before the MUL instruction.

  The operation in this example will be described with reference to FIG.

  When an LD instruction is loaded into the instruction register 2 at the instruction decode stage (ID) at time t = t1, it is decoded by the instruction decoder 3, and the decoded result is held in the decoded instruction 21 at time t = t2.

  At the execution stage (EX) at time t = t2, the arithmetic unit 6 calculates the load source memory address of the LD instruction, and the result is held in the operation result 25 at time t = t3. At the same time, the content of the decoded instruction 21 is held in the decoded instruction 22.

  At the memory access stage (MA) at time t = t3, the value of the operation result 25 (the address of the LD instruction) is output to the address A2 of the data memory 9, and the memory read data is written back at time t = t4. Retained. At the same time, the contents of the decoded instruction 22 are held in the decoded instruction 23.

  On the other hand, paying attention to the MUL instruction, the MUL instruction is loaded into the instruction register 21 at time t = t3 and held in the decoded instruction 22 at time t = t4.

  That is, at time t = t4, the decoded instruction 23 indicates an LD instruction, and the decoded instruction 21 indicates a MUL instruction. Therefore, the selection condition determination means 13 determines that the instruction executed at the write back stage (WB) at this time is the LD instruction at the time t = t4, and that the LD instruction is located two instructions before the MUL instruction. Therefore, the condition of “LD instruction executed 1 to 2 instructions before the MUL instruction” is met. Therefore, by outputting “1” as the selection signal A3, the write enable signal A4 to the register becomes valid on the extension register group 8 side. At the same time, since the value of the write-back data 26 is output to the data bus 11 (this is the data at the data memory address “0x0000”), the data at the data memory address “0x0000” is stored at time t = t5. Loaded into extension register ER0.

  Although the standard register R0 is specified in the instruction code like the LD instruction in this example, the extension register ER0 can actually be the access target.

  However, if two or more instructions are executed between the LD instruction and the MUL instruction by the interrupt process, it cannot be recognized that it is an “LD instruction executed one or two instructions before the MUL instruction”. Therefore, by outputting the interrupt permission / inhibition signal A5 from the instruction history holding unit 14 described in the second embodiment, the interruption is prohibited during the period from the recognition of the LD instruction to the recognition of the MUL instruction.

  The information processing apparatus of the present invention is useful as an information processing apparatus that can expand the number of registers without adding or extending an instruction code and can maintain high compatibility with an information processing apparatus before expansion. is there.

  In addition, the extension register can be accessed with the same execution cycle and number of instructions as standard register access without consuming additional execution cycles for explicit register switching. This is useful as an information processing apparatus in which the size and execution cycle do not increase as compared with the information processing apparatus before expansion.

The block diagram which shows the internal structure of the microcomputer as an information processing apparatus of Embodiment 1 of this invention Timing chart of Embodiment 1 of the present invention The block diagram which shows the internal structure of the microcomputer as an information processing apparatus of Embodiment 2 of this invention State transition diagram of instruction sequence determination circuit in Embodiment 2 of the present invention Timing chart of embodiment 2 of the present invention (part 1) Timing chart of embodiment 2 of the present invention (part 2) The block diagram which shows the structure inside the microcomputer as information processing apparatus of Embodiment 3 of this invention Timing chart of Embodiment 3 of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Instruction memory 2 Instruction register 3 Instruction decoder 4 Instruction control part 5 Arithmetic unit which does not use an extension register group 6 Arithmetic unit which uses an extension register group 7 Standard register group 8 Extension register group 9 Data memory 10 Load / store unit 11 Data bus DESCRIPTION OF SYMBOLS 12 Selection means 13 Selection condition determination means 14 Instruction log | history holding means 20 Instruction information holding means 21-23 Instruction decode result register | resistor 24 hold | maintained in each stage 24 Register which hold | maintains the data used with the calculator 5 Register 26 that holds the result Register that holds either the operation result 25 or the read data of the data memory 9 A1 Instruction decode result (control signal)
A2 Memory address A3 Select signal A4 Read enable signal / read data / write enable signal / write data to each register A5 Interrupt enable / disable signal

Claims (6)

An instruction memory for storing instructions;
Data memory for storing data;
An instruction control unit that generates a control signal according to an instruction read from the instruction memory;
A load / store unit that accesses the data memory in accordance with the control signal by the instruction control unit;
An arithmetic unit that performs an operation according to the control signal by the instruction control unit;
A group of standard registers for storing data used in the computing unit;
An extension register group for storing data used in the arithmetic unit;
A selection means for selecting one of the standard register group and the extension register group by a selection signal;
Selection condition determination means for outputting the selection signal to the selection means,
The information processing apparatus configured to generate the selection signal based on a specific state signal inside the apparatus.   The information processing apparatus according to claim 1, wherein the selection condition determination unit generates the selection signal using an address generated by the load / store unit when executing an instruction that causes a memory access.   2. The selection condition determining means includes instruction history holding means for holding history information of instructions executed in the past, and generates the selection signal based on instruction history information held by the instruction history holding means. The information processing apparatus described in 1.   The information processing apparatus according to claim 3, wherein the instruction history holding unit saves history information of instructions executed in the past when interrupt processing is started, and restores history information of the instructions when interrupt is restored. It is configured as an information processing device that operates in a pipeline system,
The instruction control unit is configured to generate instruction information;
Furthermore, it comprises instruction information holding means for holding the instruction information corresponding to each pipeline stage,
The information processing apparatus according to claim 1, wherein the selection condition determination unit is configured to generate the selection signal using the command information held in the command information holding unit.   6. The apparatus according to claim 5, further comprising instruction history holding means for holding history information of instructions executed in the past, wherein the instruction history holding means detects a specific sequence of instructions executed in the past and prohibits interrupt processing. The information processing apparatus described.

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