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WO2011130890A1 - 以氮化铝为势垒层的mo基金属栅叠层结构的刻蚀方法 - Google Patents

以氮化铝为势垒层的mo基金属栅叠层结构的刻蚀方法 Download PDF

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WO2011130890A1
WO2011130890A1 PCT/CN2010/001459 CN2010001459W WO2011130890A1 WO 2011130890 A1 WO2011130890 A1 WO 2011130890A1 CN 2010001459 W CN2010001459 W CN 2010001459W WO 2011130890 A1 WO2011130890 A1 WO 2011130890A1
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etching
metal gate
barrier layer
layer
based metal
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李永亮
徐秋霞
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H10P50/267—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H10D64/666—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum the conductor further comprising additional layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane

Definitions

  • the present invention relates to the field of integrated circuit manufacturing technology, and in particular, to an etching method of a Mo-based metal gate stacked structure using aluminum nitride as a barrier layer in a gate-first process. Background technique
  • the power consumption of the device is reduced, and the polysilicon depletion effect and the P-type metal oxide-semiconductor field effect transistor (PM0SFET) are completely eliminated.
  • the reliability problem caused by B-penetration and the mitigation of the Fermi level pinning effect have become an inevitable choice to replace the traditional Si0 2 /polysilicon (poly) structure with a high dielectric constant (K) / metal gate material.
  • the work function of N- and P-tubes should be near the bottom of the conduction band of Si (4. leV) in order to obtain a better short-channel effect and a suitable threshold. ) and the vicinity of the price band (about 5. 2eV). Since Mo metal gate having a low resistivity (5 X 10- 6 Q. Cra ), high melting point (greater than 2600 degrees) and Mo metal gate (100) to exhibit a work function of 5eV nearby, Mo based metal such The gate becomes a powerful candidate for P-tube metal gate materials.
  • a laminated structure of a plug-in metal gate ie, a stacked structure of a silicon gate/metal gate
  • a pure metal gate electrode ie, a silicon gate/metal gate
  • High K metal gate material integration.
  • the Mo metal gate reacts with the silicon gate.
  • the barrier layer is used to improve thermal stability.
  • the thermal stability problem is solved after the barrier layer is added, the difficulty of etching the high K/metal gate structure is also increased. Therefore, solving the etching of the barrier layer/Mo-based metal gate stack structure is a powerful guarantee for realizing the integration of the P-tube Mo-based metal gate. Summary of the invention
  • a Mo-based barrier layer is provided in the gate-first process.
  • the present invention provides a Mo-based metal gate stacked structure using aluminum nitride as a barrier layer.
  • Etching method the method includes:
  • Photolithography and hard mask etching of a semiconductor substrate forming an interface Si0 2 layer, a high K gate dielectric layer, a Mo-based metal gate electrode layer, an A1N barrier layer, a silicon gate layer, and a hard mask layer;
  • the glue is removed, and the hard mask is used as a mask, and the silicon gate layer is subjected to a high selective ratio anisotropic etching by a dry etching process;
  • the high-k gate dielectric layer is formed of Hf0 2 , HfON, HfA10, HfA10N, HfTaO, HfTaON, HfSiO, HfSiON, HfLaO or HfLaON.
  • the Mo-based metal gate electrode layer is composed of a layer structure of any two of Mo, MoN, MoAIN or ⁇ 1 ⁇ , MoN, and Mo.
  • the A1N barrier layer is prepared by a physical vapor deposition process and has a thickness of 2 to 10 nm.
  • the silicon gate layer is made of polysilicon or amorphous silicon.
  • the hard mask layer is formed of a silicon oxide, silicon nitride or silicon oxide/silicon nitride stacked structure.
  • the dry etching process is used for anisotropic etching of the A1N barrier layer, the Mo-based metal gate and the high-k dielectric, and the BC1 3 -based etching gas is used for the A1N barrier layer and the Mo-based metal.
  • the gate and high K dielectrics perform an anisotropic etch with a high selectivity ratio.
  • the BC1 3 -based etching gas includes one or more gases of Cl 2 , 0 2 , and Ar as an etching gas in addition to the BC1 3 .
  • the ratio of Cl 2 to BC1 3 in the BC1 3 -based etching gas is (T1 : 4, the ratio of 0 2 to BC1 3 is 0 to 1: 8, the ratio of Ar to BC1 3 is 1: 5; To 1: 2.
  • the dry etching process conditions of the A1N barrier layer, the Mo-based metal gate, and the high-k dielectric stacked structure are as follows: the upper electrode power is 14 (T450W, the lower electrode power is 3 (T120W, the pressure is 4) ⁇ 15mt, BC1 The total flow rate of the 3 -base etching gas is 5 (Tl30 S c C ni, and the temperature of the cavity and the electrode is controlled at 50 to 80 degrees.
  • the present invention has the following beneficial effects:
  • the etching method of the Mo-based metal gate stack structure using aluminum nitride as a barrier layer in the gate-first process proposed by the present invention without increasing the etching complexity due to the existence of the barrier layer, the barrier layer and Etching of the M0-based metal gate
  • One-step etching is completed; the etching method is highly compatible with existing CMOS processes; not only a steep etching profile is obtained by an etching process that optimizes the MN barrier layer, the Mo-based metal gate, and the high-k dielectric layer structure.
  • the loss on the Si substrate is small, which provides the necessary guarantee for the integration of the high K/metal gate.
  • the etching method of the Mo-based metal gate stack structure using aluminum nitride as a barrier layer in the gate-first process proposed by the present invention does not increase the etching process by adding an A1N barrier layer on the Mo-based metal gate.
  • the complexity of the barrier layer and the etching of the M0-based metal gate is completed by one-step etching.
  • the etching method of the Mo-based metal gate stack structure using aluminum nitride as a barrier layer in the gate-first process proposed by the present invention can not only obtain a steep etch profile, but also has a small loss on the Si substrate. To meet the requirements of the etching process after introducing high K and metal gate materials in the integrated process.
  • the etching method of the Mo-based metal gate stack structure using aluminum nitride as a barrier layer in the gate-first process proposed by the present invention has high compatibility with the existing CMOS process.
  • FIG. 1 is a flow chart showing an etching method of a Mo-based metal gate stacked structure using aluminum nitride as a barrier layer provided by the present invention
  • FIG. 2 is a scanning electron micrograph of a M0A1N metal gate, an A1N barrier layer, a polysilicon gate, and a Si0 2 hard mask formed on a HfSiAlON high-k dielectric in accordance with an embodiment of the present invention
  • FIG. 3 is a scanning electron micrograph of an etched film using an optimized hard mask and polysilicon etching process in accordance with an embodiment of the present invention
  • FIG. 4 is a scanning electron micrograph of an A1N barrier layer, a MoAIN metal gate, and a high-k dielectric laminate structure etched using a BCl 3 /0 2 /Ar etching gas in accordance with an embodiment of the present invention.
  • FIG. 1 is a flow chart of an etching method of a Mo-based metal gate stacked structure using aluminum nitride as a barrier layer according to the present invention, the method comprising:
  • Step 1 forming an interface Si0 2 layer, a high K gate dielectric layer, a Mo-based metal gate electrode layer, an A1N barrier layer, a silicon gate layer, and a hard mask layer on the semiconductor substrate;
  • Step 2 Photolithography and hard masking of a semiconductor substrate forming an interface Si0 2 layer, a high K gate dielectric layer, a Mo-based metal gate electrode layer, an A1N barrier layer, a silicon gate layer, and a hard mask layer eclipse;
  • Step 3 removing the glue, masking with a hard mask, and performing a high selective ratio anisotropic etching on the silicon gate layer by a dry etching process;
  • Step 4 Anisotropic etching of the MN barrier layer, the Mo-based metal gate, and the high-k dielectric is performed by a dry etching process.
  • the high-k gate dielectric layer is formed of Hf0 2 , HfON, HfA10, HfA10N, HfTaO, HfTaON, HfSiO, HfSiON, HfLaO or HfLaON.
  • the Mo-based metal gate electrode layer is composed of a laminated structure of any two materials of Mo, MoN, MoAIN or MoAIN, MoN, and Mo.
  • the A1N barrier layer is prepared by a physical vapor deposition process and has a thickness of 2 to 10 nm.
  • the silicon gate layer is composed of polysilicon or amorphous silicon.
  • the hard mask layer is composed of a silicon oxide, silicon nitride or silicon oxide/silicon nitride stacked structure.
  • the dry etching process is used for anisotropic etching of the A1N barrier layer, the Mo-based metal gate and the high-k dielectric
  • the BC1 3 -based etching gas is used for the A1N barrier layer, the Mo-based metal gate and High K dielectrics perform anisotropic etching with high selectivity.
  • the BC1 3 -based etching gas includes, in addition to BC1 3 , one or more gases of Cl 2 , 0 2 , Ar as an etching gas.
  • the ratio of Cl 2 to BC1 3 in the BC1 3 -based etching gas is (T1 : 4, the ratio of 0 2 to BC1 3 is ( ⁇ : 8, the ratio of Ar to BC1 3 is 1: 5 to 1: 2).
  • the dry etching process conditions of the A1N barrier layer, the Mo-based metal gate and the high-k dielectric stacked structure are: the upper electrode power is 140 ⁇ 450W, the lower electrode power is 30 ⁇ 120W, and the pressure is 4 ⁇ 15mt.
  • the total flow rate of the BC1 3 -based etching gas is 5 (Tl30 SCCm , and the temperature of the cavity and the electrode is controlled at 5 ( ⁇ 80 degrees).
  • FIG. 1 A flow chart of an etching method of a Mo-based metal gate stacked structure using aluminum nitride as a barrier layer according to FIG. 1, and FIGS. 2 to 4 show a barrier layer of aluminum nitride according to an embodiment of the present invention.
  • FIG. 2 is a scanning electron micrograph of a M0A1N metal gate, an A1N barrier layer, a polysilicon gate, and a Si0 2 hard mask formed on a HfSiAlON high-k dielectric in accordance with an embodiment of the present invention.
  • the specific preparation process is that an interface Si0 2 layer is formed on the Si substrate by RT0, and then a 3 nm HfSiAlON high K medium is formed by a physical vapor deposition process; after 900 degree high temperature treatment, a thickness of 14 nm is formed by a physical vapor deposition process.
  • FIG. 3 is a scanning electron micrograph of an etched film using an optimized hard mask and polysilicon etch process in accordance with an embodiment of the present invention.
  • the specific process is to lithography and hard mask etching for the prepared Si/SiO 2 /HfSiA10N/MoAlN/AlN/poly/SiO 2 stacked structure; after the glue is removed, the hard mask is used as a mask.
  • FIG. 4 is a scanning electron micrograph of an A1N barrier layer, a ⁇ / ⁇ metal gate, and a sorghum dielectric laminate structure etched using a BCl 3 /0 2 /Ar etching gas in accordance with an embodiment of the present invention.
  • the specific process is as follows: on the basis of FIG. 2 and FIG. 3, the hard mask and the silicon gate layer are etched by a dry etching process, and the ratio of the BCl 3 /Cl 2 /Ar mixed gas is optimized and etched. Parameters such as the upper and lower electrode power, pressure, and temperature of the cavity and the electrode etch the A1N barrier layer, the MoAIN metal gate, and the high-k dielectric stack structure. It can be seen from Fig. 4 that after etching, the etching profiles of the polysilicon and the metal gate are steep, no etching residue, and the etching process has less loss on the Si substrate.
  • the etching method of the Mo-based metal gate stack structure using aluminum nitride as a barrier layer in the gate-first process provided by the present invention is suitable for the integration of high dielectric constant dielectric/metal gate in nano-scale CMOS devices. It provides the necessary guarantee for the integration of high K/metal gates.

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Description

以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方法 技术领域
本发明涉及集成电路制造技术领域，尤其涉及一种先栅工艺中以氮化铝为势垒层 的 Mo基金属栅叠层结构的刻蚀方法。 背景技术
随着半导体器件的特征尺寸进入到 45nm技术节点以后， 为了减小栅隧穿电流， 降低器件的功耗，并彻底消除多晶硅耗尽效应和 P型金属一氧化物一半导体场效应晶 体管 （PM0SFET ) 中 B 穿透引起的可靠性问题， 缓解费米能级钉扎效应， 采用高介电 常数（K ) /金属栅材料代替传统的 Si02/多晶硅（poly ) 结构已经成为了必然的选择。
对于引入高 K、金属栅材料的纳米级 CMOS器件来说，为了得到较好的短沟效应以 及合适的阈值， N管和 P管的功函数应在 Si的导带底附近（4. leV左右）和价带顶附 近 （5. 2eV左右）。 Mo金属栅由于具有低的电阻率 （5 X 10— 6 Q . cra)、 高的熔点 （大于 2600度） 以及 （100 ) 晶向的 Mo金属栅展现出 5eV附近的功函数， 使得 Mo基金属栅 成为 P管金属栅材料的有力候选者。 另外， 为了降低刻蚀的难度， 不过多地增加原有 CMOS工艺的复杂性，一般采用插入式金属栅的叠层结构（即硅栅 /金属栅的叠层结构） 代替纯金属栅电极来实现高 K、金属栅材料的集成。但由于直接在 Mo基金属栅上淀积 硅栅时的高温过程导致 Mo金属栅与硅栅发生反应，我们在 Mo基金属栅与硅栅间加入 一层热稳定性很高的金属氮化物势垒层来提高热稳定性。加入势垒层后虽解决了热稳 定性的问题， 但是也增加了高 K/金属栅结构刻蚀的难度。 因此， 解决好势垒层 /Mo基 金属栅叠层结构的刻蚀是实现 P管 Mo基金属栅集成的有力保证。 发明内容
(一） 要解决的技术问题
本发明针对的纳米级 CMOS器件制备过程中引入高 K、 金属栅材料后， 为实现高 Κ/金属栅集成的新课题， 提供一种先栅工艺中以氮化铝为势垒层的 Mo基金属栅叠层 结构的刻蚀方法。
(二） 技术方案
为达到上述目的， 本发明提供了一种以氮化铝为势垒层的 Mo基金属栅叠层结构 的刻蚀方法， 该方法包括：
在半导体衬底上依次形成界面 Si02层、 高 K栅介质层、 Mo基金属栅电极层、 A1N 势垒层、 硅栅层和硬掩膜层；
对形成界面 Si02层、 高 K栅介质层、 Mo基金属栅电极层、 A1N势垒层、 硅栅层和 硬掩膜层的半导体衬底进行光刻和硬掩膜的刻蚀；
去胶， 以硬掩膜为掩蔽， 采用干法刻蚀工艺对硅栅层进行高选择比的各向异性刻 蚀；
采用干法刻蚀工艺对 A1N势垒层、 Mo基金属栅和高 K介质进行各向异性刻蚀。 上述方案中， 所述高 K栅介质层由 Hf02、 HfON、 HfA10、 HfA10N、 HfTaO, HfTaON, HfSiO、 HfSiON、 HfLaO或者 HfLaON形成。
上述方案中， 所述 Mo基金属栅电极层由 Mo、 MoN、 MoAIN或者 ΜοΑ1Ν、 MoN、 Mo 中任意两种材料的 层结构构成。
上述方案中， 所述 A1N势垒层通过物理气相淀积工艺制备， 其厚度为 2至 10纳 米。
上述方案中， 所述硅栅层由多晶硅或非晶硅构成。
上述方案中， 所述硬掩膜层由氧化硅、 氮化硅或氧化硅 /氮化硅叠层结构构成。 上述方案中，所述采用干法刻蚀工艺对 A1N势垒层、 Mo基金属栅和高 K介质进行 各向异性刻蚀， 是采用 BC13基刻蚀气体对 A1N势垒层、 Mo基金属栅和高 K介质进行 高选择比的各向异性刻蚀。
上述方案中， 所述 BC13基刻蚀气体除了包括 BC13外， 还包括 Cl2、 02、 Ar中的一 种或几种气体作为刻蚀气体。
上述方案中， 所述 BC13基刻蚀气体中 Cl2与 BC13的比率为（Tl : 4， 02与 BC13的比 率为 0〜1： 8， Ar与 BC13的比率为 1 : 5到 1 : 2。
上述方案中，所述 A1N势垒层、 Mo基金属栅和高 K介质叠层结构的干法刻蚀工艺 条件为： 上电极功率为 14(T450W， 下电极功率为 3(T120W， 压强为 4~15mt， BC13基刻 蚀气体的总流量为 5(Tl30ScCni， 腔体和电极的温度控制在 50〜80度。
(三） 有益效果
从上述技术方案可以看出， 本发明具有以下有益效果：
1、本发明提出的先栅工艺中以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方 法， 没有因为势垒层的存在而增加刻蚀的复杂性， 势垒层与 M0基金属栅的刻蚀通过 一步刻蚀完成； 该刻蚀方法与现有的 CMOS工艺兼容性较高； 通过优化 MN势垒层、 Mo基金属栅和高 K介质叠层结构的刻蚀工艺不仅得到陡直的刻蚀剖面， 而且对 Si衬 底的损耗很小， 为实现高 K/金属栅的集成提供了必要保证。
2、本发明提出的先栅工艺中以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方 法， 没有因为在 Mo基金属栅上增加了 A1N势垒层而增加刻蚀工艺的复杂性， 势垒层 与 M0基金属栅的刻蚀通过一步刻蚀完成。
3、本发明提出的先栅工艺中以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方 法， 不仅可以得到陡直的刻蚀剖面， 而且对 Si衬底的损耗很小， 满足集成工艺中引 入高 K、 金属栅材料后对刻蚀工艺的要求。
4、本发明提出的先栅工艺中以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方 法， 与现有的 CMOS工艺兼容性较高。 附图说明
图 1是本发明提供的以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方法流程 图；
图 2为依照本发明实施例在 HfSiAlON高 K介质上， 依次形成 M0A1N金属栅、 A1N 势垒层、 多晶硅栅以及 Si02硬掩膜后的扫描电镜照片；
图 3为依照本发明实施例采用优化的硬掩膜和多晶硅刻蚀工艺刻蚀后的扫描电镜 照片；
图 4为依照本发明实施例采用 BCl3/02/Ar刻蚀气体刻蚀插 A1N势垒层、 MoAIN金 属栅和高 K介质叠层结构后的扫描电镜照片。 具体实施方式
为使本发明的目的、 技术方案和优点更加清楚明白， 以下结合具体实施例， 并参 照附图， 对本发明进一步详细说明。
如图 1所示， 图 1是本发明提供的以氮化铝为势垒层的 Mo基金属栅叠层结构的 刻蚀方法流程图， 该方法包括：
步骤 1 : 在半导体衬底上依次形成界面 Si02层、 高 K栅介质层、 Mo基金属栅电极 层、 A1N势垒层、 硅栅层和硬掩膜层；
歩骤 2: 对形成界面 Si02层、 高 K栅介质层、 Mo基金属栅电极层、 A1N势垒层、 硅栅层和硬掩膜层的半导体衬底进行光刻和硬掩膜的刻蚀； 步骤 3: 去胶， 以硬掩膜为掩蔽， 采用干法刻蚀工艺对硅栅层进行高选择比的各 向异性刻蚀；
步骤 4: 采用干法刻蚀工艺对 MN势垒层、 Mo基金属栅和高 K介质进行各向异性 刻蚀。
其中， 所述高 K栅介质层由 Hf02、 HfON、 HfA10、 HfA10N、 HfTaO、 HfTaON、 HfSiO、 HfSiON、 HfLaO或者 HfLaON形成。 所述 Mo基金属栅电极层由 Mo、 MoN、 MoAIN或者 MoAIN, MoN、 Mo中任意两种材料的叠层结构构成。所述 A1N势垒层通过物理气相淀积 工艺制备， 其厚度为 2至 10纳米。 所述硅栅层由多晶硅或非晶硅构成。 所述硬掩膜 层由氧化硅、 氮化硅或氧化硅 /氮化硅叠层结构构成。
其中，所述采用干法刻蚀工艺对 A1N势垒层、 Mo基金属栅和高 K介质进行各向异 性刻蚀， 是采用 BC13基刻蚀气体对 A1N势垒层、 Mo基金属栅和高 K介质进行高选择 比的各向异性刻蚀。 所述 BC13基刻蚀气体除了包括 BC13外， 还包括 Cl2、 02、 Ar中的 一种或几种气体作为刻蚀气体。 所述 BC13基刻蚀气体中 Cl2与 BC13的比率为 (T1 : 4, 02与 BC13的比率为（Π : 8, Ar与 BC13的比率为 1 : 5到 1 : 2。
其中，所述 A1N势垒层、 Mo基金属栅和高 K介质叠层结构的干法刻蚀工艺条件为： 上电极功率为 140〜450W， 下电极功率为 30~120W， 压强为 4~15mt， BC13基刻蚀气体的 总流量为 5(Tl30SCCm， 腔体和电极的温度控制在 5(Γ80度。
基于图 1所述的以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方法流程图， 图 2至图 4示出了依照本发明实施例以氮化铝为势垒层的 Mo基金属栅叠层结构的刻 蚀方法。
图 2为依照本发明实施例在 HfSiAlON高 K介质上， 依次形成 M0A1N金属栅、 A1N 势垒层、 多晶硅栅以及 Si02硬掩膜后的扫描电镜照片。 其具体制备工艺为在 Si衬底 上 RT0生成界面 Si02层，然后采用物理气相淀积工艺形成 3nm的 HfSiAlON高 K介质； 经 900度高温处理后， 通过物理气相淀积工艺形成厚度为 14nm的 MoAIN金属栅， 并 在位淀积 5. Onra的 A1N势垒层；采用低压化学气相淀积工艺形成厚度为 110纳米的多 晶硅， 并在其上采用低温热氧化工艺形成厚度为 65纳米的二氧化硅硬掩膜。 从图 2 可以看出， 加入势垒层后得到热稳定性很高的插入式金属栅叠层结构， 满足器件制备 过程的需要。
图 3为依照本发明实施例采用优化的硬掩膜和多晶硅刻蚀工艺刻蚀后的扫描电镜 照片。 其具体工艺为对于已经制备好的 Si/Si02/HfSiA10N/MoAlN/ AlN/poly/ Si02叠 层结构， 进行光刻和硬掩膜的刻蚀； 去胶后， 以硬掩膜为掩蔽， 对多晶硅栅进行高选 择比的各向异性刻蚀。从图 2可以看出，刻蚀后，不仅得到了陡直的多晶硅刻蚀剖面， 而且该工艺对下面势垒层的选择比很高。
图 4为依照本发明实施例采用 BCl3/02/Ar刻蚀气体刻蚀插 A1N势垒层、 Μο/ Ν金 属栅和高 Κ介质叠层结构后的扫描电镜照片。其具体工艺为：在图 2和图 3的基础上， 采用干法刻蚀工艺对硬掩膜和硅栅层进行刻蚀后， 通过优化 BCl3/Cl2/Ar混合气体的 比率、 刻蚀工艺的上下电极功率、 压力以及腔体和电极的温度等参数对 A1N势垒层、 MoAIN金属栅和高 K介质叠层结构进行刻蚀。 从图 4可以看出， 刻蚀后， 多晶硅和金 属栅的刻蚀剖面都是陡直的， 无刻蚀残余， 且该刻蚀工艺对 Si衬底的损耗较少。
因此， 本发明所提供的先栅工艺中以氮化铝为势垒层的 Mo基金属栅叠层结构的 刻蚀方法，适于纳米级 CMOS器件中高介电常数介质 /金属栅的集成需要，为实现高 K/ 金属栅的集成提供了必要保证。
以上所述的具体实施例， 对本发明的目的、技术方案和有益效果进行了进一步详 细说明， 所应理解的是， 以上所述仅为本发明的具体实施例而已， 并不用于限制本发 明， 凡在本发明的精神和原则之内， 所做的任何修改、 等同替换、 改进等， 均应包含 在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方法， 其特征在于， 该 方法包括：
在半导体衬底上依次形成界面 Si02层、 高 K栅介质层、 Mo基金属栅电极层、 A1N 势垒层、 硅栅层和硬掩膜层；
对形成界面 Si02层、 高 K栅介质层、 Mo基金属栅电极层、 A1N势垒层、 硅栅层和 硬掩膜层的半导体衬底进行光刻和硬掩膜的刻蚀；
去胶， 以硬掩膜为掩蔽， 采用干法刻蚀工艺对硅栅层进行高选择比的各向异性刻 蚀；
采用干法刻蚀工艺对 A1N势垒层、 Mo基金属栅和高 K介质进行各向异性刻蚀。
2、根据权利要求 1所述的以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方法， 其特征在于，所述高 K栅介质层由 Hf02、 HfON、 HfA10、 HfA10N、 HfTaO、 HfTaON、 HfSiO、 HfSiON、 HfLaO或者 HfLaON形成。
3、根据权利要求 1所述的以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方法， 其特征在于， 所述 Mo基金属栅电极层由 Mo、 MoN、 MoAIN或者 ΜοΑ1Ν、 MoN、 Mo中任 意两种材料的叠层结构构成。
4、根据权利要求 1所述的以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方法， 其特征在于， 所述 A1N势垒层通过物理气相淀积工艺制备， 其厚度为 2至 10纳米。
5、根据权利要求 1所述的以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方法， 其特征在于， 所述硅栅层由多晶硅或非晶硅构成。
6、根据权利要求 1所述的以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方法， 其特征在于， 所述硬掩膜层由氧化硅、 氮化硅或氧化硅 /氮化硅叠层结构构成。
7、根据权利要求 1所述的以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方法， 其特征在于，所述采用干法刻蚀工艺对 A1N势垒层、 Mo基金属栅和高 K介质进行各向 异性刻蚀， 是采用 BC13基刻蚀气体对 A1N势垒层、 Mo基金属栅和高 K介质进行高选 择比的各向异性刻蚀。
8、根据权利要求 7所述的以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方法， 其特征在于， 所述 BC13基刻蚀气体除了包括 BC13外， 还包括 Cl2、 02、 Ar中的一种或 几种气体作为刻蚀气体。
9、 根据权利要求 8所述的以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方 法， 其特征在于， 所述 BC13基刻蚀气体中 Cl2与 BC13的比率为（Tl: 4， 02与 BC13的比 率为 (Γΐ: 8， Ar与 BC13的比率为 1: 5到 1: 2。
10、 根据权利要求 1所述的以氮化铝为势垒层的 Mo基金属栅叠层结构的刻蚀方 法， 其特征在于， 所述 A1N势垒层、 Mo基金属栅和高 K介质叠层结构的干法刻蚀工艺 条件为： 上电极功率为 14(T450W， 下电极功率为 3(Tl20W， 压强为 i5mt， BC13基刻 蚀气体的总流量为 5(Tl30SCCm， 腔体和电极的温度控制在 5CT80度。
PCT/CN2010/001459 2010-04-21 2010-09-21 以氮化铝为势垒层的mo基金属栅叠层结构的刻蚀方法 Ceased WO2011130890A1 (zh)

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