WO2011130890A1 - Method of etching mo-based metal gate stacked strecture based aluminum nitride barrier layer - Google Patents

Abstract

Provided is a method of etching a Mo-based metal gate stacked structure based on an aluminum nitride barrier layer, the method includes: successively forming an interface SiO₂ layer, a high k gate dielectrics layer, a Mo-based metal gate layer, an AlN barrier layer, a silicon gate layer and a hard mask layer on the substrate; photo lithographing the formed substrate and etching the hard mask layer; removing a resist, shielding with the hard mask, high selective etching anisotropically the silicon gate layer by dry etching process; etching anisotropically the AlN barrier layer, the Mo-based metal gate and the high k dielectrics by dry etching process. The optimal etching process for the stacked structure having the AlN barrier layer, the Mo-based metal gate and the high k dielectrics not only obtains steep profile, but also has very small loss of the Si substrate, which provides necessary guarantee for achieving integration of the high k/metal gate.

Description

 Etching method of Mo-based metal gate stacked structure using aluminum nitride as barrier layer

 The present invention relates to the field of integrated circuit manufacturing technology, and in particular, to an etching method of a Mo-based metal gate stacked structure using aluminum nitride as a barrier layer in a gate-first process. Background technique

As the feature size of the semiconductor device enters the 45nm technology node, in order to reduce the gate tunneling current, the power consumption of the device is reduced, and the polysilicon depletion effect and the P-type metal oxide-semiconductor field effect transistor (PM0SFET) are completely eliminated. The reliability problem caused by B-penetration and the mitigation of the Fermi level pinning effect have become an inevitable choice to replace the traditional Si0 ₂ /polysilicon (poly) structure with a high dielectric constant (K) / metal gate material.

For nano-scale CMOS devices with high-k, metal-gate materials, the work function of N- and P-tubes should be near the bottom of the conduction band of Si (4. leV) in order to obtain a better short-channel effect and a suitable threshold. ) and the vicinity of the price band (about 5. 2eV). Since Mo metal gate having a low resistivity _{^{(5 X 10- 6 Q. Cra}} ), high melting point (greater than 2600 degrees) and Mo metal gate (100) to exhibit a work function of 5eV nearby, Mo based metal such The gate becomes a powerful candidate for P-tube metal gate materials. In addition, in order to reduce the difficulty of etching, but to increase the complexity of the original CMOS process, a laminated structure of a plug-in metal gate (ie, a stacked structure of a silicon gate/metal gate) is generally used instead of a pure metal gate electrode. High K, metal gate material integration. However, due to the high temperature process when depositing a silicon gate directly on the Mo-based metal gate, the Mo metal gate reacts with the silicon gate. We add a high thermal stability metal nitride potential between the Mo-based metal gate and the silicon gate. The barrier layer is used to improve thermal stability. Although the thermal stability problem is solved after the barrier layer is added, the difficulty of etching the high K/metal gate structure is also increased. Therefore, solving the etching of the barrier layer/Mo-based metal gate stack structure is a powerful guarantee for realizing the integration of the P-tube Mo-based metal gate. Summary of the invention

 (1) Technical problems to be solved

 In order to realize a new topic of high germanium/metal gate integration in the preparation process of the nano-scale CMOS device, a Mo-based barrier layer is provided in the gate-first process. An etching method of a metal gate stacked structure.

(ii) Technical solutions

In order to achieve the above object, the present invention provides a Mo-based metal gate stacked structure using aluminum nitride as a barrier layer. Etching method, the method includes:

Forming an interface Si0 ₂ layer, a high K gate dielectric layer, a Mo-based metal gate electrode layer, an A1N barrier layer, a silicon gate layer, and a hard mask layer on the semiconductor substrate;

Photolithography and hard mask etching of a semiconductor substrate forming an interface Si0 ₂ layer, a high K gate dielectric layer, a Mo-based metal gate electrode layer, an A1N barrier layer, a silicon gate layer, and a hard mask layer;

 The glue is removed, and the hard mask is used as a mask, and the silicon gate layer is subjected to a high selective ratio anisotropic etching by a dry etching process;

Anisotropic etching of the A1N barrier layer, the Mo-based metal gate, and the high-k dielectric is performed by a dry etching process. In the above solution, the high-k gate dielectric layer is formed of Hf0 ₂ , HfON, HfA10, HfA10N, HfTaO, HfTaON, HfSiO, HfSiON, HfLaO or HfLaON.

 In the above aspect, the Mo-based metal gate electrode layer is composed of a layer structure of any two of Mo, MoN, MoAIN or ΜοΑ1Ν, MoN, and Mo.

 In the above solution, the A1N barrier layer is prepared by a physical vapor deposition process and has a thickness of 2 to 10 nm.

 In the above solution, the silicon gate layer is made of polysilicon or amorphous silicon.

In the above aspect, the hard mask layer is formed of a silicon oxide, silicon nitride or silicon oxide/silicon nitride stacked structure. In the above solution, the dry etching process is used for anisotropic etching of the A1N barrier layer, the Mo-based metal gate and the high-k dielectric, and the BC1 ₃ -based etching gas is used for the A1N barrier layer and the Mo-based metal. The gate and high K dielectrics perform an anisotropic etch with a high selectivity ratio.

In the above solution, the BC1 ₃ -based etching gas includes one or more gases of Cl ₂ , 0 ₂ , and Ar as an etching gas in addition to the BC1 ₃ .

In the above solution, the ratio of Cl ₂ to BC1 ₃ in the BC1 ₃ -based etching gas is (T1 : 4, the ratio of 0 ₂ to BC1 ₃ is 0 to 1: 8, the ratio of Ar to BC1 ₃ is 1: 5; To 1: 2.

In the above solution, the dry etching process conditions of the A1N barrier layer, the Mo-based metal gate, and the high-k dielectric stacked structure are as follows: the upper electrode power is 14 (T450W, the lower electrode power is 3 (T120W, the pressure is 4) ~15mt, BC1 The total flow rate of the ₃ -base etching gas is 5 (Tl30 _S c _C ni, and the temperature of the cavity and the electrode is controlled at 50 to 80 degrees.

(3) Beneficial effects

 As can be seen from the above technical solutions, the present invention has the following beneficial effects:

1. The etching method of the Mo-based metal gate stack structure using aluminum nitride as a barrier layer in the gate-first process proposed by the present invention, without increasing the etching complexity due to the existence of the barrier layer, the barrier layer and Etching of the M0-based metal gate One-step etching is completed; the etching method is highly compatible with existing CMOS processes; not only a steep etching profile is obtained by an etching process that optimizes the MN barrier layer, the Mo-based metal gate, and the high-k dielectric layer structure. Moreover, the loss on the Si substrate is small, which provides the necessary guarantee for the integration of the high K/metal gate.

 2. The etching method of the Mo-based metal gate stack structure using aluminum nitride as a barrier layer in the gate-first process proposed by the present invention does not increase the etching process by adding an A1N barrier layer on the Mo-based metal gate. The complexity of the barrier layer and the etching of the M0-based metal gate is completed by one-step etching.

 3. The etching method of the Mo-based metal gate stack structure using aluminum nitride as a barrier layer in the gate-first process proposed by the present invention can not only obtain a steep etch profile, but also has a small loss on the Si substrate. To meet the requirements of the etching process after introducing high K and metal gate materials in the integrated process.

 4. The etching method of the Mo-based metal gate stack structure using aluminum nitride as a barrier layer in the gate-first process proposed by the present invention has high compatibility with the existing CMOS process. DRAWINGS

 1 is a flow chart showing an etching method of a Mo-based metal gate stacked structure using aluminum nitride as a barrier layer provided by the present invention;

2 is a scanning electron micrograph of a M0A1N metal gate, an A1N barrier layer, a polysilicon gate, and a Si0 ₂ hard mask formed on a HfSiAlON high-k dielectric in accordance with an embodiment of the present invention;

 3 is a scanning electron micrograph of an etched film using an optimized hard mask and polysilicon etching process in accordance with an embodiment of the present invention;

4 is a scanning electron micrograph of an A1N barrier layer, a MoAIN metal gate, and a high-k dielectric laminate structure etched using a BCl ₃ /0 ₂ /Ar etching gas in accordance with an embodiment of the present invention. detailed description

 In order to make the objects, the technical solutions and the advantages of the present invention more comprehensible, the present invention will be further described in detail below with reference to the accompanying drawings.

 As shown in FIG. 1, FIG. 1 is a flow chart of an etching method of a Mo-based metal gate stacked structure using aluminum nitride as a barrier layer according to the present invention, the method comprising:

Step 1: forming an interface Si0 ₂ layer, a high K gate dielectric layer, a Mo-based metal gate electrode layer, an A1N barrier layer, a silicon gate layer, and a hard mask layer on the semiconductor substrate;

Step 2: Photolithography and hard masking of a semiconductor substrate forming an interface Si0 ₂ layer, a high K gate dielectric layer, a Mo-based metal gate electrode layer, an A1N barrier layer, a silicon gate layer, and a hard mask layer eclipse; Step 3: removing the glue, masking with a hard mask, and performing a high selective ratio anisotropic etching on the silicon gate layer by a dry etching process;

 Step 4: Anisotropic etching of the MN barrier layer, the Mo-based metal gate, and the high-k dielectric is performed by a dry etching process.

Wherein, the high-k gate dielectric layer is formed of Hf0 ₂ , HfON, HfA10, HfA10N, HfTaO, HfTaON, HfSiO, HfSiON, HfLaO or HfLaON. The Mo-based metal gate electrode layer is composed of a laminated structure of any two materials of Mo, MoN, MoAIN or MoAIN, MoN, and Mo. The A1N barrier layer is prepared by a physical vapor deposition process and has a thickness of 2 to 10 nm. The silicon gate layer is composed of polysilicon or amorphous silicon. The hard mask layer is composed of a silicon oxide, silicon nitride or silicon oxide/silicon nitride stacked structure.

Wherein, the dry etching process is used for anisotropic etching of the A1N barrier layer, the Mo-based metal gate and the high-k dielectric, and the BC1 ₃ -based etching gas is used for the A1N barrier layer, the Mo-based metal gate and High K dielectrics perform anisotropic etching with high selectivity. The BC1 ₃ -based etching gas includes, in addition to BC1 ₃ , one or more gases of Cl ₂ , 0 ₂ , Ar as an etching gas. The ratio of Cl ₂ to BC1 ₃ in the BC1 ₃ -based etching gas is (T1 : 4, the ratio of 0 ₂ to BC1 ₃ is (Π : 8, the ratio of Ar to BC1 ₃ is 1: 5 to 1: 2).

The dry etching process conditions of the A1N barrier layer, the Mo-based metal gate and the high-k dielectric stacked structure are: the upper electrode power is 140~450W, the lower electrode power is 30~120W, and the pressure is 4~15mt. The total flow rate of the BC1 ₃ -based etching gas is 5 (Tl30 _SCCm , and the temperature of the cavity and the electrode is controlled at 5 (Γ80 degrees).

 A flow chart of an etching method of a Mo-based metal gate stacked structure using aluminum nitride as a barrier layer according to FIG. 1, and FIGS. 2 to 4 show a barrier layer of aluminum nitride according to an embodiment of the present invention. An etching method for a Mo-based metal gate stacked structure.

2 is a scanning electron micrograph of a M0A1N metal gate, an A1N barrier layer, a polysilicon gate, and a Si0 ₂ hard mask formed on a HfSiAlON high-k dielectric in accordance with an embodiment of the present invention. The specific preparation process is that an interface Si0 ₂ layer is formed on the Si substrate by RT0, and then a 3 nm HfSiAlON high K medium is formed by a physical vapor deposition process; after 900 degree high temperature treatment, a thickness of 14 nm is formed by a physical vapor deposition process. MoAIN metal gate, and in-situ deposition of Onra's A1N barrier layer; low-pressure chemical vapor deposition process to form polysilicon with a thickness of 110 nm, and low temperature thermal oxidation process on it to form a thickness of 65 nm dioxide Silicon hard mask. It can be seen from Fig. 2 that the plug-in metal gate stack structure with high thermal stability is obtained after the barrier layer is added, which satisfies the needs of the device preparation process.

3 is a scanning electron micrograph of an etched film using an optimized hard mask and polysilicon etch process in accordance with an embodiment of the present invention. The specific process is to lithography and hard mask etching for the prepared Si/SiO ₂ /HfSiA10N/MoAlN/AlN/poly/SiO ₂ stacked structure; after the glue is removed, the hard mask is used as a mask. High-selection of polysilicon gate Selective anisotropic etching. It can be seen from Fig. 2 that after etching, not only a steep polysilicon etching profile is obtained, but also the selection ratio of the lower barrier layer is high.

4 is a scanning electron micrograph of an A1N barrier layer, a Μο/ Ν metal gate, and a sorghum dielectric laminate structure etched using a BCl ₃ /0 ₂ /Ar etching gas in accordance with an embodiment of the present invention. The specific process is as follows: on the basis of FIG. 2 and FIG. 3, the hard mask and the silicon gate layer are etched by a dry etching process, and the ratio of the BCl ₃ /Cl ₂ /Ar mixed gas is optimized and etched. Parameters such as the upper and lower electrode power, pressure, and temperature of the cavity and the electrode etch the A1N barrier layer, the MoAIN metal gate, and the high-k dielectric stack structure. It can be seen from Fig. 4 that after etching, the etching profiles of the polysilicon and the metal gate are steep, no etching residue, and the etching process has less loss on the Si substrate.

 Therefore, the etching method of the Mo-based metal gate stack structure using aluminum nitride as a barrier layer in the gate-first process provided by the present invention is suitable for the integration of high dielectric constant dielectric/metal gate in nano-scale CMOS devices. It provides the necessary guarantee for the integration of high K/metal gates.

 The above described specific embodiments of the present invention are described in detail, and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Claims

Rights request 1. A method of etching a Mo-based metal gate stack structure using aluminum nitride as a barrier layer, the method comprising: Forming an interface Si0 ₂ layer, a high K gate dielectric layer, a Mo-based metal gate electrode layer, an A1N barrier layer, a silicon gate layer, and a hard mask layer on the semiconductor substrate; Photolithography and hard mask etching of a semiconductor substrate forming an interface Si0 ₂ layer, a high K gate dielectric layer, a Mo-based metal gate electrode layer, an A1N barrier layer, a silicon gate layer, and a hard mask layer;  The glue is removed, and the hard mask is used as a mask, and the silicon gate layer is subjected to a high selective ratio anisotropic etching by a dry etching process;  Anisotropic etching of the A1N barrier layer, the Mo-based metal gate, and the high-k dielectric is performed by a dry etching process. 2. The method of etching a Mo-based metal gate stack structure using aluminum nitride as a barrier layer according to claim 1, wherein the high-k gate dielectric layer is composed of Hf0 ₂ , HfON, HfA10, HfA10N , HfTaO, HfTaON, HfSiO, HfSiON, HfLaO or HfLaON.  The method for etching a Mo-based metal gate stack structure using aluminum nitride as a barrier layer according to claim 1, wherein the Mo-based metal gate electrode layer is composed of Mo, MoN, MoAIN or ΜοΑ1Ν , a laminated structure of any two materials of MoN and Mo.  The method for etching a Mo-based metal gate stack structure using aluminum nitride as a barrier layer according to claim 1, wherein the A1N barrier layer is prepared by a physical vapor deposition process, and the thickness thereof is It is 2 to 10 nanometers.  The method of etching a Mo-based metal gate stack structure using aluminum nitride as a barrier layer according to claim 1, wherein the silicon gate layer is made of polysilicon or amorphous silicon.  6. The method of etching a Mo-based metal gate stack structure using aluminum nitride as a barrier layer according to claim 1, wherein the hard mask layer is made of silicon oxide, silicon nitride or silicon oxide. / Silicon nitride stacked structure. The method for etching a Mo-based metal gate stack structure using aluminum nitride as a barrier layer according to claim 1, wherein the dry etching process is applied to the A1N barrier layer and the Mo-based layer. The anisotropic etching of the metal gate and the high-k dielectric is performed by using a BC1 ₃ -based etching gas for anisotropic etching of a high selectivity ratio of the A1N barrier layer, the Mo-based metal gate, and the high-k dielectric. The method for etching a Mo-based metal gate stack structure using aluminum nitride as a barrier layer according to claim 7, wherein the BC1 ₃ -based etching gas includes, in addition to BC1 ₃ One or several gases of Cl ₂ , 0 ₂ , and Ar are used as etching gases. 9. The etching method of a Mo-based metal gate stacked structure using aluminum nitride as a barrier layer according to claim 8. The method is characterized in that the ratio of Cl ₂ to BC1 ₃ in the BC1 ₃ -based etching gas is (Tl: 4, the ratio of 0 ₂ to BC1 ₃ is (Γΐ: 8, the ratio of Ar to BC1 ₃ is 1: 5 to 1: 2. 10. The method of etching a Mo-based metal gate stack structure using aluminum nitride as a barrier layer according to claim 1, wherein the A1N barrier layer, the Mo-based metal gate, and the high-k dielectric stack The dry etching process conditions of the layer structure are as follows: the upper electrode power is 14 (T450W, the lower electrode power is 3 (Tl20W, the pressure is i5mt, and the total flow rate of the BC1 ₃ -based etching gas is 5 (Tl30 _SCC m, cavity and The temperature of the electrode is controlled at 5 CT 80 degrees.