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WO2011000177A1 - Dispositif de stockage de données et procédé d'accès à des données - Google Patents

Dispositif de stockage de données et procédé d'accès à des données Download PDF

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Publication number
WO2011000177A1
WO2011000177A1 PCT/CN2009/073171 CN2009073171W WO2011000177A1 WO 2011000177 A1 WO2011000177 A1 WO 2011000177A1 CN 2009073171 W CN2009073171 W CN 2009073171W WO 2011000177 A1 WO2011000177 A1 WO 2011000177A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
scrambled
memory
error correction
correction code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2009/073171
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English (en)
Chinese (zh)
Inventor
杨宗杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silicon Motion Inc
Original Assignee
Silicon Motion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Motion Inc filed Critical Silicon Motion Inc
Publication of WO2011000177A1 publication Critical patent/WO2011000177A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to memory, and more particularly to data access to a memory. Background technique
  • the controller of the memory Before the data is stored in the memory, the controller of the memory usually processes the data with the scrambler in advance, so that bit 0 and bit 1 in the processed data are randomly distributed, and the processed data is stored in the memory. This avoids the excessive concentration of bit 0 or bit 1 in the data stored in the memory and affects data storage.
  • flash memory can be divided into single-level cell (SLC) and multi-level cell (MLC).
  • SLC single-level cell
  • MLC multi-level cell
  • the controller of the multi-level cell flash memory must previously use the scrambler to process the data that needs to be stored to the multi-level cell flash memory.
  • data processed by the scrambler has other drawbacks.
  • the controller transfers data to the memory by the data bus.
  • the data transmitted by the controller is bit 1
  • the potential of the data bus is raised to a logic high level
  • the data transmitted by the controller is bit 0, the potential of the data bus drops to a logic low level.
  • bit 0 or bit 1 carried by the data processed by the scrambler is randomly distributed, when the controller transfers the data to the memory for storage by the data bus, the potential on the data bus is frequently switched by the logic high potential. It is logic low or it is switched from logic low to logic high. Frequent switching of potentials causes the data bus to consume additional energy when transmitting data, thereby increasing the power consumption of the system.
  • the system including the controller and the memory is a portable device
  • the portable device since the portable device is usually powered by a battery, the high power consumption required for storing the data reduces the time the system can operate under a fixed amount of power, thereby making the system performance decline. Therefore, there is a need for a controller that can reduce the power consumption required to transfer data to a memory while processing data that needs to be stored to the memory with a scrambler to improve system performance.
  • the data storage device includes a memory and a controller.
  • the memory is used to store data.
  • the controller receives a first raw data for writing to the memory from a host, the controller generates at least one first input data according to the first original data, and respectively scrambles the plurality of random sequences according to the plurality of random sequences.
  • An optimally disturbing data of the transmission power is stored in the memory.
  • the invention also provides a data access method.
  • a data access method When receiving a first raw data for writing to a memory from a host, first generating at least one first input data based on the first original data. Then, the first input data is separately disturbed according to a plurality of random sequences to obtain a plurality of first scrambled data. Next, a plurality of transmission powers of the plurality of first scrambled data are calculated. Then, an optimal scrambled data having the smallest transmission power is selected from the plurality of first scrambled data for storage in the memory according to the plurality of transmission powers.
  • the controller according to the present invention can previously disturb the input data with a plurality of sets of random sequences, and then evaluate the transmission power required for each of the scrambled data to select the scrambled data having the lowest transmission power for transmission to the memory storage. Therefore, the memory controller of the present invention can reduce the power consumption of the system for data transmission, thereby improving system performance.
  • FIG. 1 is a schematic structural view of a data storage device according to the present invention.
  • FIG. 2 is a schematic structural diagram of a write data processing circuit of a controller according to the present invention
  • FIG. 3 is a flow chart of a method for processing write data according to the present invention
  • FIG. 4 is a schematic structural diagram of a part of a circuit of a transmission power calculation module according to the present invention
  • Figure 5 is a block diagram showing the structure of the read data processing circuit of the controller according to the present invention
  • Figure 6 is a flow chart showing the processing of the read data of the memory in accordance with the present invention
  • Figure 7 is a process write according to the present invention.
  • 500 is a controller; 502 is an error correction code decoder; 504 is an index separation module; 506 is a selector; 508 is a descrambler. detailed description
  • FIG. 1 is a block diagram showing the structure of a data storage device 104 in accordance with the present invention.
  • the data storage device 104 is coupled to a host 102 for storing data for the host 102 in accordance with instructions from the host 102.
  • data storage device 104 includes controller 112 and memory 114.
  • the memory 114 is used to store data, and the controller 112 accesses the data stored in the memory 114 for the host 102 in accordance with the instructions of the host 102.
  • a data bus is coupled between the controller 112 and the memory 114 for data transfer.
  • the controller 112 when the host 102 needs to store data 0 to the data storage device 104, the controller 112 first receives the data D 1 from the host 102 and then converts the data into an error correction code d (including the data portion and the check code portion), and then The error correction code is passed to memory 114 for storage.
  • the controller 112 When the host 102 needs to read data from the data storage device 104, the controller 112 first instructs the memory 114 to read the error correction code C 2 , then restores the error correction code C 2 to the data D 2 , and finally transmits the data D 2 to Host 102.
  • the controller 112 Before the controller 112 needs to store the data in the memory, it will disturb the bits 0 and 1 of the data, so that the bits 0 and 1 of the disturbed data are randomly distributed, and the transmission power of the data after the disturbance is reduced, thereby generating error correction.
  • the data bus transfers the error correction code from the controller 112 to the memory 114, the transmission power consumed by the data bus can be reduced.
  • the error correction code C 2 is stored in a data bit type that reduces the transmission power.
  • the data bus transmits the error correction code C 2 from the memory 114 to the controller 112
  • the transmission power consumed by the data bus can be reduced. Therefore, the data storage device 104 consumes less power than the existing device, and thus has higher performance than the existing device.
  • FIG. 2 is a block diagram showing the structure of a write data processing circuit of the controller 200 in accordance with the present invention. It is to be noted that, in order to embody the technical features of the present invention, FIG. 2 shows only the components related to the present invention, and the remaining common components are omitted.
  • the controller 200 includes a plurality of scramblers 201, 202, ..., 20N, a transmission power calculation module 212, a selector 214, an index addition module 216, and an error correction code encoder 218.
  • 3 is a flow diagram of a method 300 of processing write data in accordance with the present invention. The controller 200 of FIG. 2 processes data that the host needs to write to the memory in accordance with the method 300 of FIG.
  • the controller 200 receives a raw data for writing to the memory by the host (step 302).
  • the scramblers 201, 202, ..., 20N respectively scramble the original data according to the plurality of random sequences M 2 , ..., MN to obtain a plurality of scrambling data S 2 , ..., S N (step 304).
  • the scramblers 201, 202, ..., 20N respectively perform XOR operations on the original data 1 ⁇ and the plurality of random sequences Mi, M 2 , I, M N bit by bit to obtain a plurality of Disturb the data Si, S 2 , ..., S N .
  • the bits 0 and 1 of the disturbed data Si, S 2 , ..., S N are not excessively concentrated and appear randomly distributed, the bits of the memory can be made when the scrambled data Si, S 2 , ..., S N are stored in the memory. The error rate drops.
  • the transmission power calculation module 212 calculates a plurality of transmission powers required for transmission of the plurality of scrambling data S 2 , ..., S N on the data bus (step 306).
  • the transmission power calculation module 212 selects an optimal scrambling data having the minimum transmission power from the scrambling data Si, S 2 , ..., S N ⁇ according to the plurality of transmission powers (step 308), and outputs corresponding to the minimum transmission power.
  • the index L of the random sequence In one embodiment, the number of random sequences M 2 , ..., ⁇ 1 ⁇ 2 is N, and the number of bits of the index L is greater than or equal to Log 2 N.
  • the selector 214 selects the best scrambling data J 1 D having the minimum transmission power from the scrambling data S 2 , ..., 8 1 ⁇ according to the index ⁇ , and the index appending module 216 will correspond to the optimal scrambling data.
  • An index L of the random sequence is appended to the best scrambled data to obtain an output data (step 310).
  • the error correction code encoder 218 encodes the output data into an error correction code d for output to the memory for storage (step 312).
  • the error correction code except for the data part of the check code and the additional index ⁇ , it is the same as the data data bit of the best scramble data, so when the controller 200 transmits the error correction code to the memory from the data bus, the data bus The power consumption of the transmission can be significantly reduced.
  • a portion of the circuitry of the transmit power calculation module 400 includes a delay unit 402, an XOR unit 404, and a counter 406. It is assumed that the transmission power calculation module 400 receives a scrambled data S k from a scrambler, and the index K may be 1 to N.
  • the delay unit 402 delays the scrambled data S k by one clock interval according to a clock signal CLK to obtain the delay data S k '.
  • the XOR unit 404 performs an XOR operation on the scrambled data S k and the delayed data S k ' to obtain a transition data T, where the scrambled data S k changes from bit 0 to bit 1 or bit 1 When bit 0, the corresponding bit value of the converted data T is 1.
  • the counter 406 accumulates the number of times of the converted data T to obtain the transmission power CN. Therefore, the transmission power CN records the switching frequency of the scrambled data Sk from bit 0 to bit 1 or from bit 1 to bit 0. When the scrambling data S k CN higher switching frequencies, scrambling the data bus power required data S k are greater.
  • FIG. 5 is a block diagram showing the structure of a read data processing circuit of the controller 500 according to the present invention.
  • the controller 500 includes an error correction code decoder 502, an index separation module 504, a selector 506, and a descrambler 508.
  • 6 is a flow diagram of a method 600 of processing memory for processing memory in accordance with the present invention.
  • the controller 500 of FIG. 5 processes the read data of the memory according to the method 600, and transfers the processed data to the host.
  • the controller 500 receives a read command from the host, it instructs the memory to read an error correction code C 2 in accordance with the read command.
  • the error correction code decoder 502 decodes the error correction code C 2 to obtain an output data K 2 (step 602).
  • the separation module 504 ⁇ 2 index to extract index of a random sequence of the output data 12, and a data scrambling J 2 (step 604).
  • the selector 506 selects a descrambled random sequence M* corresponding to the index 1 2 from the plurality of random sequences M 2 , ..., M N according to the index 1 2 (step 606).
  • the descrambler 508 descrambles the scrambled data J 2 according to the descrambled random sequence M* to restore a raw data 126 (step 608).
  • the descrambler 508 disturbs the random sequence M*
  • the XOR operation is performed bit by bit with the scrambled data J 2 to obtain the original data D 2 .
  • the controller 500 outputs the original data 0 2 to the host to complete the reading operation of the data.
  • FIG. 7 is a schematic diagram of another embodiment of a method of processing write data in accordance with the present invention. It is assumed that the controller receives the original data D that needs to be written to the memory from the host as shown in (a) of FIG. According to the method 300 of processing the write data of FIG. 3, the controller will raw data. 1 is converted to the scrambled data having the minimum transmission power shown in (b) of FIG. 7, and the index K 1N for processing the random sequence of the scrambled data and the check code obtained by the error correction coding are added to the back end of the scrambled data ⁇ , and get the error correction code. However, for processing the original data D, a plurality of random sequences M 2 , ..., M N have the same data as the original data.
  • the same data length, and the scrambled data Si, S 2 , ..., S N generated by the scramblers 201, 202, ..., 20N also have the same data length as the original data. Since the controller 200 executing the method 300 requires multiple buffers with a large amount of storage to store random sequences
  • the controller 200 requires a lot of hardware cost to include multiple buffers.
  • the controller will raw data in advance! ⁇ [For example, the length of the original data is one data page (page)) is divided into a plurality of segment data ⁇ ⁇ , ⁇ 12 , . . . , D 1N as shown in (c) of FIG. 7 . Therefore, the length of each of the extent data Du, D 12 , ..., D 1N is only 1/N of the length of the original data 0 1 . Then, the controller sequentially converts the segment data Du, D 12 , . . . , D 1N into the scrambled data Jn, J 12 , and J 1N having the minimum transmission power shown in (d) of FIG. 7 . (d) of 7.
  • the data lengths of M 2 , - , M N and the scrambling data S 2 , - , S N also correspondingly become 1/N, so the controller is required to store the random sequences M 2 , ..., M N and the scrambling data S
  • the length (storage) of the buffers of 2 , ..., S N thus becomes 1/N, thereby reducing the hardware cost of the controller including the multiple buffers.
  • the scrambling operation and the error correction code encoding need to be performed in parallel to save operating time.
  • the scramblers 201, 202, ..., 20N need to be scrambled for the sector data D 13 and then selected by the transmission power calculation module 212 and the selector 214.
  • the disturbance data J 13 with the smallest transmission power is output.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Stored Programmes (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

La présente invention concerne un dispositif de stockage de données et un procédé d'accès à des données. Le procédé comprend les étapes suivantes : quand des premières données d'origine qui sont fournies pour être enregistrées dans la mémoire sont reçues depuis un ordinateur hôte, premièrement, au moins des premières données d'entrée sont générées selon les premières données d'origine ; ensuite, les premières données d'entrée sont respectivement mélangées selon des séquences aléatoires multiples pour obtenir des premières données multiples mélangées ; puis, plusieurs puissances de transmission des premières données multiples mélangées sont calculées ; ensuite, les données mélangées optimales avec la puissance de transmission minimum sont sélectionnées depuis les premières données multiples mélangées selon les puissances de transmission multiples devant être stockées dans la mémoire.
PCT/CN2009/073171 2009-07-01 2009-08-10 Dispositif de stockage de données et procédé d'accès à des données Ceased WO2011000177A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22246509P 2009-07-01 2009-07-01
US61/222,465 2009-07-01

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WO2011000177A1 true WO2011000177A1 (fr) 2011-01-06

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TW (1) TWI442221B (fr)
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Publication number Priority date Publication date Assignee Title
TWI562149B (en) * 2015-03-09 2016-12-11 Phison Electronics Corp Memory control circuit unit, memory storage apparatus and data accessing method

Citations (4)

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Publication number Priority date Publication date Assignee Title
US6304482B1 (en) * 2000-11-21 2001-10-16 Silicon Integrated Systems Corp. Apparatus of reducing power consumption of single-ended SRAM
WO2006022802A1 (fr) * 2004-01-09 2006-03-02 Matsushita Electronic Industrial Co, Ltd Embrouilleur a bande ultralarge destine a reduire la densite spectrale de puissance
CN1755819A (zh) * 2004-10-01 2006-04-05 其乐达科技股份有限公司 数字激光视盘（dvd）储存装置中实时循环冗余校验码之产生与扰乱
CN101447216A (zh) * 2007-09-28 2009-06-03 英特尔公司 在双数据速率存储系统中使用数据加扰来抑制电源噪声

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7672967B2 (en) * 2005-02-07 2010-03-02 Microsoft Corporation Method and system for obfuscating data structures by deterministic natural data substitution
WO2006112114A1 (fr) * 2005-03-31 2006-10-26 Matsushita Electric Industrial Co., Ltd. Dispositif et procede de cryptage de donnees

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6304482B1 (en) * 2000-11-21 2001-10-16 Silicon Integrated Systems Corp. Apparatus of reducing power consumption of single-ended SRAM
WO2006022802A1 (fr) * 2004-01-09 2006-03-02 Matsushita Electronic Industrial Co, Ltd Embrouilleur a bande ultralarge destine a reduire la densite spectrale de puissance
CN1755819A (zh) * 2004-10-01 2006-04-05 其乐达科技股份有限公司 数字激光视盘（dvd）储存装置中实时循环冗余校验码之产生与扰乱
CN101447216A (zh) * 2007-09-28 2009-06-03 英特尔公司 在双数据速率存储系统中使用数据加扰来抑制电源噪声

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CN101937705A (zh) 2011-01-05
TWI442221B (zh) 2014-06-21
TW201102819A (en) 2011-01-16
CN101937705B (zh) 2012-05-09

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