WO2011000177A1 - Data storage device and method for data access - Google Patents

Abstract

The present invention provides a data storage device and a method for data access. The method includes: when a first original data which is provided to be written in the storage is received from a host computer, firstly, at least a first inputting data is generated according to the first original data. Then, the first inputting data is respectively scrambled according to multiple random sequences to obtain multiple first scrambled data. Then, multiple transmission powers of the multiple first scrambled data are calculated. Then, the optimal scrambled data with the minimum transmission power is selected from the multiple first scrambled data according to the multiple transmission powers to be stored in the storage.

Description

 Data storage device and data access method

 The present invention relates to memory, and more particularly to data access to a memory. Background technique

 Before the data is stored in the memory, the controller of the memory usually processes the data with the scrambler in advance, so that bit 0 and bit 1 in the processed data are randomly distributed, and the processed data is stored in the memory. This avoids the excessive concentration of bit 0 or bit 1 in the data stored in the memory and affects data storage. For example, flash memory can be divided into single-level cell (SLC) and multi-level cell (MLC). When data is stored in the multi-level cell flash memory, if bit 0 or bit 1 of the data is excessively concentrated, the bit error rate of the stored data is increased. Therefore, the controller of the multi-level cell flash memory must previously use the scrambler to process the data that needs to be stored to the multi-level cell flash memory.

However, data processed by the scrambler has other drawbacks. In general, the controller transfers data to the memory by the data bus. When the data transmitted by the controller is bit 1, the potential of the data bus is raised to a logic high level; and when the data transmitted by the controller is bit 0, the potential of the data bus drops to a logic low level. Since bit 0 or bit 1 carried by the data processed by the scrambler is randomly distributed, when the controller transfers the data to the memory for storage by the data bus, the potential on the data bus is frequently switched by the logic high potential. It is logic low or it is switched from logic low to logic high. Frequent switching of potentials causes the data bus to consume additional energy when transmitting data, thereby increasing the power consumption of the system. When the system including the controller and the memory is a portable device, since the portable device is usually powered by a battery, the high power consumption required for storing the data reduces the time the system can operate under a fixed amount of power, thereby making the system performance decline. Therefore, there is a need for a controller that can reduce the power consumption required to transfer data to a memory while processing data that needs to be stored to the memory with a scrambler to improve system performance. Summary of the invention

 Accordingly, it is an object of the present invention to provide a data storage device that solves the problems of the prior art. In one of the embodiments, the data storage device includes a memory and a controller. The memory is used to store data. When the controller receives a first raw data for writing to the memory from a host, the controller generates at least one first input data according to the first original data, and respectively scrambles the plurality of random sequences according to the plurality of random sequences. Decoding a first input data to obtain a plurality of first scrambling data, calculating a plurality of transmission powers of the plurality of first scrambling data, and selecting a minimum from the plurality of first scrambling data according to the plurality of transmission powers An optimally disturbing data of the transmission power is stored in the memory.

 The invention also provides a data access method. When receiving a first raw data for writing to a memory from a host, first generating at least one first input data based on the first original data. Then, the first input data is separately disturbed according to a plurality of random sequences to obtain a plurality of first scrambled data. Next, a plurality of transmission powers of the plurality of first scrambled data are calculated. Then, an optimal scrambled data having the smallest transmission power is selected from the plurality of first scrambled data for storage in the memory according to the plurality of transmission powers.

 The controller according to the present invention can previously disturb the input data with a plurality of sets of random sequences, and then evaluate the transmission power required for each of the scrambled data to select the scrambled data having the lowest transmission power for transmission to the memory storage. Therefore, the memory controller of the present invention can reduce the power consumption of the system for data transmission, thereby improving system performance.

 The above and other objects, features and advantages of the present invention will become more < DRAWINGS

 1 is a schematic structural view of a data storage device according to the present invention;

 2 is a schematic structural diagram of a write data processing circuit of a controller according to the present invention; and FIG. 3 is a flow chart of a method for processing write data according to the present invention;

4 is a schematic structural diagram of a part of a circuit of a transmission power calculation module according to the present invention; Figure 5 is a block diagram showing the structure of the read data processing circuit of the controller according to the present invention; Figure 6 is a flow chart showing the processing of the read data of the memory in accordance with the present invention; and Figure ₇ is a process write according to the present invention. A schematic diagram of another embodiment of a method of entering data.

 [Main component symbol description]

 102 is a host; 104 is a data storage device; 112 is a controller; 114 is a memory; 200 is a controller; 201, 202, ..., 20N is a scrambler; 214 is a selector; 212 is a transmission power calculation module; Is an index add-on module; 218 is an error correction code encoder;

 400 is a transmission power calculation module; 402 is a delay unit; 404 is an XOR unit; 406 is a counter;

 500 is a controller; 502 is an error correction code decoder; 504 is an index separation module; 506 is a selector; 508 is a descrambler. detailed description

1 is a block diagram showing the structure of a data storage device 104 in accordance with the present invention. The data storage device 104 is coupled to a host 102 for storing data for the host 102 in accordance with instructions from the host 102. In one embodiment, data storage device 104 includes controller 112 and memory 114. The memory 114 is used to store data, and the controller 112 accesses the data stored in the memory 114 for the host 102 in accordance with the instructions of the host 102. In one embodiment, a data bus is coupled between the controller 112 and the memory 114 for data transfer. For example, when the host 102 needs to store data 0 to the data storage device 104, the controller 112 first receives the data D ₁ from the host 102 and then converts the data into an error correction code d (including the data portion and the check code portion), and then The error correction code is passed to memory 114 for storage. When the host 102 needs to read data from the data storage device 104, the controller 112 first instructs the memory 114 to read the error correction code C ₂ , then restores the error correction code C ₂ to the data D ₂ , and finally transmits the data D ₂ to Host 102.

Before the controller 112 needs to store the data in the memory, it will disturb the bits 0 and 1 of the data, so that the bits 0 and 1 of the disturbed data are randomly distributed, and the transmission power of the data after the disturbance is reduced, thereby generating error correction. Thus, when the data bus transfers the error correction code from the controller 112 to the memory 114, the transmission power consumed by the data bus can be reduced. The same, because The error correction code C ₂ is stored in a data bit type that reduces the transmission power. When the data bus transmits the error correction code C ₂ from the memory 114 to the controller 112, the transmission power consumed by the data bus can be reduced. Therefore, the data storage device 104 consumes less power than the existing device, and thus has higher performance than the existing device.

2 is a block diagram showing the structure of a write data processing circuit of the controller 200 in accordance with the present invention. It is to be noted that, in order to embody the technical features of the present invention, FIG. 2 shows only the components related to the present invention, and the remaining common components are omitted. In one embodiment, the controller 200 includes a plurality of scramblers 201, 202, ..., 20N, a transmission power calculation module 212, a selector 214, an index addition module 216, and an error correction code encoder 218. 3 is a flow diagram of a method 300 of processing write data in accordance with the present invention. The controller 200 of FIG. 2 processes data that the host needs to write to the memory in accordance with the method 300 of FIG. First, the controller 200 receives a raw data for writing to the memory by the host (step 302). Next, the scramblers 201, 202, ..., 20N respectively scramble the original data according to the plurality of random sequences M ₂ , ..., MN to obtain a plurality of scrambling data S ₂ , ..., S _N (step 304). In one embodiment, the scramblers 201, 202, ..., 20N respectively perform XOR operations on the original data 1^ and the plurality of random sequences Mi, M ₂ , I, M _N bit by bit to obtain a plurality of Disturb the data Si, S ₂ , ..., S _N . Since the bits 0 and 1 of the disturbed data Si, S ₂ , ..., S _N are not excessively concentrated and appear randomly distributed, the bits of the memory can be made when the scrambled data Si, S ₂ , ..., S _{N are} stored in the memory. The error rate drops.

Next, the transmission power calculation module 212 calculates a plurality of transmission powers required for transmission of the plurality of scrambling data S ₂ , ..., S _N on the data bus (step 306). Next, the transmission power calculation module 212 selects an optimal scrambling data having the minimum transmission power from the scrambling data Si, S ₂ , ..., S _N依据 according to the plurality of transmission powers (step 308), and outputs corresponding to the minimum transmission power. The index L of the random sequence. In one embodiment, the number of random sequences M ₂ , ..., ^1⁄2 is N, and the number of bits of the index L is greater than or equal to Log ₂ N. Next, the selector 214 selects the best scrambling data J _{1 D} having the minimum transmission power from the scrambling data S ₂ , ..., 8 ₁ ^ according to the index ^, and the index appending module 216 will correspond to the optimal scrambling data. An index L of the random sequence is appended to the best scrambled data to obtain an output data (step 310). Finally, the error correction code encoder 218 encodes the output data into an error correction code d for output to the memory for storage (step 312). By In the error correction code, except for the data part of the check code and the additional index ^, it is the same as the data data bit of the best scramble data, so when the controller 200 transmits the error correction code to the memory from the data bus, the data bus The power consumption of the transmission can be significantly reduced.

4 is a block diagram showing the structure of a portion of the circuit of the transmission power calculation module 400 in accordance with the present invention. A portion of the circuitry of the transmit power calculation module 400 includes a delay unit 402, an XOR unit 404, and a counter 406. It is assumed that the transmission power calculation module 400 receives a scrambled data S _k from a scrambler, and the index K may be 1 to N. The delay unit 402 delays the scrambled data S _k by one clock interval according to a clock signal CLK to obtain the delay data S _k '. Next, the XOR unit 404 performs an XOR operation on the scrambled data S _k and the delayed data S _k ' to obtain a transition data T, where the scrambled data S _k changes from bit 0 to bit 1 or bit 1 When bit 0, the corresponding bit value of the converted data T is 1. Next, the counter 406 accumulates the number of times of the converted data T to obtain the transmission power CN. Therefore, the transmission power CN records the switching frequency of the scrambled data Sk from bit 0 to bit 1 or from bit 1 to bit 0. When the scrambling data S _k CN higher switching frequencies, scrambling the data bus power required data S _k are greater.

FIG. 5 is a block diagram showing the structure of a read data processing circuit of the controller 500 according to the present invention. In one embodiment, the controller 500 includes an error correction code decoder 502, an index separation module 504, a selector 506, and a descrambler 508. 6 is a flow diagram of a method 600 of processing memory for processing memory in accordance with the present invention. The controller 500 of FIG. 5 processes the read data of the memory according to the method 600, and transfers the processed data to the host. First, when the controller 500 receives a read command from the host, it instructs the memory to read an error correction code C _{2 in} accordance with the read command. When the controller 500 receives the error correction code C ₂ from the memory, the error correction code decoder 502 decodes the error correction code C _{2 to} obtain an output data K ₂ (step 602).

Next, since the output data is data scrambling Κ ₂ contains random sequence index and the two parts, the separation module 504 Κ ₂ index to extract index of a random sequence of the output data _12, and a data scrambling J ₂ (step 604). Next, the selector 506 selects a descrambled random sequence M* corresponding to the index 1 ₂ from the plurality of random sequences M ₂ , ..., M _{N according} to the index 1 ₂ (step 606). Next, the descrambler 508 descrambles the scrambled data J ₂ according to the descrambled random sequence M* to restore a raw data 126 (step 608). In one embodiment, the descrambler 508 disturbs the random sequence M* The XOR operation is performed bit by bit with the scrambled data J ₂ to obtain the original data D ₂ . Finally, the controller 500 outputs the original data 0 ₂ to the host to complete the reading operation of the data.

₇ is a schematic diagram of another embodiment of a method of processing write data in accordance with the present invention. It is assumed that the controller receives the original data D that needs to be written to the memory from the host as shown in (a) of FIG. According to the method 300 of processing the write data of FIG. 3, the controller will raw data. _{1 is} converted to the scrambled data having the minimum transmission power shown in (b) of FIG. 7, and the index K _1N for processing the random sequence of the scrambled data and the check code obtained by the error correction coding are added to the back end of the scrambled data ^ , and get the error correction code. However, for processing the original data D, a plurality of random sequences M ₂ , ..., M _N have the same data as the original data. The same data length, and the scrambled data Si, S ₂ , ..., S _N generated by the scramblers 201, 202, ..., 20N also have the same data length as the original data. Since the controller 200 executing the method 300 requires multiple buffers with a large amount of storage to store random sequences

M ₂ , ..., M _N and the scrambled data Si, S ₂ , ..., S _N , the controller 200 requires a lot of hardware cost to include multiple buffers.

In another embodiment of the method of processing write data, the controller will raw data in advance! ^ [For example, the length of the original data is one data page (page)) is divided into a plurality of segment data Ο _η , ϋ ₁₂ , . . . , D _1N as shown in (c) of FIG. 7 . Therefore, the length of each of the extent data Du, D ₁₂ , ..., D _1N is only 1/N of the length of the original data 0 ₁ . Then, the controller sequentially converts the segment data Du, D ₁₂ , . . . , D _1N into the scrambled data Jn, J ₁₂ , and J _1N having the minimum transmission power shown in (d) of FIG. 7 . (d) of 7. Next, processing for scrambling data controller then Ju, J _12, ..., K _u index random sequence of J _1N, K _12, ..., Κ 1Ν scrambling data are added to the _{J u, J 12, ...,} J 1N The back end finally adds the check code obtained by the error correction coding to the back end of the index K _N1 of the scrambled data J _1N to obtain the error correction code d' as shown in (e) of FIG. Since the length of each segment data D _u , D ₁₂ , ..., D _1N is only 1/N of the length of the original data 0, and the random sequence in FIG. 2

The data lengths of M ₂ , - , M _N and the scrambling data S ₂ , - , S _N also correspondingly become 1/N, so the controller is required to store the random sequences M ₂ , ..., M _N and the scrambling data S The length (storage) of the buffers of ₂ , ..., S _N , thus becomes 1/N, thereby reducing the hardware cost of the controller including the multiple buffers. Please note that in another embodiment, the scrambling operation and the error correction code encoding need to be performed in parallel to save operating time. Detailed description is as follows, when the index of Figure 2 Additional modules 216 attached to the index K _u scrambling data J "after error correction code encoder 218 for an index for the immediately encoded and K _n J _u scrambling data to generate an error check code containing Pu correcting codes C". While the error correction code encoder 218 generates the error correction code Cu, the scramblers 201, 202, ..., 20N need to be scrambled for the sector data D ₁₂ , and then selected by the transmission power calculation module 212 and the selector 214 to have a minimum. The transmission power is disturbed by the data J ₁₂ . Similarly, while the error correction code encoder 218 generates the error correction code C ₁₂ , the scramblers 201, 202, ..., 20N need to be scrambled for the sector data D ₁₃ and then selected by the transmission power calculation module 212 and the selector 214. The disturbance data J ₁₃ with the smallest transmission power is output. By performing the scrambling operation and the error correction code encoding on each segment data in parallel, the operation time can be greatly saved, and the overall performance can be enhanced.

 While the preferred embodiments of the present invention have been described hereinabove, it is not intended to limit the invention, and various modifications and alternatives may be made without departing from the spirit and scope of the invention. The scope of protection of the invention is defined by the scope of the claims.

Claims

Rights request A data storage device comprising:  a memory for storing data;  a controller, when receiving a first raw data for writing to the memory from a host, generating at least one first input data according to the first original data, respectively scrambling the first input according to a plurality of random sequences Data, to obtain a plurality of first scrambling data, calculate a plurality of transmission powers of the plurality of first scrambled data, and select one of the plurality of first scrambled data from the plurality of first scrambled data according to the plurality of transmission powers The data is optimally disturbed for storage in the memory.  2. The data storage device of claim 1, wherein the controller appends an index of a random sequence corresponding to the best scrambled data to the optimal scrambled data to obtain a first output data, The output data is encoded as a first error correction code, and the first error correction code is transmitted to the memory for storage.  3. The data storage device according to claim 1, wherein the controller comprises: a plurality of scramblers respectively scrambling the first input data according to the plurality of random sequences to obtain the plurality of first disturbances Data  a transmission power calculation module, calculating the plurality of transmission powers of the plurality of first scrambling data, determining a minimum transmission power from the plurality of transmission powers, and outputting a random sequence corresponding to the minimum transmission power Index; and  a selector for selecting the best scrambled data having the minimum transmission power from the plurality of first scrambled data according to the cable.  4. The data storage device of claim 3, wherein the plurality of scramblers respectively perform XOR operations on the plurality of random sequences and the first input data to obtain the plurality of first scrambled data.  5. The data storage device of claim 3, wherein the controller further comprises: an index attaching module, appending the index corresponding to the random sequence of the best scrambled data to the best scrambled data To obtain a first output data; An error correction code encoder, encoding the first output data into a first error correction code, For output to the memory.  6. The data storage device of claim 3, wherein the transmission power calculation module comprises:  a plurality of delay units respectively delaying the plurality of first scrambling data to obtain a plurality of delay data; and a plurality of XOR units respectively XORing the plurality of delay data and the corresponding plurality of first scrambled data Computing to obtain multiple transition data;  And a plurality of counters respectively accumulating the number of times of converting the data to obtain the plurality of transmission powers. 7. The data storage device of claim 1, wherein the controller divides the first raw data into a plurality of segment data as the plurality of first input data.  8. The data storage device of claim 7, wherein the controller concurrently pairs the plurality of segments when the controller scrambles one of the plurality of segment data An output data corresponding to another segment data in the data is subjected to error correction code encoding.  9. The data storage device of claim 1, wherein when the controller receives a read command from the host, the controller instructs the memory to read a second error correction code for output to The controller converts the second error correction code into a second output data, and extracts a second index and a second scrambling data from the second output data, according to the second index from the plurality of The random sequence selects a descrambling random sequence, and the second scrambled data is descrambled according to the descrambled random sequence to restore a second original data, and the second original data is output to the host.  10. The data storage device according to claim 9, wherein the controller further comprises: an error correction code decoder, converting the second error correction code to the second output data; an index separation module, Extracting, by the second output data, the second index and the second scrambling data;  a selector that selects the descrambling random sequence from the plurality of random sequences according to the second index;  A descrambler distracts the second scrambled data according to the descrambled random sequence to restore the second original data. 11. The data storage device of claim 10, wherein the descrambler pairs the solution The scrambling random sequence is XORed with the second scrambled data to obtain the second original data.  12. The data storage device of claim 1, wherein the memory is a flash memory. 13. A method of data access, comprising:  Receiving, from a host, a first raw data for writing to a memory;  Generating at least one first input data according to the first raw data;  Dissipating the first input data according to a plurality of random sequences to obtain a plurality of first scrambled data;  Calculating a plurality of transmission powers of the plurality of first scrambled data;  And selecting, according to the plurality of transmission powers, an optimal scrambled data having a minimum transmission power from the plurality of first scrambled data for storage in the memory.  14. The data access method according to claim 13, wherein the method further comprises: appending an index of a random sequence corresponding to the optimal scrambled data to the optimal scrambled data to obtain a first output data. ;  Encoding the output data as a first error correction code;  The first error correction code is transmitted to the memory for storage.  15. The data access method of claim 13, wherein the step of disturbing the first input data comprises performing an XOR operation on the plurality of random sequences and the first input data, respectively, to obtain the plurality of The first disturbs the data.  16. The data access method of claim 13, wherein the calculating the plurality of transmission powers comprises:  Delaying the plurality of first scrambling data respectively to obtain a plurality of delay data;  Performing XOR operations on the plurality of delay data and the corresponding plurality of first scrambled data, respectively, to obtain a plurality of transition data;  The number of times of converting the data is separately accumulated to obtain the plurality of transmission powers.  17. The data access method according to claim 13, wherein the at least one first input data is a plurality of first input data, and the generating step of the plurality of first input data comprises: Dividing the first raw data into a plurality of segment data as the plurality of first input numbers According to.  18. The data access method of claim 17, further comprising:  And performing error correction code encoding on an output data corresponding to another segment data of the plurality of segment data in parallel when the segment data of the plurality of segment data is scrambled.  19. The data access method of claim 13, further comprising:  When receiving a read command from the host, instructing the memory to read a second error correction code;  Converting the second error correction code to a second output data;  Extracting a second index and a second scrambled data from the second output data;  Selecting, according to the second index, a descrambling random sequence from the plurality of random sequences; and de-scrambling the second scrambled data according to the descrambling random sequence to restore a second original data;  The second raw data is output to the host.  20. The data access method of claim 19, wherein the descrambling step of the second scrambled data comprises XORing the descrambled random sequence and the second scrambled data to obtain the Two raw data.  21. The data access method of claim 13, wherein the memory is a flash memory.