[go: up one dir, main page]

WO2011076259A1 - Structure de lignes de transmission à prises, table d'essais et de mesure, équipement d'essai automatisé et procédé pour la fourniture de signaux à une pluralité de dispositifs - Google Patents

Structure de lignes de transmission à prises, table d'essais et de mesure, équipement d'essai automatisé et procédé pour la fourniture de signaux à une pluralité de dispositifs Download PDF

Info

Publication number
WO2011076259A1
WO2011076259A1 PCT/EP2009/067780 EP2009067780W WO2011076259A1 WO 2011076259 A1 WO2011076259 A1 WO 2011076259A1 EP 2009067780 W EP2009067780 W EP 2009067780W WO 2011076259 A1 WO2011076259 A1 WO 2011076259A1
Authority
WO
WIPO (PCT)
Prior art keywords
transmission line
branching
test
main transmission
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2009/067780
Other languages
English (en)
Inventor
Jose Antonio Alves Moreira
Bernhard Roth
Marc Moessinger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Verigy Singapore Pte Ltd
Original Assignee
Verigy Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Verigy Singapore Pte Ltd filed Critical Verigy Singapore Pte Ltd
Priority to PCT/EP2009/067780 priority Critical patent/WO2011076259A1/fr
Priority to TW099144937A priority patent/TW201142864A/zh
Publication of WO2011076259A1 publication Critical patent/WO2011076259A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31723—Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56016—Apparatus features
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test

Definitions

  • Embodiments of the invention are related to a tapped transmission line structure for providing an electrical connection between a driver terminal and a plurality of device connections.
  • Other embodiment according to the invention is related to a test board for coupling a plurality of devices-under-test with an automated test equipment.
  • Further embodiments according to the invention are related to an automated test equipment.
  • Yet further embodiments according to the invention are related to methods for providing signals to a plurality of devices.
  • Another embodiment is related to a method to improve the signal integrity of testing multiple high-speed double-data-rate (DDR) memory integrated circuits (IC's) using a tapped transmission line approach.
  • DDR double-data-rate
  • SSTL stub-series terminated logic
  • Fig. 13 shows a schematic representation of an application, in which multiple DRAMs are coupled to a common memory controller.
  • an application 1300 typically comprises a memory controller 1310 and a plurality of dynamic-random-access- memory devices (also briefly designated as DRAMs) 1320a, 1320b, 1320c. Signals are provided from the memory controller 1310 to the dynamic random access memory devices 1320a, 1320b, 1320c, like, for example, an address signal "ADDRESS_0". Said address signal may be routed from the memory controller 1310 to a first branching point 1340a via a first transmission line portion 1330a.
  • DRAMs dynamic-random-access- memory devices
  • An address input of the first dynamic random access memory device 1320a may be coupled to the first branching point 1340a via an appropriate electrical connection.
  • a second transmission line portion 1330b typically connects the first branching point 1340a with a second branching point 1340b.
  • An address input of the second dynamic random access memory device 1320b may be connected with the second branching point 1340b via an appropriate electrical connection.
  • an address input of the third dynamic random access memory device 1320c may be coupled with the second branching point 1340b via a third transmission line portion 1330c, and possibly an additional electrical path.
  • the transmission line is terminated by a termination resistor R t connected to a termination voltage V t .
  • the type of data bus (or address bus) design shown in Fig. 13 can have significant signal integrity issues for high-data rates (for example above 2 gigabit per second) and/or when there is a large number of integrated circuits that hang on the data bus or address bus (for example 8 integrated circuits instead of 4 integrated circuits).
  • Fig. 13 the technology described with reference to Fig. 13 has been successful in the current generation of dual-inline-memory-module (DIMM) designs (for example according to the standard DDR3), and in the context of production test of double-data-rate memories (DDR memories) it has been leveraged as a way to test multiple double-date-rate integrated circuits using a smaller number of automated test equipment channels, as will be discussed taking reference to Fig. 14.
  • DIMM dual-inline-memory-module
  • Figs. 14a and 14b show block schematic diagrams of circuit arrangements for production testing of dynamic random access memories (DRAMs).
  • Fig. 14a shows a block schematic diagram of a simple arrangement for a production testing of DRAMs according to a first option.
  • separate automated-test-equipment channels 1410a, 1410b, 1410c can be used to provide separate signals (for example "ADDRESS_0") for the individual dynamic random access memory devices 1420a, 1420b, 1420c, which act as devices- under-test ("dutl", "dut2", “dut3").
  • the concept shown in Fig. 14a is very resource-inefficient and requires a high number of costly automated-test-equipment channels 1410a, 1410b, 1410c.
  • Fig. 14b shows a block schematic diagram of an arrangement for a more resource-efficient production testing of dynamic random access memories, according to a second option.
  • a common automated-test-equipment channel 1460 is used to provide a signal (for example "ADDRESS_0") to a plurality of dynamic random access memories 1470a, 1470b, 1470c.
  • the common automated-test-equipment channel 1460 is connected to inputs of the dynamic random access memory devices 1470a, 1470b, 1470c (or, more generally, to inputs of a plurality of devices-under-test) via a common signal transmission structure.
  • Fig. 15 shows a schematic diagram with an automated-test-equipment configured for testing a plurality of devices-under-test (in the following also designated as "duts").
  • an automated-test- equipment driver 1510 is connected to a driver terminal 1522 of a tapped transmission line 1520 having a plurality of transmission line segments 1520a, 1520b, 1520c, 1520d with branching points 1524a, 1524b, 1524c in between adjacent transmission line segments.
  • An end 1526 of the transmission line 1520 is terminated, i. e. connected to a termination voltage V t via a termination resistor R te rm.
  • the first branching point 1524a is coupled to a dut input 1540a of a first dut 1542a via an electrically conducting structure, which may comprise a via 1530a.
  • a dut input 1540b of a second dut 1542b is coupled with the second branching point 1524b via an electrically conducting structure 1530b.
  • a dut input 1540c of a third device-under-test 1542c is coupled with the third branching point 1524c via an electrically conducting structure 1530c.
  • An electrical behavior of the dut inputs 1540a, 1540b, 1540c of the duts 1542a, 1542b, 1542c may be modeled, for example, using a series connection of an inductance, a resistance and a capacitance, thereby describing an inductance of any connections (for example package pads, bond wires and so on), an unavoidable parasitic series resistance and an input capacitance of input transistors.
  • the challenge with a tapped transmission line approach for double-data-rate testing is that multiple device pins (for example inputs 1540a, 1540b, 1540c) are connected to a single automated test equipment (ATE) driver 1510, and that each device- under-test input 1540a, 1540b, 1540c is not terminated (or not terminated with an appropriate impedance to avoid reflections), so that there is no amplitude reduction (or only a limited amplitude reduction). This in turn creates several reflections that travel across the entire signal path until they are absorbed by the automated test equipment driver 1510 or the termination R ter m at the end 1526 of the signal path 1520a, 1520b, 1520c, 1520d.
  • ATE automated test equipment
  • An embodiment according to the invention creates a tapped transmission line structure for providing an electrical connection between a driver terminal and a plurality of device connections.
  • the tapped transmission line structure comprises a main transmission line and a plurality of branching structures coupling the main transmission line with the device connections at different distances from the driver terminal.
  • the branching structures have associated therewith respective signal transmission portions. Different of the signal transmission portions are designed to have different signal transmission characteristics in order to counteract differences of signal characteristics at different device connections.
  • a signal integrity for example a signal uniformity across multiple device connections
  • a signal integrity can be improved by providing a plurality of different signal transmission portions, each associated with one of the branching structures.
  • differences of signal characteristics for example rise times, or eye-openings
  • differences of signal characteristics which conventionally appear at device inputs of devices connected to a tapped transmission line at different distances from the driver terminal of the tapped transmission line, are reduced by the differences of the signal transmission portions associated with the different branching structures.
  • the different signal transmission portions associated with the different branching structures may, for example, be configured to at least partially compensate for a degradation of rise times of signals traveling along the main transmission line, thereby resulting in more uniform signals at inputs of different devices coupled to the main transmission line.
  • the different signal transmission portions associated with the different branching structures may, for example, be configured to at least partially compensate for a degradation of an eye opening of a data signal at a remote device connection when compared to an eye opening at a closer device connection (wherein it is assumed that the remote device connection is electrically further away from the driver terminal than the closer device connection).
  • the inventive concept improves the signal degradation in a tapped transmission line approach to test multiple DDR memory duts with a reduced number of channels.
  • the inventive concept generally allows to connect multiple devices to a common driver.
  • the inventive concept allows to test multiple devices, for example, double data rate memory devices, with a reduced number of channels.
  • the inventive approach allows to test devices at higher data rate when compared to a conventional approach.
  • the inventive concept improves the correlation of signals at different DUT connections.
  • the signal at all DUT's is (at least approximately) the same, i.e. having some DUT's receiving a good performance signal and some a bad performance signal is not acceptable for production testing. All DUT's need to receive (at least approximately) the same signal quality even if that means degrading the signal for some of the DUT's.
  • the different characteristics of the signal transmission portions contribute to obtaining a balance between the signal characteristics at different dut connections, thereby counteracting differences of signal characteristics at different device connections.
  • test board for coupling a plurality of devices-under-test with an automated test equipment.
  • the test board comprises a plurality of device-under-test sockets for contacting the devices-under-test.
  • the test board also comprises a tapped transmission line structure as discussed above.
  • the tapped transmission line structure is configured to forward a signal from the automated test equipment (or an automated test-equipment interface) to a plurality of the device-under- test sockets.
  • test board coupling a plurality of devices-under-test with an automated test equipment.
  • the test board comprises a plurality of devices-under-test and a tapped transmission line structure as discussed above.
  • the branching structures of the tapped transmission line structure are configured to couple inputs of a plurality of the devices-under-test to the main transmission line.
  • a signal transmission portion of a first branching structure is configured to form a first low pass filter with an input capacitance of an input of a first device-under-test, which is coupled to the main transmission line via the first branching structure.
  • a signal transmission portion of a second branching structure is configured to form a second low pass filter with an input capacitance of an input of a second device-under-test, which is coupled to the main transmission line via the second branching structure.
  • the time constant of the first low pass filter is larger than the time constant of the second low pass filter, and a first branching point, at which the first branching structure branches from the main transmission line, is closer to the driver terminal than a second branching point, at which the second branching structure branches from the main transmission line.
  • the discussed test board allows to exploit the input capacitances of the devices-under-test such that the complexity of the branching structure can be kept low. Also, by using a first low pass filter having a higher time constant in the proximity of the driver terminal and a second low pass filter having a smaller time constant at a larger distance from the driver terminal, the degrading impact of the main transmission line and the branching structures on the signal integrity (causing a variation of signal characteristics across the devices) can be compensated at least partially. In other words, the different time constants of the low pass filters counteract differences of the signal characteristics at different device connections, which would occur in the absence of filters having different time constants or in the presence of identical filters.
  • Another embodiment according to the invention creates an automated test equipment comprising a test board, as discussed before.
  • the automated test equipment is configured to test in parallel a plurality of devices-under-test attached to the test board.
  • the automated test equipment is configured to apply a test signal to the tapped transmission line structure having a bit rate of larger than 1 gigabit per second.
  • the advantages of the inventive tapped transmission line structure bring along a significant improvement of the signal integrity, because the inventive concept is particularly efficient for high bit rates and fast rise times.
  • Another embodiment according to the invention creates a method for providing signals to a plurality of devices using a common main transmission line, to which devices are coupled via a plurality of branching structures.
  • the method comprises forwarding a signal from a driver terminal to a first of the devices via the main transmission line and a first branching structure coupling the first device to the main transmission line.
  • the method also comprises forwarding the signal from the driver terminal to a second of the devices via the main transmission line and a second branching structure coupling the second device to the main transmission line.
  • the signal When being forwarded, the signal is shaped by a first signal transmission portion associated with the first branching structure and by a second signal transmission portion associated with the second branching structure, such that the signal shaping by the first signal transmission portion and by the second signal transmission portion counteracts differences of signal characteristics at different device connections.
  • Fig. 1 shows a schematic representation of a tapped transmission line structure, according to a first embodiment of the invention
  • 5 c show schematic representations of structural elements for the implementation the signal transmission portions; shows a schematic representation of a tapped transmission line structure, according to a sixth embodiment of the invention; shows a schematic representation of a tapped transmission line structure, according to a seventh embodiment of the invention; shows a graphical representation of eye-diagrams of signals at different device connections in the absence of signal shaping resistors; shows a graphical representation of eye-diagrams of signals at different device connections in the presence of signal shaping resistors; shows a schematic cross-sectional view of a test arrangement, according to an embodiment of the invention; shows a three-dimensional view of a test board and an interposer board, according to an embodiment of the invention;
  • Fig. 12 shows a graphical representation of eye-diagrams at different signal connections in the absence of a interposer and in the presence of an interposer
  • Fig. 13 shows a schematic representation of a topology for connecting dynamic random access memories to a memory controller
  • Fig. 14 shows a schematic representation of different approaches for a production testing of dynamic random access memories
  • Fig. 15 shows a schematic representation of a transmission line structure for connecting devices to a driver
  • Fig. 16 shows a schematic representation of a Y-shaped tapped transmission line structure, according to an embodiment of the invention.
  • Fig. 1 shows a schematic representation of a tapped transmission line structure 100, according to a first embodiment of the invention.
  • the tapped transmission line structure 100 is configured for providing an electrical connection between a driver terminal 110 and a plurality of device connections 120a, 120b.
  • the tapped transmission line structure comprises a main transmission line 130 and a plurality of branching structures 140a, 140b coupling the main transmission line 130 with the device connections 120a, 120b at different distances 1 1; 1 2 from the driver terminal 110.
  • the branching structures 140a, 140b have associated therewith signal transmission portions.
  • the first branching structure 140a has associated therewith a signal transmission portion 142a and/or a signal transmission portion 144a.
  • the second branching structure 140b has associated therewith a signal transmission portion 142b and/or a signal transmission portion 144b.
  • the one or more signal transmission portions 142a, 144a associated with the first branching structure 140a may be part of the first branching structure 140a, or may be adjacent to the first branching structure 140a.
  • the signal transmission portion 142a is part of the branching structure 140a.
  • the signal transmission portion 144a is arranged in an environment of a branching point, at which the branching structure 140a branches from the main transmission line 130.
  • the presence of one of the signal transmission portions 142a, 144a associated with the first branching structure 140a is sufficient. Nevertheless, both signal transmission portions may be present simultaneously in an embodiment.
  • one or more signal transmission portions 142b, 144b are associated with the second branching structure 140b.
  • the signal transmission portion 142b may be part of the branching structure 140b.
  • the signal transmission portion 144b may be arranged in an environment of a branching point, at which the second branching structure 140b branches from the main transmission line 130.
  • different signal transmission portions 142a, 144a, 142b, 144b are designed to have different signal transmission characteristics in order to counteract differences of signal characteristics at different device connections 120a, 120b.
  • the signal transmission portion 142a associated with the first branching structure 140a may comprise different signal transmission characteristics when compared to the signal transmission portion 142b, which is associated with the second branching structure 140b.
  • the signal transmission portions 144a, 144b, which are associated with the first branching structure 140a and the second branching structure 140b may optionally comprise different transmission characteristics (if the signal transmission portions 144a, 144b are present).
  • the signals arriving at the second device connection 120b are also degraded by signal reflections occurring, for example, at the first device connection 120a. Accordingly, it can be said that the signal characteristics (for example a steepness of the edges, or an eye-opening) would be significantly worse for a signal arriving at the second device connection 120b when compared to signals arriving at the first device connection 120a.
  • different branching structures 140a, 140b comprise, as the signal transmission portions 142a, 142b (or as a part of the signal transmission portions), resistors of different resistances circuited in series between the main transmission line 130 and the device connections 120a, 120b.
  • resistors of different resistances circuited in series between the main transmission line 130 and the device connections 120a, 120b.
  • a series resistor of a signal transmission portion 142a of the first branching structure 140a which branches from the main transmission line 130 at a first branching point, comprises a larger resistance (for example by at least 10% larger, or even by at least 30% larger, or even by 100% larger) than a series resistor of the signal transmission structure 142b of a second branching structure 140b, which branches from the main transmission line 130 at a second branching point, wherein the second branching point is electrically spaced further away from the driver terminal 110 than the first branching point.
  • the tapped transmission line structure further comprises a high pass filter arranged between the driver terminal 110 and a first branching point, at which the first branching structure 140a (when seen from the driver terminal 110) branches from the main transmission line 130.
  • the high pass filter is preferably configured to at least partially compensate for an effect of the one or more low pass filters.
  • the effect of the low pass filter in the first branching structure 140a can be partially compensated, such that a degradation of an edge steepness caused by the low pass filter of the first branching structure 140a is at least partially compensated. Accordingly, steep edges can be observed at the first device connection 120a even in the presence of a low pass filter (circuited into the first branching structure 140a).
  • the high pass filter is an equalization-type high pass filter configured to reduce a rise time of a signal.
  • the signal transmission portions 144a, 144b associated with the branching structures 140a, 140b comprise portions of the main transmission line 130 arranged adjacent to (or in an environment of) branching points, at which the branching structures 140a, 140b branch from the main transmission line 130.
  • the portions of the main transmission line comprise an increased impedance when compared to the rest of the main transmission line.
  • the signal transmission portions 142a, 142b associated with the branching structures comprise vias extending from the transmission line to another layer of a multi-layer circuit board, and pads in an electrical contact with the vias, thereby forming capacitances.
  • the desired low pass characteristic of the branching structures 140a, 140b can be obtained, wherein the low pass filter time constant of the different branching structures 140a, 140b may be chosen differently, such that the branching structure 140a, which is closer to the driver terminal 110, comprises a longer low pass filter time constant than the branching structure 140b, which is further away from the driver terminal 110.
  • Fig. 2a shows a schematic representation of a test board 200 for coupling a plurality of devices-under-test with an automated test equipment.
  • the test board 200 comprises a plurality of device-under-test sockets 210a, 210b for contacting the devices-under-test.
  • the test board 200 also comprises a tapped transmission line structure 100, as discussed above.
  • the tapped transmission line structure is configured to forward a signal from the automated test equipment (received, for example, at the driver terminal 110) to a plurality of the device-under-test sockets 210a, 210b.
  • Fig. 2b shows a schematic representation of a test board 250 for coupling a plurality of devices-under-test 260a, 260b with an automated test equipment.
  • Test board 250 comprises the devices-under-test 260a, 260b.
  • the test board also comprises a tapped transmission line structure 100, as discussed above.
  • the branching structures 140a, 140b of the tapped transmission line structure are configured to couple inputs 262a, 262b of a plurality of the devices-under-test 260a, 260b to the main transmission line 130.
  • a signal transmission portion 142a of the first branching structure 140a is configured to form a first low pass filter with an input capacitance of the input 262a of the first device-under-test 260a, which first device-under-test is coupled to the main transmission line 130 via the first branching structure 140a.
  • a signal transmission portion 142b of the second branching structure 140b is configured to form a second low pass filter with an input capacitance of the input 262b of a second device-under-test 260b, which second device-under-test is coupled to the main transmission line 130 via the second branching structure 140b.
  • a time constant of the first low pass filter is larger than a time constant of the second low pass filter, wherein a first branching point, at which the first branching structure 140a branches from the main transmission line 130, is closer to the driver terminal 110 than a second branching point, at which the second branching structure 140b branches from the main transmission line 130.
  • the input capacitances of the devices-under-test 260a, 260b are exploited for the implementation of different signal transmission characteristics to counteract differences of signal characteristics (e. g. rise times or eye-openings) at device connections (or inputs 262a, 262b) of the different devices-under-test 260a, 260b.
  • signal characteristics e. g. rise times or eye-openings
  • inputs of one or more of the devices-under-test are coupled to the main transmission line 130 via one or more branching structures (e.g. the branching structure 140a) branching from the main transmission line 130 comparatively closer to the driver terminal 110.
  • inputs of one or more of the devices-under-test are coupled to the main transmission line 130 via one or more branching structures (e.g. the branching structure 140b) branching from the main transmission line 130 comparatively further away from the driver terminal 110.
  • the one or more branching structures 140a branching from the main transmission line comparatively closer to the driver terminal 1 10 comprise a series resistance larger than 20 Ohm
  • the one or more branching structures 140b branching from the main transmission line 130 comparatively further away from the driver terminal 110 comprise a series resistance smaller than 4 Ohm.
  • the significant difference of the series resistances of the branching structures helps to counteract differences of the signal characteristics at different device connections. It has been found, that for devices being coupled to the main transmission line 130 comparatively closer to the driver terminal 110, it is important to reduce reflections and to slow down the rise time.
  • the devices-under-test 260a, 260b are double-data-rate memory devices, wherein double-data-rate inputs are coupled to the transmission line structure 100.
  • Fig. 3 shows a schematic representation of an automated test equipment, according to an embodiment of the invention.
  • the automated test equipment 300 comprises an automated test equipment channel 310 and a test board 320.
  • the test board 320 may be identical to the test board 200 described with reference to Fig. 2a or the test board 250 described with reference to Fig. 2b.
  • An output driver 312 of the automated test equipment 210 may, for example, be coupled with the driver terminal 110 of the main transmission line 130 via a so-called "POGO PIN" connection 316.
  • POGO PIN so-called "POGO PIN" connection
  • the automated test equipment 300 is preferably configured to test in parallel a plurality of devices-under-test attached to test board 320. Also, the automated test equipment is preferably (but not necessarily) configured to apply a test signal to the tapped transmission line structure 100 having a bit rate of larger than one gigabit per second. Accordingly, the automated test equipment 300 as a whole is capable of a reliable parallel testing of a plurality of devices-under-test even at high bit rates.
  • a tapped transmission line structure 400 will be described taking reference to Fig. 4.
  • the tapped transmission line structure 400 is based on the transmission line structure 1500 shown in Fig. 15.
  • the tapped transmission line structure 400 shown in Fig. 4 comprises a main transmission line 430, which comprises a plurality of main transmission line segments 430a, 430b, 430c, 430d.
  • a first main transmission line segment 430a is circuited between a driver terminal 432 of the tapped transmission line structure and a first branching point (or branching node) 434a.
  • a branching structure 436a branches from the main transmission line 430, wherein the main transmission line 430 continues from the first branching point 434a via a second main transmission line segment 430b.
  • the branching structure 436a which couples a device input 442a of a first device 440a with the branching point 434a, comprises a filter 450 and, optionally, a via 452.
  • the filter 450 and the optional via 452 are circuited in series between the branching point 434a and the device input 442a.
  • An additional branching point 434b is arranged further downstream the main transmission line 430, for example between a third main transmission line segment 430c and an (optional) fourth transmission line segment 430d.
  • the second branching point 434b is coupled to an input 442b of a second device 440b using a second branching structure 436b.
  • the second branching structure 436b comprises a filter 460 and, optionally, a via 462.
  • the filter 460 and the optional via 462 are circuited in series between the branching point 434b and the input 442b of the device 440b.
  • the main transmission line 430 may be terminated.
  • an end 433 of the main transmission line 430 may be coupled to a termination potential V t using a termination resistor R.
  • the tapped transmission line structure may optionally comprise an equalization filter 470, which may be circuited between the driver terminal 430 and the first branching point 444a.
  • the equalization filter 470 may also be part of a driver driving the tapped transmission line structure.
  • the filter 450, 460 and the functionality thereof may be described.
  • the filter 450 which is included in the first branching structure 436a, is preferably a low pass filter. Accordingly, a frequency transmission in response is typically monotonically decaying with increasing frequency, such that the filter 450 comprises a low insertion attenuation for low frequencies and an increasing insertion attenuation for increasing frequencies.
  • the filter 460 is preferably a low pass filter comprising an insertion loss that increases with frequency.
  • the filter 450 of the first branching structure 436a typically comprises a longer low pass filter time constant (or smaller cutoff frequency) than the low pass filter 460 of the second branching structure 436b.
  • a low pass filter time constant is defined as a delay time after which an output of the low pass filter reaches a predetermined percentage (e. g. 50 % or 63 %) of an input signal value for a step signal applied at the filter input.
  • a threshold frequency e. g.
  • the high pass filter 470 further contributes to an improvement of signal characteristics of signals arriving at the device inputs 442a, 442b.
  • the filter 470 may comprise a high pass characteristic, such that a predetermined range of higher frequencies is emphasized over a range of lower frequencies.
  • the filter 470 may comprise an approximately constant amplitude transmission.
  • the amplitude response of the filter 470 may decay. Accordingly, the filter 470 may be considered as an equalization-type high pass filter, which is configured to reduce rise times of signal transitions.
  • Some of those techniques are to change the thickness of the signal trace (for example of the main transmission line 430) before the via (e. g. before the via 452, or before the via 462) to the device (or device-under-test) 440a, 440b to either add inductance or capacitance, to add copper pads on the via 452, 462 to add capacitance, or to add a series resistor to the via 452,462 by using an embedded passive on the printed circuit board.
  • Fig. 5a shows a schematic representation of a first technique for implementing a filter, for example the filter 450 or the filter 460.
  • the first segment 430a of the main transmission line 430 may comprise a width Wo.
  • a second segment 430b of the main transmission line 430 may comprise the same width Wo.
  • the width of the main transmission line 430 may be reduced to a width W narr over a length l narr .
  • This reduction of the width of the main transmission line 430 in the environment of the branching point 434a may effectively act as a series inductance circuited between the first main transmission line segment 430a and the branching point 434a, and also as a series inductance circuited between the branching point 434a and the second main transmission line segment 430b.
  • another narrowed portion of the main transmission line may be arranged in an environment 512 of the second branching point 434b, if desired.
  • Another technique to implement the filters 450, 460 is to add a pad to one or more to the vias 452, 462, which brings along an additional capacitance.
  • a copper pad 540 which is electrically coupled to the via 452, may be added.
  • the via 452, or at least a portion thereof may be electrically in between the pad 540 and the main transmission line 430.
  • the via 452 (or the portion of the via 452) may act as an inductance, which is circuited between the main transmission line 430 and the capacitance constituted by the pad 540.
  • the combination of the via 452 and the pad 540 may act as a low pass filter structure (also designated as a "signal transmission portion" herein).
  • FIG. 5c A further technique to implement the filters 450, 460 is shown in Fig. 5c.
  • the branching point 434a is connected to the device input 442a using a via 452, which via is considered to establish a "vertical" connection through one or more printed circuit board layers, approximately perpendicular to a plane, in which the main transmission line extends.
  • the via 452 comprises a resistor (or dedicated resistor) 570.
  • a resistance of the resistor 570 may be chosen such that the specific resistance (per unit length) of the resistor 570 is at least by a factor of 10 larger than a specific resistance of a normal low-resistance via material.
  • a resistance of the resistor 570 is larger than 5 Ohms, or even larger than 10 Ohms, which is significantly higher than a "normal" resistance of a "good” via.
  • the resistor 570 may act, in combination with an additional capacitance (e. g. as shown in Fig. 5b, or implemented by the input capacitance of a device), as a low pass filter.
  • Figs. 5a, 5b and 5c can be combined in order to implement the filters 450, 460. However, in other embodiments a single one of the concepts shown in Figs. 5 a, 5b and 5c may be sufficient to implement the different signal transmission portions discussed above. Also, in some cases, different of the concepts of Figs. 5a, 5b and 5c may be applied for different signal transmission portions associated with different branching structures (or different devices). Also, in some embodiments completely different concepts may be used to implement the signal transmission portions associated with the branching structures.
  • Fig. 6 shows a schematic representation of a tapped transmission line structure 600, according to a sixth embodiment of the invention.
  • the optional filter 470 which has been described with reference to Fig. 4, can be omitted.
  • the vias 452, 462, which have been described with reference to Fig. 4 can be omitted in some cases.
  • the filter 450 can be replaced by a low pass filter 650
  • the filter 460 can be replaced by a low pass filter 660.
  • the low pass filter 650 is circuited between the branching point 434a and the device input 442a of the first device 440a.
  • the low pass filter 660 is circuited between the branching point 434b and the device input 442b of the second device 440b.
  • the structure of Fig. 6 addresses the finding that in the case of a tapped transmission line structure to test multiple double-data-rate memories, the challenge is that the first (one or more) devices under test after the automated test equipment driver 431 (for example the first dut 440a) will (conventionally) see a much faster rise-time than the devices under test at the end 433 (or in the proximity of the end 433) of the tapped transmission line 430 (for example the dut 440b).
  • testing conditions e.g. signal characteristics
  • a frequency response of the first low pass filter 650 is shown in a graphical representation at reference numeral 652, and a frequency response of the second low pass filter 660 as shown in a graphical representation at reference numeral 662.
  • An abscissa 652a describes a frequency
  • an ordinate 652b describes an amplitude response.
  • an abscissa 662a describes the frequency and an ordinate 662b describes the amplitude response.
  • Curves 652c, 662c describe the evolution of the amplitude responses over the frequency for the filters 650, 660.
  • the second low pass filter 660 is configured to have a higher bandwidth than the first low pass filter 650.
  • the amplitude response of the first low pass filter 650 decays faster with frequency than the amplitude response to the second filter 660.
  • tapped transmission line structure 700 of Fig. 7 is very similar to the tapped transmission line structure 600 of Fig. 7, identical reference numerals are used to designate identical features.
  • the tapped transmission line structure 600 comprises a main transmission line 430, which comprises a plurality of main transmission line segments 430a-430d.
  • a resistor Ri and a via 750 are circuited in series between the branching point 434a and an input (or a device connection) 442a of (or for) a first device 440.
  • a resistor R réelle and a via 760 are circuited in series between the branching point 434b and an input (or device connection) 442b of (or for) a device 440b.
  • the input 442a of the device 440a can be modeled, at least approximately, by a series connection of an inductance Lout, a resistance Rout and an input capacitance Cout-
  • the tapped transmission line structure 700 optionally comprises a high-pass filter 770, which is connected between a driver terminal 432 of the tapped transmission line structure 700 and the branching node 434a.
  • the high pass filter 770 may optionally be part of the automated test equipment driver 431 driving the tapped transmission line structure.
  • the optional high-pass filter 770 may, for example, comprise a T-structure.
  • a first high-pass filter resistor 772 is circuited between an input 780 of the high-pass filter and a central node 782 of the high-pass filter.
  • a second high-pass filter resistor 774 is circuited between the central node 782 and an output 784 of the high-pass filter.
  • a third high-pass filter resistor 776 and a high-pass filter inductor 778 are circuited in series between the central node 782 and a reference potential connection GND.
  • a high-pass-filter bypass capacitor 779 is circuited between the high-pass filter input 780 and the high-pass filter output 784.
  • the high-pass filter 770 may attenuate DC signals and low-frequency signals having frequencies for which the high-pass filter capacitor 779 comprises an impedance, which is larger than the resistance R of the high-pass filter resistors 772, 774, 776.
  • the high-pass filter 770 may pass high frequencies, for example, frequencies, for which the impedance of the high-pass filter capacitor 779 is smaller than the resistance R of the high-pass filter resistors 772, 774, 776.
  • the high-pass filter 770 may be configured to emphasize edges or transitions over steady signals, thereby reducing a rise-time of the filtered signal, which is forwarded via the man transmission line 430.
  • the R,L,C values of the filter may be chosen so that the impedance of the high-pass filter is equal or similar to the impedance of the main transmission line.
  • Fig. 7 One approach to implement the low-pass behavior, which has been discussed with reference to Fig. 6, is to use an embedded resistor (for example the resistors Rj to RN) before the via (for example vias 750, 760) to each device-under-test (for example devices 440a, 440b), wherein each resistor value (for example values Ri to R ) is different depending on the device-under-test position along the tapped transmission line to generate the required time constant for the low-pass filter.
  • an embedded resistor for example the resistors Rj to RN
  • each device-under-test for example devices 440a, 440b
  • this resistor for example of the resistors Ri to RN
  • the input capacitance for example Cout
  • the resistor value e.g. Ri to RN
  • the performance can be further improved by adding the equalization-type high-pass filter 770 after the automated test equipment driver 431 , so that a faster rise-time is available at the last devices-under-test (e.g. device 440b and possibly adjacent devices) of the tapped transmission line without adverse consequences to the first devices-under-test (for example device 440a and possibly adjacent devices) because of the low-pass behavior of the R/C circuit (comprising, for example, the resistor Rj and the input capacitance Cout of the device 440a) at the initial (close to the driver terminal 432) devices-under-test. Details regarding this arrangement have been shown in Fig. 7. Performance discussion with reference to Figs. 8 and 9
  • Fig. 8 shows a graphical representation of simulation results for the circuit setup of Fig. 7 with eight devices-under-test, where each device-under-test is assumed to have an input capacitance of 1.3 pF and a resistance of 5 ⁇ and an inductance of 0.5 nH. Also, for the simulations, the results, which are shown in Fig. 8, the socket (which connects the dut 440a, 440b with the test board or the via 750,760) is assumed to have an inductance of 1 nH. Also, it was assumed that no high-pass filter 770 was used after the automated test equipment driver 431. All transmission lines have a 50 Ohm impedance.
  • DUT5 0 ⁇
  • DUT6 0 ⁇
  • DUT7 0 ⁇
  • DUT8 0 ⁇ .
  • DUT1 is the device, which is electrically closest to the driver terminal 432, and that the device DUT8 is electrically furthest away from the driver terminal 432.
  • the branching point 434a at which a branching structure coupling the input 442a of the first DUT 440a (DUT1) branches from the main transmission line, is closer to the driver terminal 432 than the branching point 434b, at which the branching structure coupling the input 442b of the DUT 440b (DUT8) branches from the main transmission line.
  • Fig. 8 shows a graphical representation of eye diagrams, which represent the signals at the device connections 442a, 442b of eight devices-under-test DUT1 to DUT8.
  • Fig. 8 shows the data eye at each device-under-test (for DUT1 to DUT8) and the rise times if no resistor was added (i.e. if resistors Ri to R N were omitted).
  • Fig. 9 shows a graphical representation of the data eyes at each DUT with the added resistors (as discussed above). Also, Fig. 9 shows results for the rise-times.
  • Fig. 8 which shows the data eye in the absence of the resistors Ri to R
  • the eye opening is significantly larger for the first device-under-test DUT1 (which is closest to the driver terminal) than for the last device-under-test DUT8 (which is electrically farthest away from the driver terminal).
  • the rise-time varies significantly, by a factor of more than 2, between the first device DUT1 (97 picoseconds) and the last device DUT8 (199 picoseconds).
  • the data eye openings are significantly more uniform across the devices DUT1 to DUT8.
  • the rise-times are significantly more uniform.
  • a variation of the rise-times is reduced to a range between 146 picoseconds (for DUT1) and 206 picoseconds (for DUT8).
  • the implementation of the inventive concept to add resistors of different values into the branching structures coupling inputs of the devices with the main transmission line, brings along a significant improvement in uniformity of the signals present at the inputs of the devices. It allows testing a plurality of devices in parallel, because meaningful and reliable testing results can only be obtained if the signals at the different devices to be tested comprise similar characteristics. Also, as the rise-times at the first one or more devices (electrically closest to the driver terminal) are increased, reflections are reduced and the signal integrity, in particular for the more remote devices, is increased. As can be seen in Fig. 9, the data eye at the DUT8 is more "smooth" in the presence of said resistors Ri, R N when compared to the situation in the absence of the resistors Ri, .. . , RN, which is shown in Fig. 8.
  • Fig. 8 shows the data eye at each device-under-test in the rise-times if no resistor was added
  • Fig. 9 represents the results with the added resistors.
  • the results of Fig. 9 show a smaller variation in the rise-time (across the devices) and a better data eye correlation across the eight devices-under-test.
  • Fig. 10 shows a cross-sectional view of a tapped transmission line structure, according to an embodiment of the invention.
  • the tapped transmission line structure 1000 shown in Fig. 10 comprises a main printed-circuit-board (pcb) 1010.
  • a main transmission line 430 comprising a plurality of transmission line segments 430a, 430b, 430c, 430d is embedded on an inner or outer layer of the main printed circuit board 1010.
  • the main transmission line 430 may be implemented as a strip line or micro strip line, which is embedded between two or more layers of the main printed circuit board 1010.
  • the main print circuit board 1010 comprises a plurality of vias 750, 760, which typically extend from the main transmission line 430 to a main surface 1011 of the main printed circuit board 1010.
  • the vias typically extend approximately perpendicularly to the main surface 1011 of the main printed circuit board 1010, thereby establishing an electrical coupling between the main transmission line 430 and pads 1050, 1060 on the main surface of the main print circuit board 1010.
  • a plurality of vias branch from the main transmission line 430 at different distances from a driver terminal 432 of the main transmission line 430.
  • another via 1070 extends between the driver terminal 432 of the main transmission line 430 and a driver pad 1072 arranged on a second main surface 1012 of the main printed circuit board 1010.
  • An automated testing equipment channel 431 may be connected to the driver pad 1072, for example via a so-called "POGO ASSEMBLY" cable.
  • An interposer (or interposer printed-circuit-board) 1080 is arranged on the first main surface 1011 of the main printed circuit board 1010, such that the interposer 1080 neighbors the first main surface 1011 of the main printed circuit board 1010 in an environment of the pad 1050.
  • a device-under-test socket 1090 is stacked onto the interposer 1080, such that the interposer 1080 is sandwiched by the device-under-test socket 1090 and the main printed circuit 1010.
  • Interposer 1080 comprises an embedded resistor 1082, which extends "vertically", i.e.
  • the embedded resistor 1082 is configured to establish an electrical connection between the pad 1050 and an electrical connection 1092 of the DUT socket 1090. Accordingly, the arrangement is configured such that an electrical connection is established between the main transmission line 430 and a device connection 1096 of a device 1094, if the device 1094 is inserted into the DUT socket 1090.
  • the electrical connection between the main transmission line 430 and the DUT connection 1096 may be established via the via 750, the pad 1050, the embedded resistor 1082 and the DUT socket connection 1092. Accordingly, the via 750 and the embedded resistor 1082 may be considered as a signal transmission portion in the sense of the present application.
  • DUT sockets (not shown in Fig. 10), which are coupled to the main transmission line 430 close to the end 433 of the main transmission line 430 (for example via the via 760 and the tap 1060), may see a smaller series resistance circuited between the DUT socket and the corresponding branching point of the main transmission line than DUT sockets (e.g. the DUT socket 1090) coupled to the main transmission line close to the driver terminal 432.
  • a DUT socket is arranged from the driver terminal 432, the smaller is the resistance of the embedded resistor in the corresponding interposer.
  • one or more of the dut sockets which are coupled to the main transmission line 430 close to the end 433 of the main transmission line 430, may be coupled to the main transmission line without an interposer, or using an interposer without an embedded resistor.
  • Fig. 11 shows a three-dimensional representation of the main printed circuit board 1010 and the interposer 1080, which interposer is not yet attached to the main printed circuit board.
  • a contact pattern 1120 of the interposer 1080 is at least approximately identical to a contact pattern 1110 of the main printed circuit board 1010.
  • the interposer 1080 is configured to vertically route through signals from a pad 1050 on the first main surface 101 lof the main printed circuit board 1010 to the device socket 1090 to be attached to the top surface of the interposer 1080.
  • the resistor 1082 may be involved, which resistor 1082 is embedded in the interposer 1080, as discussed with reference to Fig. 10.
  • the interposer is embedded on the PCB socket board.
  • the top layer for example of the PCB socket board
  • the resistor integrated there is designed to serve the same functionality as the interposer described above by having the resistor integrated there. This would save the need to use the separate interposer but would require a more complex manufacturing process on the socket board.
  • the technique to introduce different resistors into the branching structures branching from the main transmission line has been implemented on a real prototype using a Verigy pin electronics board that already includes a high-pass type active equalization filter in the pin electronics (for example in the automated test equipment driver 431).
  • the needed resistor (for example the resistor R] shown in Fig. 7) was implemented on an interposer type printed circuit board 1080, which is arranged (in operation) between the printed circuit board socket board that connects to the automated test equipment system (for example the main printed circuit board 1010) and the device under test socket 1090, as shown in Fig. 10.
  • This resistor R can be implemented as an embedded passive component 1082 in a very thin interposer 1080 for a maximum signal integrity, as shown in Fig. 11.
  • the interposer board is commercially available. Measured Results in the presence of an interposer layer
  • Fig. 12 shows a graphical representation of measured results for an eight device-under-test tapped transmission line where a single 33 ⁇ resistor was set on the DUTl position.
  • Fig. 12 shows, in a first graphical representation 1210, a data eye at the DUTl position, which is obtained without using an interposer, and, in a graphical representation 1220, a data eye at the DUT8 position obtained without using an interposer.
  • Fig. 12 shows, in a graphical representation 1230, a data eye at the DUTl position obtained in the presence of an interposer, and, in a graphical representation 1240, a data eye at the DUT8 position obtained in the presence of the interposer.
  • the data eye is significantly different at the DUTl position and at the DUT8 position in the absence of an interposer.
  • a difference of the eye openings is 85 picoseconds in the absence of an interposer.
  • the graphical representations 1230 and 1240 show that the eye openings at the DUTl position and the DUT8 position are more similar in the presence of an interposer (which is arranged at the DUTl position).
  • a difference of the eye openings is only 29 picoseconds in this case. Accordingly, it can be clearly seen from Fig. 12 that the usage of the interposer improves the signal correlation at different DUT positions.
  • Fig. 12 shows the measured results for an eight device-under-test tapped transmission line, where a single 33 ⁇ resistor was set on the DUTl position. A significant improvement is seen on the rise time correlation between DUTl and DUT8. Even though the results shown in Fig. 12 already demonstrate significant improvements, it should be noted that the techniques shown in Fig. 5 can be further used to tune each of the filters to the best response, including the optimization of the termination resistor at the end of the tapped transmission line. Accordingly, even better results can be obtained in some embodiments.
  • the inventive concept can also be applied for a tapped transmission line structure, as will be explained taking reference to Fig. 16, which shows a schematic representation of such a tapped transmission line structure 1600.
  • the tapped transmission line 1600 comprises a first main transmission line 430, and a second main transmission line 1630, both branching from a common line portion 1620 at a Y branching-point 1622.
  • the first main transmission line 430 and the branching structures coupled therewith may comprise any of the features and functionalities discussed above.
  • identical reference numerals are used to designate identical means in the embodiment of Fig 16, as discussed above.
  • the second main transmission 1630 line may for example be symmetrical with respect to the first main transmission line 430, having portions 1630a, 1630b, 1630c.
  • branching structures comprising low pass filter structures 1650, 1660 may branch from the main transmission line 1630 at branching points 1634a, 1634b.
  • the Y-shaped transmission line constitutes an additional topology. This topology has been verified, and it could be seen that it also provides significant improvements.
  • the topology has a "Y-sharing tapped transmission line".
  • a disadvantage of this topology is the fact that there is a signal amplitude loss from the Y-sharing circuit. Nevertheless, since each branch has a smaller number of duts (e.g.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

La présente invention concerne une structure de lignes de transmission à prises (1) pour la fourniture de connexion électrique entre un terminal pilote (110) et une pluralité de connexions de dispositifs (120a, 120b) comportant une ligne de transmission principale (130) et une pluralité de structures de branchement (142a, 142b). Les structures de branchement relient la ligne de transmission principale (130) aux connexions de dispositifs à des distances différentes (I1, I2) depuis le terminal pilote (110) et comprennent en association des parties de transmission de signaux. Différentes parties parmi les parties de transmission sont agencées pour avoir des caractéristiques différentes de transmission de signaux afin de contrecarrer les différences de caractéristiques de signaux au niveau des différentes connexions de dispositifs.
PCT/EP2009/067780 2009-12-22 2009-12-22 Structure de lignes de transmission à prises, table d'essais et de mesure, équipement d'essai automatisé et procédé pour la fourniture de signaux à une pluralité de dispositifs Ceased WO2011076259A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/EP2009/067780 WO2011076259A1 (fr) 2009-12-22 2009-12-22 Structure de lignes de transmission à prises, table d'essais et de mesure, équipement d'essai automatisé et procédé pour la fourniture de signaux à une pluralité de dispositifs
TW099144937A TW201142864A (en) 2009-12-22 2010-12-21 Tapped transmission line structure, test board, automated test equipment and method for providing signals to a plurality of devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2009/067780 WO2011076259A1 (fr) 2009-12-22 2009-12-22 Structure de lignes de transmission à prises, table d'essais et de mesure, équipement d'essai automatisé et procédé pour la fourniture de signaux à une pluralité de dispositifs

Publications (1)

Publication Number Publication Date
WO2011076259A1 true WO2011076259A1 (fr) 2011-06-30

Family

ID=41800717

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2009/067780 Ceased WO2011076259A1 (fr) 2009-12-22 2009-12-22 Structure de lignes de transmission à prises, table d'essais et de mesure, équipement d'essai automatisé et procédé pour la fourniture de signaux à une pluralité de dispositifs

Country Status (2)

Country Link
TW (1) TW201142864A (fr)
WO (1) WO2011076259A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190123595A (ko) * 2018-04-24 2019-11-01 삼성전자주식회사 인터포저 장치 및 그것을 포함하는 반도체 테스트 시스템
WO2020040852A1 (fr) * 2018-08-23 2020-02-27 Raytheon Company Sélecteur d'entrée/sortie mécanique
EP3955250A1 (fr) * 2020-08-10 2022-02-16 Samsung Electronics Co., Ltd. Dispositifs de stockage et procédés de fonctionnement de dispositifs de stockage
WO2025130117A1 (fr) * 2023-12-22 2025-06-26 华为技术有限公司 Procédé de transmission de signal, dispositif associé et support de stockage

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI506536B (zh) 2013-01-10 2015-11-01 Accton Technology Corp 執行裝置及其堆疊方法與堆疊系統
US10914757B2 (en) * 2019-02-07 2021-02-09 Teradyne, Inc. Connection module
CN113917311A (zh) * 2021-09-14 2022-01-11 中国电子技术标准化研究院 一种芯片参数容限测试方法和装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6366972B1 (en) * 1996-07-23 2002-04-02 Compaq Computer Corporation Multi-user communication bus with a resistive star configuration termination
US20030126338A1 (en) * 2001-12-31 2003-07-03 Dodd James M. Memory bus termination with memory unit having termination control
US20040230880A1 (en) * 2003-05-12 2004-11-18 Kingston Technology Corp. Memory-Module Burn-In System With Removable Pattern-Generator Boards Separated from Heat Chamber by Backplane
US20070150635A1 (en) * 1997-09-26 2007-06-28 Haw-Jyh Liaw Memory System Having Memory Devices on Two Sides
US20070247935A1 (en) * 2001-04-24 2007-10-25 Ware Frederick A Clocked Memory System with Termination Component

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6366972B1 (en) * 1996-07-23 2002-04-02 Compaq Computer Corporation Multi-user communication bus with a resistive star configuration termination
US20070150635A1 (en) * 1997-09-26 2007-06-28 Haw-Jyh Liaw Memory System Having Memory Devices on Two Sides
US20070247935A1 (en) * 2001-04-24 2007-10-25 Ware Frederick A Clocked Memory System with Termination Component
US20030126338A1 (en) * 2001-12-31 2003-07-03 Dodd James M. Memory bus termination with memory unit having termination control
US20040230880A1 (en) * 2003-05-12 2004-11-18 Kingston Technology Corp. Memory-Module Burn-In System With Removable Pattern-Generator Boards Separated from Heat Chamber by Backplane

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190123595A (ko) * 2018-04-24 2019-11-01 삼성전자주식회사 인터포저 장치 및 그것을 포함하는 반도체 테스트 시스템
KR102574570B1 (ko) * 2018-04-24 2023-09-06 삼성전자주식회사 인터포저 장치 및 그것을 포함하는 반도체 테스트 시스템
WO2020040852A1 (fr) * 2018-08-23 2020-02-27 Raytheon Company Sélecteur d'entrée/sortie mécanique
US10955802B2 (en) 2018-08-23 2021-03-23 Raytheon Company Mechanical input/output selector
EP3955250A1 (fr) * 2020-08-10 2022-02-16 Samsung Electronics Co., Ltd. Dispositifs de stockage et procédés de fonctionnement de dispositifs de stockage
US11825596B2 (en) 2020-08-10 2023-11-21 Samsung Electronics Co., Ltd. Storage devices and methods of operating storage devices
WO2025130117A1 (fr) * 2023-12-22 2025-06-26 华为技术有限公司 Procédé de transmission de signal, dispositif associé et support de stockage

Also Published As

Publication number Publication date
TW201142864A (en) 2011-12-01

Similar Documents

Publication Publication Date Title
WO2011076259A1 (fr) Structure de lignes de transmission à prises, table d'essais et de mesure, équipement d'essai automatisé et procédé pour la fourniture de signaux à une pluralité de dispositifs
US7035116B2 (en) Memory system and memory subsystem
US8933718B2 (en) Signal distribution structure and method for distributing a signal
US7203460B2 (en) Automated test of receiver sensitivity and receiver jitter tolerance of an integrated circuit
US20140239994A1 (en) Concept for Extracting a Signal Being Exchanged Between a Device Under Test and an Automatic Test Equipment
JP5582248B2 (ja) 伝送システムとバックプレーンシステム構築方法
US20120194304A1 (en) Equalizer Circuit and Printed Circuit Board
WO2011142079A1 (fr) Ligne de transmission de signaux différentiels, boîtier de circuit intégré, et procédé pour tester ladite ligne de transmission de signaux différentiels et ledit boîtier de circuit intégré
US6449166B1 (en) High capacity memory module with higher density and improved manufacturability
KR100913711B1 (ko) 인쇄 회로 보드
RS20050693A (sr) Metod za visoko-frekventno podešavanje električnog uređaja
US20060203830A1 (en) Semiconductor integrated circuit and test method for the same
US6496380B1 (en) High capacity memory module with high electrical design margins
JP5561428B2 (ja) 伝送システムとバックプレーンシステム構築方法
CN111683453B (zh) 电子总成
Zhang et al. Application of a new power distribution scheme for complex printed circuit boards for high-speed signaling
JP2012227617A (ja) 信号伝送回路
US9542305B2 (en) Impedance matching for high speed signaling in memory system
TW202222108A (zh) 連接電路板
CN219552455U (zh) 芯片输出信号在不同反射条件下的通用扩展测试板
TWI685282B (zh) 高速電路及低頻減少被動等化器
Shin et al. Small-size low-cost wideband continuous-time linear passive equalizer with an embedded cavity structure on a high-speed digital channel
Lee et al. Multi-slot main memory system for post DDR3
JP4522056B2 (ja) 整合のとれた応答を生じる４ドロップ・バス
JP2007324511A (ja) 差動インピーダンス整合プリント配線板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09803762

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09803762

Country of ref document: EP

Kind code of ref document: A1