时钟源选择的方法及数据通信设备 技术领域 本发明涉及通信领域， 具体地， 涉及一种时钟源选择的方法及数据通信 设备。 背景技术 同步串口以其简单可靠的传输特点在网络通信中得到了广泛的应用， 它 同时支持不同的物理电气标准 （如 V.24, V.35 , X.21 , RS449, RS530等）， 各种标准之间的差别在于数据信号、 时钟信号和控制信号釆用单端或者差分 传输形式， 不同的电气标准对应不同的连接线缆类型 （如 DB25 , DB37等）。 同步串口分为数据通信设备 （Data Communication Equipment, 简称为 TECHNICAL FIELD The present invention relates to the field of communications, and in particular, to a method for selecting a clock source and a data communication device. BACKGROUND OF THE INVENTION A synchronous serial port has been widely used in network communication because of its simple and reliable transmission characteristics. It also supports different physical and electrical standards (such as V.24, V.35, X.21, RS449, RS530, etc.), each The difference between the standards is that the data signal, clock signal and control signal are in single-ended or differential transmission. Different electrical standards correspond to different connection cable types (such as DB25, DB37, etc.). Synchronous serial port is divided into data communication equipment (Data Communication Equipment, referred to as
DCE ) 和数据终端设备 ( Data Terminal Equipment, 简称为 DTE ) 两种工作 方式， 从某种意义上讲是按照时钟源来划分的， DCE是时钟的主动方， 提供 线路的收发时钟， DTE是时钟的被动方， 依靠 DCE提供的时钟工作， 从而 达到同步传输的目的。 一般情况下系统设备（路由器等）根据组网方式既可 以作为 DCE设备也可以作为 DTE设备，作为 DCE设备时由内部产生的时钟 作为线路收发时钟， 作为 DTE设备时接受对端 DCE设备提供的时钟， 同时 系统设备可以通过三套片等电平和协议转换芯片自动检测同步串口外接线缆 的类型。 下面以单端信号标准为例说明业界系统设备同步串口通信中 DCE 和 DTE的通用时钟控制方案。 图 1是根据相关技术的同步串口 DCE设备和 DTE设备的时钟控制的示 意图。 如图 1所示， 作为 DCE设备时， 固定由晶振产生的时钟源作为 CPU的 发送时钟的时基 CPU_ETC1 ( ETC: External Transmit Clock ), 還辑内部是直 通的设计得到 LOG_ETCl , 同时为了满足标准要求逻辑内部会产生一个和 LOG ETC 1 同频同相位的时钟 LOG_TXCLKl (图中信号虚线的含义是指对 于 X.21标准是没有该信号的）， LOG ETC 1和 LOG_TXCLKl通过三套片转 换后得到 DCE_ETC和 DCE_TXCLK作为 DTE设备侧的时钟选择源； DCE
设备的接收时钟 DCE RXCLK由 DTE_ETC提供， 而 DTE_ETC的时钟源头 实际是 DCE TXCLK或者 DCE_ETC通过三套片和還辑处理后在 DTE侧的 CPU内部环回得到的 CPU_ETC2, 因此归才艮结底 DCE设备侧的发送和接收 时钟都是使用本地时钟。作为 DTE设备时， 其接收时钟和发送时钟是由线路 提供的 DCE_ETC和 DCE_TXCLK通过三套片和逻辑选择得到的， 由于同步 设备的接收和发送时钟是独立的，即 DTE设备的发送接收时钟可以选择 DCE 设备的发送或者接收时钟， 从而产生四种时钟选择组合， 至于选择哪一种组 合方式由设备内部的逻辑控制芯片 （如： CPLD ) 决定。 但是市场上存在一些不规范的 DTE设备 （如某些雷达装置、 POS 终端 等）， 其发送或者接收釆用的是本地产生的时钟， 从而造成和 DCE侧的收发 时钟不同步引起传输丢包、 CRC校验错误甚至无法 PING通的严重问题。 目 前市场上规避该问题的方法是制作特殊线序的连接线缆， 例如： 如果发现路 由器和收发均釆用本地时钟的 DTE设备互连，则需要临时订制特殊线序的发 货线缆， 即路由器虽然工作在 DCE侧， 但是线缆的线序需要调整成 DTE的 工作模式， 以便从线路上提取时钟进行收发保持同步。 这种处理方式的缺点 是对于不同电气标准的同步串口需要订制不同的线缆类型， 大大增加了产品 成本， 更重要的是在客户方出现通信异常的情况下通过更换特殊线缆来解决 会严重影响客户的满意度， 损坏公司形象。 针对相关技术中 DCE设备往往无法与一些不规范的 DTE设备进行正常 通信的问题， 目前尚未提出有效的解决方案。 发明内容 针对 DCE设备往往无法与一些不规范的 DTE设备进行正常通信的问题 而提出本发明， 为此， 本发明的主要目的在于提供一种时钟源选择的方法及 数据通信 DCE设备， 以解决上述问题至少之一。 为了实现上述目的， 根据本发明的一个方面， 提供了一种时钟源选择的 方法。 根据本发明的时钟源选择的方法， 用于数据通信设备 ( DCE ) 和数据终 端设备（ DTE )之间的通信， 其中， 在 DCE与 DTE不能正常通信的情况下， DCE对发送时钟和 /或接收时钟进行时钟切换。
优选地， DCE对发送时钟和 /或接收时钟进行时钟切换包括： DCE对发 送时钟和 /或接收时钟进行本地时钟和线路时钟之间的切换。 优选地， DCE 对发送时钟和 /或接收时钟进行本地时钟和线路时钟之间 的切换包括： DCE 的发送时钟切换至本地时钟， DCE 的接收时钟切换至线 路时钟。 优选地， DCE 对发送时钟和 /或接收时钟进行本地时钟和线路时钟之间 的切换包括： DCE的发送时钟和 DCE的接收时钟均切换至线路时钟。 优选地， DCE对发送时钟和 /或接收时钟进行时钟切换包括： DCE通过 配置时钟源选择寄存器来实现对发送时钟和 /或接收时钟的切换。 优选地， DCE接收和发送釆用不同的波特率。 优选地， 在 DCE初始上电时， DCE的发送时钟和接收时钟均釆用本地 时钟。 为了实现上述目的， 根据本发明的另一方面， 提供了一种数据通信设备 DCE。 根据本发明的数据通信设备包括： 判断模块， 判断与数据通信设备是否 能够正常通信； 时钟源选择模块，在与数据通信设备不能正常通信的情况下， 用于对发送时钟和 /或接收时钟进行时钟切换。 优选地，上述时钟源选择模块用于对发送时钟和 /或接收时钟进行本地时 钟和线路时钟之间的切换。 优选地， 上述时钟源选择模块包括时钟源选择寄存器。 通过本发明， 在 DCE设备与 DTE设备不能正常通信的情况下， DCE设 备对发送时钟和 /或接收时钟进行时钟切换， 解决了 DCE设备往往无法与一 些不规范的 DTE设备进行正常通信的问题， 进而达到了提高 DCE设备的可 靠性及兼容性的效果。 附图说明 此处所说明的附图用来提供对本发明的进一步理解， 构成本申请的一部 分， 本发明的示意性实施例及其说明用于解释本发明， 并不构成对本发明的
不当限定。 在附图中: 图 1是根据相关技术的同步串口 DCE设备和 DTE设备的时钟控制的示 意图； 图 2是才艮据本发明实施例的时钟源选择的方法的流程图； 图 3是根据本发明实施例的同步串口 DCE设备和 DTE设备的时钟控制 的示意图； 图 4是才艮据本发明实施例的优选的时钟源选择的方法的流程图； 图 5是根据本发明实施例的 DCE设备的示意图。 具体实施方式 考虑到 DCE设备往往无法与一些不规范的 DTE设备进行正常通信， 本 发明以下实施例提供了一种时钟源选择的方法及数据通信 DCE设备， 用于 DCE设备和 DTE设备之间的通信， 该方法包括： 在 DCE设备与 DTE设备 不能正常通信的情况下， DCE设备对发送时钟和 /或接收时钟进行时钟切换。 下文中将参考附图并结合实施例来详细说明本发明。 需要说明的是， 在 不冲突的情况下， 本申请中的实施例及实施例中的特征可以相互组合。 方法实施例 根据本发明的实施例， 提供了一种时钟源选择的方法。 图 2是根据本发明实施例的时钟源选择的方法的流程图。 如图 2所示， 该方法包括如下的步骤 S202至步骤 S204： 步骤 S202, DCE设备与 DTE设备不能正常通信； 步骤 S204, DCE设备对发送时钟和 /或接收时钟进行时钟切换。 下面将结合实例对本发明实施例的实现过程进行详细描述。 本发明的目的在于提供一种同步串口 DCE 工作模式下的时钟源选择方 法， 能够实现各种情况下的时钟选择和切换功能， 保证与 DTE设备的正常通
信。 表 1是根据本发明实施例的 DTE设备收发时钟组合方式的表格。 DCE) and Data Terminal Equipment (DTE) work in two ways. In a sense, they are divided according to the clock source. DCE is the active side of the clock, which provides the clock for sending and receiving, and the DTE is the clock. The passive side relies on the clock provided by DCE to achieve the purpose of synchronous transmission. In general, system devices (routers, etc.) can be used as both DCE devices and DTE devices according to the networking mode. When the DCE device is used as the DCE device, the clock is sent and received by the peer DCE device. At the same time, the system device can automatically detect the type of the external serial cable of the synchronous serial port through three sets of chip level and protocol conversion chips. The following is a single-ended signal standard as an example to illustrate the general clock control scheme of DCE and DTE in synchronous serial communication of industrial system equipment. 1 is a schematic diagram of clock control of a synchronous serial port DCE device and a DTE device according to the related art. As shown in Figure 1, when it is used as a DCE device, the clock source generated by the crystal oscillator is fixed as the time base CPU_ETC1 (ETC: External Transmit Clock) of the CPU's transmission clock, and the internal design of the pass-through is LOG_ETCl, and in order to meet the standard requirements. Inside the logic, a clock LOG_TXCLK1 with the same frequency as LOG ETC 1 is generated (the meaning of the dotted line in the figure means that there is no such signal for the X.21 standard), and LOG ETC 1 and LOG_TXCLKl are converted by DCE_ETC after three sets of slices. And DCE_TXCLK as the clock selection source on the DTE device side; DCE The receiving clock of the device DCE RXCLK is provided by DTE_ETC, and the clock source of DTE_ETC is actually the CPU_ETC2 obtained by DCE TXCLK or DCE_ETC through the three sets of chips and the internal loopback of the CPU on the DTE side, so the DCE device is finally obtained. Both the transmit and receive clocks on the side use the local clock. As a DTE device, its receive clock and transmit clock are obtained by the DCE_ETC and DCE_TXCLK provided by the line through three sets of chips and logic selection. Since the receive and transmit clocks of the synchronous device are independent, the transmit and receive clocks of the DTE device can be selected. The DCE device sends or receives a clock to generate four combinations of clock selections. Which combination is selected by the logic control chip (such as CPLD) inside the device. However, there are some non-standard DTE devices on the market (such as some radar devices, POS terminals, etc.), which transmit or receive a locally generated clock, which causes the transmission and reception of clocks on the DCE side to be asynchronous. The CRC checksum error is not even a serious problem with PING通. The current way to circumvent this problem on the market is to make a special wire-sequence connection cable. For example: If the router and the transceiver are connected to the DTE device with the local clock, you need to temporarily order the special wire-sending delivery cable. That is, although the router works on the DCE side, the cable sequence needs to be adjusted to the DTE mode of operation, so that the clock is extracted from the line for transmission and reception to maintain synchronization. The disadvantage of this type of processing is that different types of cables need to be customized for the synchronous serial ports of different electrical standards, which greatly increases the product cost, and more importantly, solves the problem by replacing special cables when the communication side of the customer is abnormal. Seriously affect customer satisfaction and damage the company's image. In view of the problem that the DCE device in the related art often cannot communicate normally with some non-standard DTE devices, an effective solution has not been proposed yet. SUMMARY OF THE INVENTION The present invention has been made in view of the problem that a DCE device is often unable to communicate normally with some non-standard DTE devices. To this end, the main object of the present invention is to provide a clock source selection method and a data communication DCE device to solve the above problem. At least one of the problems. In order to achieve the above object, according to an aspect of the present invention, a method of clock source selection is provided. A method of clock source selection according to the present invention is used for communication between a data communication device (DCE) and a data terminal equipment (DTE), wherein, in the case where the DCE and the DTE are not in normal communication, the DCE pair transmits a clock and/or Receive clock for clock switching. Preferably, the DCE clocking the transmit clock and/or the receive clock includes: DCE switching between the local clock and the line clock on the transmit clock and/or the receive clock. Preferably, the switching between the local clock and the line clock by the DCE on the transmit clock and/or the receive clock includes: the transmit clock of the DCE is switched to the local clock, and the receive clock of the DCE is switched to the line clock. Preferably, the switching between the local clock and the line clock by the DCE on the transmit clock and/or the receive clock includes: switching the transmit clock of the DCE and the receive clock of the DCE to the line clock. Preferably, the DCE clocking the transmit clock and/or the receive clock includes: The DCE implements switching of the transmit clock and/or the receive clock by configuring a clock source select register. Preferably, the DCE receives and transmits different baud rates. Preferably, when the DCE is initially powered on, both the transmit clock and the receive clock of the DCE use the local clock. In order to achieve the above object, according to another aspect of the present invention, a data communication device DCE is provided. A data communication device according to the present invention includes: a determination module that determines whether the data communication device can communicate normally; and a clock source selection module that performs a transmission clock and/or a reception clock in a case where the data communication device cannot communicate normally Clock switching. Preferably, the clock source selection module is configured to switch between a local clock and a line clock for the transmit clock and/or the receive clock. Preferably, the clock source selection module includes a clock source selection register. With the present invention, in the case that the DCE device and the DTE device cannot communicate normally, the DCE device performs clock switching on the sending clock and/or the receiving clock, which solves the problem that the DCE device often cannot communicate normally with some non-standard DTE devices. In turn, the effect of improving the reliability and compatibility of the DCE device is achieved. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set to illustrate, illustrate, Improperly qualified. In the drawings: FIG. 1 is a schematic diagram of clock control of a synchronous serial port DCE device and a DTE device according to the related art; FIG. 2 is a flowchart of a method for clock source selection according to an embodiment of the present invention; FIG. FIG. 4 is a flowchart of a method for selecting a preferred clock source according to an embodiment of the present invention; FIG. 5 is a DCE device according to an embodiment of the present invention; FIG. 4 is a flowchart of a method for clock control of a synchronous serial port DCE device and a DTE device; Schematic diagram. The following embodiments provide a clock source selection method and a data communication DCE device, which are used between a DCE device and a DTE device, in view of the fact that the DCE device is often unable to communicate with some non-standard DTE devices. For communication, the method includes: in a case where the DCE device and the DTE device cannot communicate normally, the DCE device performs clock switching on the transmit clock and/or the receive clock. The invention will be described in detail below with reference to the drawings in conjunction with the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. Method Embodiments According to an embodiment of the present invention, a method of clock source selection is provided. 2 is a flow chart of a method of clock source selection in accordance with an embodiment of the present invention. As shown in FIG. 2, the method includes the following steps S202 to S204: Step S202: The DCE device and the DTE device cannot communicate normally; Step S204: The DCE device performs clock switching on the transmit clock and/or the receive clock. The implementation process of the embodiment of the present invention will be described in detail below with reference to examples. The object of the present invention is to provide a clock source selection method in a synchronous serial port DCE working mode, which can implement clock selection and switching functions in various situations, and ensure normal communication with DTE devices. Letter. Table 1 is a table of a DTE device transceiving clock combination manner according to an embodiment of the present invention.
表 1 由表 1可知由于线路上总有 DTE侧的 DTE_ETC时钟存在， 因此 DCE 设备的发送和接收时钟除了釆用本地时钟的通用模式外， 可以增加提取线路 时钟的工作模式。 这样的话共有四种 DCE时钟控制模式可供选择： 工作模式一， 发送时钟和接收时钟均釆用本地时钟 （默认方式）； 工作模式二， 发送时钟釆用本地时钟， 接收时钟釆用线路时钟； 工作模式三， 发送时钟和接收时钟均釆用线路时钟； 工作模式四， 发送时钟釆用线路时钟， 接收时钟釆用本地时钟。 结合图 1可以得出， 第 4种工作模式实际上是无法实现的（即 CPU发送 时钟 CPU ETC 1既然选择了线路时钟 DTE ETC,则接收时钟 CPU RXCLK1 也必须选择线路时钟， 否则会产生矛盾和冲突）， 在本发明中， 优选地， 釆用 前面三种控制方案。 图 3是根据本发明实施例的同步串口 DCE设备和 DTE设备的时钟控制 的示意图。 如图 3所示， 本发明在逻辑代码 （即逻辑模块） 中增加 DCE时钟源选 择功能模块， 保证 DCE的逻辑发送时钟 LOG_ETCl和 LOG_TXCLKl可以 在本地时钟 CPU ETC 1和线路时钟 LOG RXCLK1之间选择， 同理接收时钟
CPU RXCLKl也可以在本地时钟 CPU ETCl和线路时钟 LOG RXCLKl之 间选择， 上电后逻辑默认选择工作模式 1 (收发均选择本地时钟）， 与现有技 术方案保持一致，另外增加工作模式 2和工作模式 3 ,当遇到与不规范的 DTE 设备互通时， 只需要通过软件操作逻辑器件的相关控制寄存器进行工作模式 的切换即可。 在逻辑器件代码 ( CPLD VHDL代码）中增加可读可写的 DCE时钟源选 择寄存器 DCECLK_SEL, 使用 2个比特即可， "00"代表工作模式 1 (发送接 收均釆用本地时钟的默认方式）， "01" 代表工作模式 2 (发送时钟釆用本地 时钟， 接收时钟釆用线路时钟）， "10"代表工作模式 3 (发送时钟和接收时钟 均釆用线路时钟）， "11，，保留不用。 Table 1 It can be seen from Table 1 that since there is always a DTE_ETC clock on the DTE side of the line, the transmitting and receiving clocks of the DCE device can increase the working mode of extracting the line clock in addition to the common mode of the local clock. In this case, there are four DCE clock control modes to choose from: In operating mode 1, the transmit clock and the receive clock use the local clock (the default mode); the work mode 2, the transmit clock uses the local clock, and the receive clock uses the line clock; In operation mode 3, both the transmit clock and the receive clock use the line clock; in operation mode 4, the transmit clock uses the line clock, and the receive clock uses the local clock. In combination with Figure 1, it can be concluded that the fourth mode of operation is actually unachievable (ie, the CPU sends the clock CPU ETC 1 since the line clock DTE ETC is selected, the receive clock CPU RXCLK1 must also select the line clock, otherwise there will be conflicts and Collision) In the present invention, preferably, the first three control schemes are used. FIG. 3 is a schematic diagram of clock control of a synchronous serial port DCE device and a DTE device according to an embodiment of the present invention. As shown in FIG. 3, the present invention adds a DCE clock source selection function module in a logic code (ie, a logic module) to ensure that the logical transmission clocks LOG_ETCl and LOG_TXCLK1 of the DCE can be selected between the local clock CPU ETC 1 and the line clock LOG RXCLK1. Same receiving clock The CPU RXCLK1 can also be selected between the local clock CPU ETCl and the line clock LOG RXCLK1. After power-on, the logic selects the working mode 1 by default (the local clock is selected for sending and receiving), which is consistent with the prior art solution, and additionally increases the working mode 2 and the work. Mode 3, when encountering interoperability with an unregulated DTE device, it is only necessary to switch the operating mode through the relevant control register of the software operation logic device. Add the readable and writable DCE clock source selection register DCECLK_SEL in the logic device code (CPLD VHDL code), use 2 bits, "00" stands for working mode 1 (the default mode of sending and receiving the local clock) "01" stands for working mode 2 (send clock uses local clock, receive clock uses line clock), "10" stands for working mode 3 (both transmit clock and receive clock use line clock), "11,, reserved.
DCE设备上电默认 DCECLK SEL寄存器初始值为" 00", 发送和接收时 钟均釆用本地时钟 CPU ETC 1。 对于工作模式 2, 通过软件写 DCECLK_SEL寄存器为" 01", 工作模式 2 也实现了 DCE收发釆用不同波特率的功能。 对于工作模式 3 , 通过软件写 DCECLK_SEL寄存器为" 10" , , 此时可以 认为虽然是 DCE设备但是工作在 DTE时钟控制方式下。 在具体的组网互通测试中，如果发现 DTE设备侧的发送接收时钟未釆用 线路时钟而出现通信异常问题， 可以通过软件操作 DCE 侧设备 CPLD 的 DCECLK SEL 寄存器进行工作模式的切换， 由于逻辑中已经涵盖所有可能 出现的 DTE时钟情况， 因此能够完全兼容这些不规范的 DTE设备实现正常 通信。 图 4是根据本发明实施例的优选的时钟源选择的方法的流程图。 如图 4所示， 该方法包括以下步 4聚： 步骤 S401 , 在默认情况下， DCE设备发送时钟和接收时钟均釆用本地 时钟。 步骤 S402 , DCE设备与 DTE设备进行报文的收发。 步骤 S403 , 判断当前的 DTE设备是否是规范的 DTE设备。
步骤 S404 , 当前的 DTE设备是规范的 DTE设备， 则可以进行正常的通 信。 步骤 S405 , 若当前的设备不是规范的 DTE设备， 则往往无法进行正常 的通信， 此时， 配置寄存器至表 1中的工作模式 2。 步骤 S406, 判断 DCE设备与 DTE设备是否能够进行正常通信。 步 4聚 S407, 如果能够进行正常通信， 则流程结束。 步骤 S408, 如果仍然无法进行正常的通信， 此时， 配置寄存器至表 1中 的工作模式 3。 步骤 S409, DCE设备与 DTE设备能够进行正常通信。 对于传统同步串口通信， DCE 设备配置收 /发时钟的波特率， 如果与之 通信的是不规范的 DTE设备则通信失败， 必须通过特殊线缆来解决。 如图 4 所示， 本发明在 DCE设备侧增加了时钟源选择功能模块后， 则可以通过软 件配置 CPLD的时钟源选择寄存器使 DCE设备分别工作于上述的工作模式 2 和工作模式 3 , 由于这些工作模式已经涵盖所有可能出现的 DCE时钟控制情 况， 因此能够完全兼容这些不规范的 DTE设备实现正常通信。 装置实施例 根据本发明的实施例， 提供了一种数据通信设备 DCE。 图 5是根据本发明实施例的 DCE设备的示意图。 如图 5所示， 该 DCE设备包括： 判断模块 501和时钟源选择模块 503。 其中， 判断模块 501用于判断与 DTE设备是否能够正常通信； 时钟源选 择模块 503 , 在与 DTE设备不能正常通信的情况下， 用于对发送时钟和 /或接 收时钟进行时钟切换。 优选地， 时钟源选择模块 503用于对发送时钟和 /或接收时钟进行本地时 钟和线路时钟之间的切换。 优选地， 上述时钟源选择模块 503包括时钟源选择寄存器。 从以上的描述中， 可以看出， 本发明实现了如下技术效果：
与现有技术相比较， 本发明保留业界通用的 DCE 收发时钟釆用本地时 钟的方案前提下， 在 CPLD代码中利用组合逻辑增加两种时钟控制和切换方 案， 可以方便地通过软件配置实现工作模式的切换， 涵盖了 DCE 工作方式 下所有可能出现的收发时钟控制情况， 可以兼容市场上实际存在的不规范的 DTE设备保证与之正常通信， 避免订制特殊线缆带来的成本压力， 提高了产 品的兼容性、 可靠性， 使得客户满意。 需要说明的是， 在附图的流程图示出的步骤可以在诸如一组计算机可执 行指令的计算机系统中执行， 并且， 虽然在流程图中示出了逻辑顺序， 但是 在某些情况下， 可以以不同于此处的顺序执行所示出或描述的步骤。 显然， 本领域的技术人员应该明白， 上述的本发明的各模块或各步骤可 以用通用的计算装置来实现， 它们可以集中在单个的计算装置上， 或者分布 在多个计算装置所组成的网络上， 可选地， 它们可以用计算装置可执行的程 序代码来实现， 从而， 可以将它们存储在存储装置中由计算装置来执行， 或 者将它们分别制作成各个集成电路模块， 或者将它们中的多个模块或步骤制 作成单个集成电路模块来实现。 这样， 本发明不限制于任何特定的硬件和软 件结合。 以上所述仅为本发明的优选实施例而已， 并不用于限制本发明， 对于本 领域的技术人员来说， 本发明可以有各种更改和变化。 凡在本发明的 ^"神和 原则之内， 所作的任何修改、 等同替换、 改进等， 均应包含在本发明的保护 范围之内。
DCE device power-on default DCECLK SEL register initial value is "00", both the transmit and receive clocks use the local clock CPU ETC 1. For the working mode 2, the DCECLK_SEL register is written to "01" by software, and the working mode 2 also realizes the function of different baud rates for the DCE transceiver. For the working mode 3, the DCECLK_SEL register is written to "10" by software, and it can be considered that although it is a DCE device, it works in the DTE clock control mode. In the specific networking interworking test, if the communication abnormality problem occurs when the transmit/receive clock of the DTE device side is not used, the DCECLK SEL register of the DCE side device CPLD can be operated by software to switch the working mode. All possible DTE clock conditions have been covered, so it is fully compatible with these non-standard DTE devices for normal communication. 4 is a flow chart of a method of preferred clock source selection in accordance with an embodiment of the present invention. As shown in FIG. 4, the method includes the following steps: Step S401: By default, the DCE device sends a clock and a receiving clock to use the local clock. Step S402: The DCE device and the DTE device perform packet transmission and reception. Step S403, determining whether the current DTE device is a standard DTE device. Step S404: If the current DTE device is a standardized DTE device, normal communication can be performed. Step S405, if the current device is not a standard DTE device, normal communication cannot be performed. At this time, the configuration register is set to the working mode 2 in Table 1. Step S406, determining whether the DCE device and the DTE device can perform normal communication. Step 4 gathers S407, and if normal communication is possible, the flow ends. In step S408, if normal communication is still not possible, at this time, the configuration register is set to the operation mode 3 in Table 1. In step S409, the DCE device and the DTE device can perform normal communication. For traditional synchronous serial communication, the DCE device configures the baud rate of the incoming/outgoing clock. If it communicates with an unregulated DTE device, the communication fails and must be solved by a special cable. As shown in FIG. 4, after the clock source selection function module is added to the DCE device side, the clock source selection register of the CPLD can be configured by software to enable the DCE device to work in the above working mode 2 and working mode 3 respectively. The working mode already covers all possible DCE clock control situations, so it is fully compatible with these non-standard DTE devices for normal communication. Apparatus Embodiment In accordance with an embodiment of the present invention, a data communication device DCE is provided. FIG. 5 is a schematic diagram of a DCE device in accordance with an embodiment of the present invention. As shown in FIG. 5, the DCE device includes: a determining module 501 and a clock source selecting module 503. The determining module 501 is configured to determine whether the DTE device can communicate normally. The clock source selecting module 503 is configured to perform clock switching on the sending clock and/or the receiving clock if the DTE device cannot communicate normally. Preferably, the clock source selection module 503 is configured to switch between the local clock and the line clock for the transmit clock and/or the receive clock. Preferably, the clock source selection module 503 includes a clock source selection register. From the above description, it can be seen that the present invention achieves the following technical effects: Compared with the prior art, the present invention retains the industry-wide DCE transceiver clock and uses the local clock. In the CPLD code, the combination logic is used to add two clock control and switching schemes, and the working mode can be conveniently implemented through software configuration. The switch covers all possible transceiver clock control situations in the DCE working mode. It can be compatible with the normal DTE equipment in the market to ensure normal communication with it, avoiding the cost pressure of customizing special cables and improving the cost. Product compatibility, reliability, and customer satisfaction. It should be noted that the steps shown in the flowchart of the accompanying drawings may be performed in a computer system such as a set of computer executable instructions, and, although the logical order is shown in the flowchart, in some cases, The steps shown or described may be performed in an order different than that herein. Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device, or they may be separately fabricated into individual integrated circuit modules, or they may be Multiple modules or steps are made into a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the scope of the present invention are intended to be included within the scope of the present invention.