CN1533112A - Clock signal conversion circuit of V35 interface and time division multiplexing interface - Google Patents

Abstract

A clock signal transfer circuit of V35 interface and CDM interface includes a frequency division phase-locked locked loop, a V35 clock selection module, a frequency division unit and a frequency multiplication phase-locked loop, among which, the frequency division phase-locked loop inputs the V35 interface working clock signals phase-locked and frequency-divided by clock source and provided by the opposite device into the V35 clock selective module, the output signal of which is sent to the frequency division unit, the first signal from it is sent to the multiplied phase-locked loop to output a CDM interface working clock signal, and the second frequency division signal from the frequency division unit is the CDM interface synchronous positioning clock signal. The local device can use the clocks provided by the local clock source or opposite clock source.

Description

Clock signal conversion circuit of V35 interface and time division multiplexing interface

technical field

The invention relates to telecommunication access technology, in particular to a clock signal conversion circuit of a V35 interface and a time-division multiplexing interface.

Background technique

In telecommunication access equipment, the V35 interface is widely used as a general external interface technology. Inside the device, the communication between the V35 interface module and the service processing module usually uses a time division multiplexing (TDM) bus for communication. TDM is a 2.048M data flow, which is divided into 32 time slots, and each time slot corresponds to 64K data. V35 is a data stream of N*64K, N=(1-32), that is, 64K to 2.048M, corresponding to 1-32 time slots of TDM respectively. Therefore, it is necessary to convert the clock or data between the V35 interface and the TDM interface.

Referring to FIG. 1 , FIG. 1 is a schematic diagram of conversion between a V35 interface and a TDM interface in the prior art. When the TDM sends data to the V35 interface, the TDM writes the data into the sending dual-port random access device (DPRAM) 101 inside the Field Programmable Gate Array (FPGA) for buffering through the synchronous positioning clock 8K and the working clock 2.048M. Each cycle (8K) writes the data of several time slots. The V35 interface uses the working clock N*64K selected by the V35 clock selection module 103 to read the data from the sending DPRAM 101 , and send the data to the peer device after passing through the level conversion chip 106 . Contrary to sending, the V35 interface uses the N*64K of the working clock selected by the V35 clock selection module 103 to write the data sent by the peer device into the receiving DPRAM 102 . The TDM is read out from the receiving DPRAM 102 inside the FPGA by synchronizing the positioning clock 8K and the working clock 2.048M, and reads data of several time slots in each cycle.

In the figure, the clock conversion of the prior art is as follows: the 2.048M clock of the local device passes through the frequency-division phase-locked loop module 104 to generate N*64K clock, and sends it to the V35 clock selection module 103 . The V35 clock selection module selects the N*64K clock from the V35 interface or the N*64K clock generated by the PLL as the receiving clock of the DPRAM102 and the sending clock of the DPRAM101 according to the working mode of the single board. Among them, the clock from the V35 interface is actually the peer device directly returns the sending clock of the local device, and does not really use the clock source provided by the peer device. The 2.048M clock of the local device passes through the frequency division module 105 to generate an 8K synchronous positioning clock, which is used as the sending and receiving clock of the TDM interface.

Since all clocks converted by the V35 interface and the TDM interface must be generated by the same clock source, it is possible to ensure that the amount of data sent and received by TDM in each cycle is consistent with the amount of data sent and received by V35, thereby ensuring normal conversion. As can be seen from the above clock conversion, since the N*64K clock from the peer device cannot be converted into the TDM working clock 2.048M, the 2.048M clock of the TDM interface can only be supplied by the local device, and cannot be provided by the peer clock source. Therefore, only the clock source of the local device can be used, that is, it can only work in the data transmission equipment (DCE) mode.

Contents of the invention

The purpose of the present invention is to provide a clock signal conversion circuit of a V35 interface and a time-division multiplexing interface, so that the local device can use the clock provided by the clock source of the local device and the clock provided by the clock source of the opposite device.

The present invention is realized through the following technical solutions:

A clock signal conversion circuit for a V35 interface and a time-division multiplexing interface, comprising a frequency-division phase-locked loop 104 and a V35 clock selection module 103, wherein the frequency-division phase-locked loop 104 uses the phase-locked frequency division of the clock source from the local device The obtained V35 interface operating clock signal is input to the V35 clock selection module 103, and the clock signal conversion circuit also includes a frequency division unit 100 and a frequency multiplication phase-locked loop 108, and the V35 interface operating clock signal provided by the peer device is input to the V35 clock selection Module 103, the output signal of the V35 clock selection module 103 is sent to the frequency division unit 100, and the first frequency division signal output by the frequency division unit 100 is sent to the frequency multiplication phase-locked loop 108, and the frequency multiplication phase-locked loop 108 will The first frequency-division signal is multiplied and phase-locked to output a time-division multiplexing interface working clock signal, and the second frequency-dividing signal output by the frequency division unit 100 is a time-division multiplexing interface synchronous positioning clock signal.

Preferably, the frequency division unit 100 is a frequency division module 109, the frequency of the first frequency division signal output by it is the same as or different from that of the synchronous positioning clock signal of the time division multiplexing interface.

Preferably, the frequency division unit 100 further includes a first frequency division module 107 and a second frequency division module 105, wherein the first frequency division module 107 divides the signal from the V35 clock selection module 103 into the first frequency division The signal is input to the multiplier phase-locked loop 108; the second frequency division module 105 divides the output clock signal from the frequency multiplier phase-locked loop 108 into the synchronous positioning clock signal output by the time division multiplexing interface.

Preferably, the frequency division unit also includes a third frequency division module 110, the output clock signal from the frequency multiplication phase-locked loop 108 is input to the frequency division module, and the frequency division module outputs a frequency division signal and feeds it back to the frequency multiplier The phase-locked loop 108 , the frequency of the frequency-divided signal is the frequency required by the feedback signal of the multiplier phase-locked loop 108 .

Preferably, the frequency of the first frequency-divided signal is the frequency of a time-division multiplexing interface synchronous positioning clock signal. The frequency-divided signal output by the second frequency-dividing module 105 is fed back to the frequency multiplication phase-locked loop 108 .

The present invention divides the frequency of the V35 interface working clock into a fixed frequency division signal by adding a frequency division unit 100, and uses the fixed frequency division signal to perform frequency multiplication and phase locking through the frequency multiplication phase-locked loop 108 to obtain the TDM interface working clock. The 100 frequency division output of the frequency unit obtains the synchronous positioning clock of the TDM interface, which solves the problem of converting the V35 interface working clock from the peer device into the TDM working clock, so that the clock conversion circuit can use the clock provided by the clock source of the local device, The clock provided by the clock source of the peer device can also be used, so the local device can work in both DCE mode and data terminal equipment (DTE) mode, making the application of the access device using the V35 interface more flexible and convenient . The present invention makes a simple improvement on the basis of the existing clock circuit, and the cost is low.

Description of drawings

Fig. 1 is the conversion schematic diagram of V35 interface and TDM interface of prior art;

Fig. 2 is the V35 interface of the present invention and the TDM interface conversion circuit schematic diagram;

Fig. 3 is the V35 interface and TDM interface conversion circuit diagram of embodiment 1 of the present invention;

FIG. 4 is a schematic diagram of a conversion circuit between a V35 interface and a TDM interface in Embodiment 2 of the present invention.

Detailed ways

Since the existing clock conversion circuit cannot convert the clock from the peer device into the working clock of the TDM interface, in view of this defect, a frequency division module is added inside the FPGA to convert the V35 interface working clock N*64K provided by the peer device. Frequency division, and a frequency multiplication phase-locked loop is added outside the FPGA, so as to use the frequency division module to generate the working clock of the TDM interface.

Referring to Fig. 2, Fig. 2 is an overall schematic diagram of the conversion circuit between the V35 interface and the TDM interface of the present invention. The conversion process of the TDM interface and the V35 interface data is the same as the prior art process, all of which are converted through the DPRAM buffer, and the working clock of the TDM interface, the synchronous positioning clock and the working clock of the V35 interface are all sent to the DPRAM respectively. The acquisition of the above-mentioned clock signal is as follows: the V35 interface operating clock output from the frequency division phase-locked loop module 104, and the V35 interface operating clock provided by the peer device are respectively input to the V35 clock selection module 103; the V35 clock selection module 103 outputs The clock signal is sent to the frequency division unit 100 for frequency division, and the frequency division unit 100 inputs the output first frequency division signal to the frequency multiplication phase-locked loop 108, and the TDM working clock signal is generated by the frequency multiplication phase-locked loop 108 and output respectively ; and the frequency of the second frequency division signal output by the frequency division module is the frequency of the TDM synchronous positioning clock signal.

Example 1:

Referring to FIG. 3 , FIG. 3 is a schematic diagram of a conversion circuit between a V35 interface and a TDM interface according to Embodiment 1 of the present invention. The frequency division unit 100 is a frequency division module 109, and the frequency division module 109 can directly divide the frequency of the V35 interface working clock N*64K output from the V35 clock selection module 103 into a TDM synchronous positioning clock signal, that is, the output of the frequency division module 109 The frequency of the first frequency-division signal is the same as that of the second frequency-division signal, both of which are the frequency of the TDM synchronous positioning clock signal. After the frequency-multiplication phase-locked loop performs frequency-multiplication and phase-locking on the above-mentioned frequency-division signal, it generates a TDM interface working clock signal.

Certainly, the frequency of the first frequency division signal output by the frequency division module 109 may be different from the frequency of the second frequency division signal, as long as the frequency of the first frequency division signal is a submultiple of the working clock frequency of the time division multiplexing interface.

Example 2:

Referring to FIG. 4, FIG. 4 is a schematic diagram of a conversion circuit between a V35 interface and a TDM interface according to Embodiment 2 of the present invention. The frequency division unit 100 is a first frequency division module 107 and a second frequency division module 105, wherein the first frequency division module 107 divides the frequency of the signal from the V35 clock selection module 103 into the first frequency division signal input to the frequency multiplication phase lock Ring 108, in order to ensure that the synchronous positioning clock of the TDM interface is consistent with the same clock source and phase as the working clock, and avoid the jitter of the frequency division signal output by the first frequency division module 107, the TDM interface output by the frequency multiplication phase-locked loop module 108 The working clock is sent to the second frequency division module 105, and the second frequency division module 105 divides the frequency to output the second frequency division signal. The frequency of the frequency division signal is the synchronous positioning clock frequency, and is output to the DPRAM.

In order to make the frequency-multiplication phase-locked loop 108 lock phase more stable, a third frequency division module 110 can also be added to generate the feedback signal of the frequency-multiplication phase-locked loop 108. The clock signal output by 108 is frequency-divided, the frequency-divided output is fed back and input to the frequency multiplication phase-locked loop 108, and the frequency of the frequency-divided signal is specifically determined by the phase-locked loop. In addition, in order to make the frequency of the frequency division signal output by the frequency division module the same as possible, reduce the complexity of the FPGA circuit, preferably, the frequency of the first frequency division signal output by the first frequency division module 107 is the same as that of the second frequency division module. The frequency of the second frequency division signal output by 105 frequency division is the same, which is the frequency of the TDM synchronous positioning clock signal, and the output second frequency division signal of the second frequency division module 105 is fed back to the frequency multiplier phase-locked loop 108, as shown by the dotted line in Figure 4 As shown, the third frequency division module may not be needed at this time.

As can be seen from the foregoing embodiments, since the V35 interface operating clock from the V35 clock selection module 103 can be the clock generated by the clock source of the local device, it can also be the clock from the peer device, thereby realizing the clock conversion from the peer device The working clock of the TDM interface and the synchronous positioning clock can ensure that the clock source of the working clock of the TDM interface and the working clock of the V35 interface are the same.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention. For example, the first frequency division signal can be a frequency division signal of other frequencies, as long as the frequency division signal can be multiplied for TDM work. The clock will do.

Claims (6)

1, the conversion circuit of clock signal of a kind of V35 interface and time division multiplexing interface, comprise frequency dividing phase-locked loop (104), V35 clock selection module (103), wherein, the V35 interface work clock signal that frequency dividing phase-locked loop (104) will be obtained from the clock source phase-locked frequency demultiplication of local terminal equipment inputs to V35 clock selection module (103), the V35 interface work clock signal that provides from opposite equip. inputs to V35 clock selection module (103), it is characterized in that

This conversion circuit of clock signal also comprises frequency unit (100) and frequency multiplication phase-locked loop (108), the output signal of described V35 clock selection module (103) inputs to frequency unit (100), first fractional frequency signal of frequency unit (100) frequency division output inputs to frequency multiplication phase-locked loop (108), frequency multiplication phase-locked loop (108) output time division multiplexing interface work clock signal, second fractional frequency signal of frequency unit (100) output is a time division multiplexing interface synchronized positioning clock signal.

2, conversion circuit of clock signal according to claim 1 is characterized in that, described frequency unit (100) is a frequency division module (109).

3, conversion circuit of clock signal according to claim 1, it is characterized in that, described frequency unit (100) further comprises first frequency division module (107) and second frequency division module (105), wherein, first frequency division module (107) will be first fractional frequency signal from the output signal frequency division of V35 clock selection module (103), and input to frequency multiplication phase-locked loop (108); Second frequency division module (105) will be described time division multiplexing interface synchronized positioning clock signal output from the clock signal frequency division of frequency multiplication phase-locked loop (108).

According to claim 1 or 2 or 3 described conversion circuit of clock signal, it is characterized in that 4, the frequency of described first fractional frequency signal is a time division multiplexing interface synchronized positioning clock signal frequency.

5, conversion circuit of clock signal according to claim 3 is characterized in that, the fractional frequency signal of described second frequency division module (105) output also feeds back and inputs to described frequency multiplication phase-locked loop (108).

6, according to claim 1 or 2 or 3 described conversion circuit of clock signal, it is characterized in that, described frequency unit also comprises three frequency division module (110), clock signal from frequency multiplication phase-locked loop (108) inputs to this frequency division module, this frequency division module is exported fractional frequency signal feedback and is inputed to frequency multiplication phase-locked loop (108), and the frequency of this fractional frequency signal is the required frequency of frequency multiplication phase-locked loop (108) feedback control signal.

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