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WO2010116993A1 - Structure contenant un circuit intégré - Google Patents

Structure contenant un circuit intégré Download PDF

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Publication number
WO2010116993A1
WO2010116993A1 PCT/JP2010/056230 JP2010056230W WO2010116993A1 WO 2010116993 A1 WO2010116993 A1 WO 2010116993A1 JP 2010056230 W JP2010056230 W JP 2010056230W WO 2010116993 A1 WO2010116993 A1 WO 2010116993A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
heat sink
wiring
mounting structure
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2010/056230
Other languages
English (en)
Japanese (ja)
Inventor
洋 提坂
公則 大久保
英正 久保田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of WO2010116993A1 publication Critical patent/WO2010116993A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/002—Casings with localised screening
    • H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
    • H05K9/0024—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields
    • H05K9/0032—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields having multiple parts, e.g. frames mating with lids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0233—Filters, inductors or a magnetic substance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0234—Resistors or by disposing resistive or lossy substances in or near power planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/08—Magnetic details
    • H05K2201/083—Magnetic materials
    • H05K2201/086—Magnetic materials for inductive purposes, e.g. printed inductor with ferrite core
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10022—Non-printed resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Definitions

  • the present invention relates to an integrated circuit mounting structure, and more particularly to an integrated circuit mounting structure capable of reducing radiation of electromagnetic waves.
  • a heat sink made of a material having a high thermal conductivity is brought into contact with the integrated circuit to efficiently dissipate heat generated by the integrated circuit during operation, thereby reducing the temperature.
  • a metal such as aluminum having high thermal conductivity is used as the material of the heat sink, and the heat sink is softly provided between the integrated circuit in order to secure a stable contact area with the integrated circuit.
  • a technique of inserting a sheet-like heat radiation sheet having high thermal conductivity is used.
  • a heat radiating sheet is used which is electrically insulative so that the element on the printed circuit board and the heat sink do not short-circuit.
  • EMI Electromagnetic Interference
  • EMI radiated from electronic devices may affect other electronic devices, such as malfunctions, regulatory values for EMI are set in each country. Since electronic device manufacturers cannot ship products unless the EMI generated from the products is kept below the regulation value, the importance of EMI countermeasures is increasing in product development.
  • Non-Patent Document 1 silicon in an integrated circuit is used.
  • RF radio frequency
  • Non-Patent Document 1 the heat sink is used as a common mode decoupling capacitor by conducting the heat sink with the ground plane of the printed circuit board, and the RF current is kept between the heat sink and the ground plane of the board. Measures to reduce EMI emissions into free space are described. In addition, this measure is described as effective up to the self-resonant frequency of the decoupling capacitor.
  • Non-Patent Document 1 regarding the conductive portion of the heat sink and the ground plane of the substrate, all four side surfaces are covered with a metal partition, and the portion where the partition and the printed circuit board are in contact is a ground pattern. And measures to be housed in a shield case made up of a heat sink and a metal partition.
  • Patent Document 1 describes the area around the integrated circuit in the gap between the printed circuit board and the heat sink. A method is described for converting RF energy radiated into free space into heat, which is prevented by an electromagnetic absorbing material.
  • Patent Document 1 furthermore, as an example of the electromagnetic wave absorbing material, a nonconductive silicone rubber filled with a conductive material and a semiconductor material, or a surface of a lossy material containing a magnetic compound such as ferrite can be satisfactorily used as an insulator. Covered sheet material is described.
  • the component cost of the electromagnetic wave absorbing material described in Patent Document 1 is about several times the price difference compared to the heat dissipation sheet inserted between the integrated circuit and the heat sink, and the price difference cannot be ignored in consumer electronic devices. It has become.
  • the heat generation amount of the integrated circuit is increased and the opposing area of the heat sink and the substrate is increased for the purpose of increasing the heat dissipation amount, more electromagnetic wave absorbing material is required, and the component cost increases.
  • the frequency band where the countermeasure is effective is a capacitor (in this case, the heat sink and the substrate Since it is up to the self-resonant frequency of the ground plane), it is not a sufficient measure for electronic devices using a high-frequency clock in recent years.
  • the present invention was invented in view of the above-described problems, and an object thereof is to realize a countermeasure for the EMI problem caused by a heat sink at low cost without using an electromagnetic wave absorbing material and a partition wall.
  • An integrated circuit mounting structure includes a substrate, an integrated circuit mounted on the substrate, a conductive heat dissipation element that contacts the integrated circuit, and a fixing portion that fixes the heat dissipation element to the substrate.
  • a circuit element having electrical loss is connected to the heat dissipation element and the conductor.
  • the resonance energy is converted into thermal energy by the circuit element.
  • the EMI problem can be solved.
  • the conductor is a wiring provided on the substrate.
  • the wiring is either a ground potential wiring or a power supply wiring.
  • the conductor is a shield member that covers the heat dissipation element.
  • the circuit element having electrical loss is any of a component including a resistor other than a 0 ⁇ resistor and a ferrite.
  • the resistance value of the circuit element having electrical loss is a characteristic impedance between the heat dissipation element and the ground of the substrate.
  • the heat dissipating element is a quadrangle, and the fixed part is disposed at a diagonal part of the heat dissipating element.
  • the heat sink structure for reducing unnecessary electromagnetic radiation and mounting on a printed circuit board can be realized at low cost without impairing the heat dissipation of the integrated circuit by the heat sink.
  • FIG. 1 It is sectional drawing which shows typically the printed circuit board which has a heat sink according to this invention. It is a top view which shows the printed circuit board used for the electromagnetic field analysis, and the heat sink provided on it. It is a figure which expands and shows the periphery of the heat sink 102 of FIG. It is the graph which showed the electric field strength value between the heat sink 102 and the printed circuit board 101 in each frequency computed as a result of the electromagnetic field analysis obtained by changing the kind of circuit element 1051,1052 which has electrical loss property. It is the graph which showed the electric field strength value between the heat sink 102 and the printed circuit board 101 in each frequency computed as a result of the electromagnetic field analysis obtained by changing the kind of circuit element 1051,1052 which has electrical loss property.
  • FIG. 1 is a cross-sectional view schematically showing a printed circuit board having a heat sink according to the present invention.
  • the printed circuit board 1 has a wiring pattern and a through hole constituting a circuit such as the first wiring 3 and the second wiring 4 on a base material made of a dielectric.
  • the printed board 1 is described as a multilayer board.
  • an integrated circuit package 7 and a circuit element 5 having electrical loss are mounted by solder or the like, and are electrically connected to a wiring pattern on the printed circuit board 1.
  • the integrated circuit package 7 and the heat sink 2 are in contact with the heat dissipation sheet 6 having high thermal conductivity, and the heat from the integrated circuit package 7 is efficiently radiated into the air by the heat sink 2.
  • the heat sink 2 as a heat dissipating element has heat dissipating fins 21 and contacts 22.
  • the contact 22 is electrically connected to the first pattern of the substrate using a method such as soldering.
  • the material of the heat sink 2 is made of a metal such as aluminum having high thermal conductivity in order to improve heat dissipation.
  • the contact 22 is made of metal for the purpose of conducting the heat sink 2 and the first wiring 3 with low impedance.
  • both the heat sink 2 and the contact 22 are made of aluminum, and the heat sink 2 is fixed to the printed circuit board 1 by the contact 22.
  • Other elements such as a heat pipe may be used as the heat dissipation element.
  • the first wiring 3 is a wiring for mounting the heat sink contact 22 on the printed circuit board.
  • the contact 22 and the first wiring 3 are electrically connected in the connection portion 32.
  • the contact 22 should just be provided in at least one place.
  • the second wiring 4 is electrically connected to the first wiring 3 through a circuit element 5 having electrical loss.
  • the second wiring 4 is set to a ground potential that occupies a large wiring area on the printed board 1.
  • circuit element 5 having electrical loss a circuit component using a resistor other than 0 ⁇ or a ferrite that converts electrical energy of a high frequency component into heat is used.
  • the circuit components described above are used for at least one circuit element 5 having electrical loss characteristics.
  • the heat radiating sheet 6 is used when it is necessary to lower the thermal resistance between the integrated circuit package 7 and the heat sink 2, and may be omitted if there is no problem in heat dissipation. Further, the material of the heat dissipation sheet 6 may not have the electromagnetic wave absorbing property described in Patent Document 1.
  • the integrated circuit package 7 includes a silicon die of an integrated circuit, an interposer substrate, and bonding wires that electrically connect the two.
  • the integrated circuit mounting structure 50 includes a printed circuit board 1 as a substrate, an integrated circuit package 7 as an integrated circuit placed on the printed substrate 1, and an integrated circuit package 7 A heat sink 2 as a conductive heat dissipation element, a connection portion 32 as a fixing portion for fixing the heat sink 2 to the printed circuit board 1, and an electromagnetic coupling with the heat sink 2 provided on the printed circuit board 1.
  • It has the 2nd wiring 4 as a conductor, and the circuit element 5 which has the electrical loss property electrically connected with the 2nd wiring 4 and the heat sink 2.
  • the heat sink 2 may be replaced by another conductive heat dissipating element such as a heat tube.
  • the presence or absence of electromagnetic coupling between the heat sink 2 and the second wiring 4 depends on whether the circuit element 5 having electrical loss is a 0 ⁇ resistor or when the circuit element 5 is removed and opened. Is determined by whether or not the electromagnetic field intensity distribution near, or the intensity of EMI changes. That is, when the nearby electromagnetic field intensity distribution or EMI intensity changes due to a change in the circuit element 5 that electrically connects the heat sink 2 and the second wiring 4, the heat sink 2 and the second wiring 4. Can be said to be electromagnetically coupled.
  • FIG. 2 is a plan view showing a printed circuit board used for electromagnetic field analysis and a heat sink provided thereon.
  • a heat sink 102 is provided on the printed circuit board 101.
  • FIG. 2 shows a top view of the heat sink 102 as viewed from the mounting surface.
  • the external dimensions of the heat sink 102 viewed from the upper surface direction were 58 mm ⁇ 36 mm, and the height of the heat sink 102 measured from the printed board 101 was 4 mm.
  • FIG. 3 is an enlarged view showing the periphery of the heat sink 102 of FIG.
  • a second wiring 104 and a first wiring 103 are provided on the printed circuit board 101.
  • the heat sink 102 is electrically connected to the first wiring 103 through a contact 1022.
  • the contacts 1022 are arranged at diagonal portions of the heat sink 102.
  • the second wiring 104 is a ground potential (ground potential) that is a reference potential of the printed circuit board 101.
  • the second wiring 104 actually has a slit for avoiding a short circuit with another signal line, but this is not described in FIGS. 2 and 3.
  • Example 1 an integrated circuit package (height 2 mm) made of a dielectric and a heat dissipation sheet (height 2 mm) also made of a dielectric are inserted into a region 106 (20 mm ⁇ 20 mm).
  • the relative dielectric constant of the integrated circuit package and the heat dissipation sheet are both 5.0.
  • Equation 1 shows an approximate value of the characteristic impedance value of the microstrip line.
  • W is the conductor width (in this embodiment, the short side length of the heat sink 102)
  • d is the height of the conductor (in this embodiment, the distance between the second wiring 104 and the bottom surface of the heat sink 102)
  • ⁇ r is a relative dielectric constant (in this embodiment, the relative dielectric constant of air).
  • Equation 1 when the characteristic impedance between the second wiring 104 of the printed circuit board 101 and the heat sink 102 is obtained for the cross-sectional shape parallel to the short side between the heat sinks 102, it is about 31 ⁇ . Since an integrated circuit package having a relative dielectric constant of 1 or more and a heat radiation sheet are inserted between the heat sink 102 and the second wiring 104, the effective value of the characteristic impedance is considered to be smaller than 31 ⁇ .
  • the resistance value is lower than 31 ⁇ , and 22 ⁇ is used as the resistance value given in the E6 series of JIS C 5063.
  • a small dipole antenna is installed in the specific unit 107 in the integrated circuit package, and a Gaussian pulse is used to simulate a broadband noise component. And analyzed in the time domain.
  • the electromagnetic field analysis uses a time domain finite difference method (Finite Difference Time Domain Method, FDTD method).
  • FIG. 4 is a graph showing the electric field strength value between the heat sink 102 and the printed circuit board 101 at each frequency, calculated as a result of electromagnetic field analysis obtained by changing the types of circuit elements 1051 and 1052 having electrical loss characteristics. It is.
  • the three components are as follows: (1) The heat dissipation plate described in Non-Patent Document 1 is short-circuited to the ground of the substrate, and the resistance of the circuit elements 1051 and 1052 having electrical loss is set to 0 ⁇ . It is shown with a solid line. (2) As an example of the present invention, the case where the resistance of the circuit elements 1051 and 1052 having electrical loss is 22 ⁇ is shown by a thick solid line. (3) The case where a noise countermeasure chip component using ferrite is used for the circuit elements 1051 and 1052 having electrical loss is shown by dotted lines. Here, FBMJ2125HM210NT manufactured by Taiyo Yuden Co., Ltd. was used as a noise countermeasure chip component using the ferrite of (3).
  • the FBMJ2125HM210NT is a circuit component having an upper limit of DC resistance of 0.004 ⁇ and an impedance of 21 ⁇ at 100 MHz.
  • An equivalent circuit diagram of the FBMJ2125HM210NT used for the electromagnetic field analysis is shown in FIG.
  • the conventional technology has a resonance component at about 830 MHz. This corresponds to the self-resonant frequency of the capacitor by the heat sink in Non-Patent Document 1, and the EMI generated from the device becomes a problem when the operating frequency of the integrated circuit and its harmonic components are close to the self-resonant frequency.
  • FIG. 5 is a graph showing the electric field strength value between the heat sink 102 and the printed circuit board 101 at each frequency, calculated as a result of electromagnetic field analysis obtained by changing the types of circuit elements 1051 and 1052 having electrical loss characteristics. It is.
  • FIG. 5 is a graph showing the electric field strength value between the heat sink 102 and the printed circuit board 101 converted into the frequency domain based on the analysis result performed for verifying the resistance value in the present invention, as in FIG.
  • the three components are indicated by thick solid lines in the case where (4) the resistance value of the circuit elements 1051 and 1052 having electrical loss is 1 ⁇ .
  • a dotted line indicates a case where the resistance value of the circuit elements 1051 and 1052 having electrical loss is 1 k ⁇ .
  • the case where the circuit elements 1051 and 1052 having electrical loss are opened is indicated by a thin solid line.
  • the electric field strength value at the self-resonance (850 MHz) of the capacitor of the heat sink is reduced by about 30 dB.
  • the self-resonant energy is consumed by the resistance, so that the peak value of the electric field strength is lowered. Can be reduced.
  • the self-resonant frequency has shifted to 820 MHz as in the case of opening (6), but the peak at resonance is reduced compared to (1) and (6).
  • EMI can be reduced.
  • the RF energy at the time of resonance is consumed by the resistance, so that the EMI is lower than that at the time of opening of (6). It can be seen that it has been reduced.
  • FIG. 6 is a graph showing the electric field strength value between the heat sink 102 and the printed circuit board 101 at each frequency, calculated as a result of electromagnetic field analysis obtained by changing the types of circuit elements 1051 and 1052 having electrical loss characteristics. It is.
  • FIG. 6 is a diagram in which the electric field strength value between the printed circuit board 101 and the printed circuit board 101 is converted into the frequency domain and plotted with a dotted line in the graph together with the analysis results in the cases (1) and (2).
  • FIG. 8 is a diagram for explaining an integrated circuit mounting structure according to the second embodiment of the present invention.
  • the integrated circuit mounting structure according to the second embodiment of the present invention is different from the structure according to the first embodiment in that shield member 60 is provided so as to cover heat sink 2. Different. Between the shield member 60 having conductivity and the heat sink 2, the circuit element 5 having electrical loss is interposed.
  • the shield member 60 and the heat sink 2 are connected to each other with the first wiring 3 and the second wiring 4 interposed therebetween, and an electrical loss is caused between the shield member 60 and the heat sink 2 without interposing these wirings.
  • the circuit element 5 which has property may be provided. Further, the shield member 60 and the heat sink 2 may be connected via the first wiring 3, the second wiring 4, and the chassis ground.
  • the shield member 60 is capacitively coupled to the heat sink 2.
  • the shield member 60 is made of a material having high conductivity, such as an aluminum alloy.
  • the integrated circuit mounting structure according to the second embodiment configured as described above has the same effect as that of the first embodiment.
  • the structure according to the present invention can be applied to all electronic devices including digital devices such as a personal computer, a DVD, a Blu-ray recorder, and a navigation system.
  • the present invention can be applied to a printed circuit board of an electronic device having a heat sink.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Non-Reversible Transmitting Devices (AREA)

Abstract

La présente invention concerne une structure dans laquelle un circuit intégré a été monté, permettant de réduire les EMI (interférences électromagnétiques) dans un appareil électronique dans lequel le circuit électrique a été monté sur une carte de circuit imprimé. Un dissipateur thermique (2) est placé en contact avec un module de circuit intégré (7). Un élément circuit (5) ayant une perte électrique est placé entre le dissipateur thermique (2) et le second câblage (4).
PCT/JP2010/056230 2009-04-07 2010-04-06 Structure contenant un circuit intégré Ceased WO2010116993A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-093192 2009-04-07
JP2009093192A JP4958189B2 (ja) 2009-04-07 2009-04-07 集積回路の搭載構造

Publications (1)

Publication Number Publication Date
WO2010116993A1 true WO2010116993A1 (fr) 2010-10-14

Family

ID=42936276

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Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
JP6127429B2 (ja) * 2012-09-28 2017-05-17 富士通株式会社 冷却装置及び電子装置
JP6045427B2 (ja) * 2013-04-08 2016-12-14 三菱電機株式会社 電磁波シールド構造および高周波モジュール構造
JP7069866B2 (ja) * 2017-09-29 2022-05-18 株式会社アイシン チップ放熱システム
JP6905016B2 (ja) * 2019-09-10 2021-07-21 Ｎｅｃプラットフォームズ株式会社 実装基板構造

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06252282A (ja) * 1993-02-24 1994-09-09 Nec Corp パッケージのシールド構造
JPH11259172A (ja) * 1998-03-06 1999-09-24 Canon Inc 電子機器
JPH11261181A (ja) * 1998-03-16 1999-09-24 Nec Corp プリント回路基板
JP2000115086A (ja) * 1998-09-30 2000-04-21 Em Techno:Kk 電磁遮蔽電子回路基板

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0730280A (ja) * 1993-07-09 1995-01-31 Sony Corp シールドケース
JP2853618B2 (ja) * 1995-11-15 1999-02-03 日本電気株式会社 電子装置の放熱構造
JP3012867B2 (ja) * 1998-01-22 2000-02-28 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュ―タ用ヒ―トシンク装置
JP2000133986A (ja) * 1998-10-27 2000-05-12 Murata Mfg Co Ltd 放射ノイズ抑制部品の取付構造
JP4914678B2 (ja) * 2006-08-31 2012-04-11 任天堂株式会社 電子機器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06252282A (ja) * 1993-02-24 1994-09-09 Nec Corp パッケージのシールド構造
JPH11259172A (ja) * 1998-03-06 1999-09-24 Canon Inc 電子機器
JPH11261181A (ja) * 1998-03-16 1999-09-24 Nec Corp プリント回路基板
JP2000115086A (ja) * 1998-09-30 2000-04-21 Em Techno:Kk 電磁遮蔽電子回路基板

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