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WO2010038168A3 - Limited instruction set computing (lisc), zero instruction set computing (zisc), dynamic linking instruction set (dlisc) based processor / computing machine / apparatus - Google Patents

Limited instruction set computing (lisc), zero instruction set computing (zisc), dynamic linking instruction set (dlisc) based processor / computing machine / apparatus Download PDF

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Publication number
WO2010038168A3
WO2010038168A3 PCT/IB2009/054116 IB2009054116W WO2010038168A3 WO 2010038168 A3 WO2010038168 A3 WO 2010038168A3 IB 2009054116 W IB2009054116 W IB 2009054116W WO 2010038168 A3 WO2010038168 A3 WO 2010038168A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction set
computing
dlisc
zisc
lisc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2009/054116
Other languages
French (fr)
Other versions
WO2010038168A2 (en
Inventor
Suminda Dharmasena
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of WO2010038168A2 publication Critical patent/WO2010038168A2/en
Publication of WO2010038168A3 publication Critical patent/WO2010038168A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

This invention introduces new modes of computing which would facilitate greater levels instruction parallelism. The apparatus contemplated are implemented as a dynamic network of function where the network topology is dynamically altered.
PCT/IB2009/054116 2008-10-02 2009-09-20 Limited instruction set computing (lisc), zero instruction set computing (zisc), dynamic linking instruction set (dlisc) based processor / computing machine / apparatus Ceased WO2010038168A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
LK1513808 2008-10-02
LK15138 2008-10-02

Publications (2)

Publication Number Publication Date
WO2010038168A2 WO2010038168A2 (en) 2010-04-08
WO2010038168A3 true WO2010038168A3 (en) 2010-07-08

Family

ID=42035964

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2009/054116 Ceased WO2010038168A2 (en) 2008-10-02 2009-09-20 Limited instruction set computing (lisc), zero instruction set computing (zisc), dynamic linking instruction set (dlisc) based processor / computing machine / apparatus

Country Status (1)

Country Link
WO (1) WO2010038168A2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007039837A2 (en) * 2005-09-15 2007-04-12 Dharmasena Suminda Sirinath Sa Implied instruction set computing (iisc) / dual instruction set computing (disc) / single instruction set computing (sisc) / recurring multiple instruction set computing (rmisc) based computing machine / apparatus / processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007039837A2 (en) * 2005-09-15 2007-04-12 Dharmasena Suminda Sirinath Sa Implied instruction set computing (iisc) / dual instruction set computing (disc) / single instruction set computing (sisc) / recurring multiple instruction set computing (rmisc) based computing machine / apparatus / processor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CORPORAAL H ET AL: "MOVE32INT, A SEA OF GATES REALIZATION OF A HIGH PERFORMANCE TRANSPORT TRIGGERED ARCHITECTURE", MICROPROCESSING AND MICROPROGRAMMING, ELSEVIER SCIENCE PUBLISHERS, BV., AMSTERDAM, NL LNKD- DOI:10.1016/0165-6074(93)90125-5, vol. 38, no. 1 / 05, 1 September 1993 (1993-09-01), pages 53 - 60, XP000383760, ISSN: 0165-6074 *
JAN HOOGERBRUGGE: "Code Generation for Transport Triggered Architectures", PROEFSCHRIFT UNIVERSITEIT DELFT, XX, XX, 5 February 1996 (1996-02-05), pages COMPLETE, XP002303070 *

Also Published As

Publication number Publication date
WO2010038168A2 (en) 2010-04-08

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