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WO2010031203A1 - Élément de résistance à semi-conducteurs à haute résistivité - Google Patents

Élément de résistance à semi-conducteurs à haute résistivité Download PDF

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Publication number
WO2010031203A1
WO2010031203A1 PCT/CN2008/001619 CN2008001619W WO2010031203A1 WO 2010031203 A1 WO2010031203 A1 WO 2010031203A1 CN 2008001619 W CN2008001619 W CN 2008001619W WO 2010031203 A1 WO2010031203 A1 WO 2010031203A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
resistive
semiconductor
high resistivity
resistor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2008/001619
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English (en)
Chinese (zh)
Inventor
弗朗西斯科·格雷诺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Grace Semiconductor Manufacturing Corp filed Critical Grace Semiconductor Manufacturing Corp
Priority to PCT/CN2008/001619 priority Critical patent/WO2010031203A1/fr
Publication of WO2010031203A1 publication Critical patent/WO2010031203A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H10W20/498—

Definitions

  • the present invention relates to a technique for fabricating a semiconductor resistor element, and more particularly to a semiconductor device having a high resistivity and an element and a method of fabricating the same.
  • the polysilicon is a pure silicon material composed of small single crystal silicon grains of different crystal orientations, wherein each single crystal grain in the mother crystal silicon is composed of crystal grains.
  • the interface (Grain Boundary) is separated. And because the grain interface contains various line defects and point defects, the diffusion ability of the dopants through these grain boundaries will be faster than that through the inside of the grains.
  • the polysilicon may be doped to change its electrical properties and obtain a polysilicon material that meets the processing conditions; in other words, the fabrication of solid electronic components is usually performed by doping dopants of different properties and concentrations to adjust the polysilicon material.
  • the characteristics of the electrical characteristics are used to design electronic components with different functionalities. Therefore, the use of polycrystalline silicon itself has a high electrical resistivity and can be used as a resistive element for IC design.
  • Fig. 1 is a cross-sectional view showing the structure of a prior art resistive element
  • Fig. 2 is a top plan view showing the structure of the prior art resistive element.
  • the resistive element forms a layer of polycrystalline silicon 12 on the substrate 10, and a poly-seal layer 12 is formed at both ends thereof to form a salicide 16 having contact pads 18 for connection to external leads. Since the resistive element 'must be non-salicide, the surface of the polysilicon layer 12 is covered with a barrier oxide layer 14 to prevent the formation of the metal silicide 16 between the polysilicon layer 12 and the barrier oxide layer 14.
  • the resistive element When the resistive element has a high resistivity, such as greater than ⁇ ⁇ /m, an interface resistance is generated between the metal silicide 16 and the non-metal silicide region caused by the oxide layer 14 being blocked, the interface The generation of the resistance increases the resistivity of the polysilicon resistor element, but since the interface resistance can only be generated at the boundary between the metal silicide 16 and the non-metal germanide region, the configuration of the existing resistor element produces a small amount of interface resistance. Therefore, a large increase in the resistivity of the polysilicon resistor element cannot be obtained.
  • High-voltage integrated circuit products often use high-resistance resistive components and integrate them directly inside the integrated circuit to reduce the chip's geometry. For example, when ultra-low-power devices require resistive components with large resistivity. Usually, this requires an additional etching process for the semiconductor, such as doping or undoped polysilicon as the material of the high-resistance element, called high-resistance polysilicon, but because of the need to increase the etching and implantation process Not only does it increase costs, it wastes time, affects efficiency, and has a negative impact on the yield of semiconductor components. Summary of the invention
  • An object of the present invention is to provide a semiconductor resistor element having a high resistivity and a method of manufacturing the same, which does not require a process change, does not require additional etching, and can reduce the size of the semiconductor resistor element.
  • the present invention provides a method of fabricating a semiconductor resistive element having a high resistivity, comprising the steps of: forming a resistive layer on a semiconductor substrate; forming a plurality of spaced apart regions on the surface of the resistive layer a strip-shaped barrier oxide layer; each of the plurality of strip-shaped barrier oxide layers blocks f on both sides of the oxide layer and forms a metal silicide layer on the surface of the resist layer.
  • the manufacturing method further includes forming an oxide layer covering the surface of the plurality of strip-shaped barrier oxide layers and the metal silicide layer, and exposing only a portion of the metal silicide as a contact pad.
  • the above oxide layer is formed by a chemical vapor deposition method.
  • the plurality of strip-shaped barrier oxide layers have a set width.
  • the impedance layer is a polysilicon layer, an active injection layer or an active well layer
  • the resistive component is a non-metal polysilicon resistive component, a non-metal silicide active implanted region resistive component, or a non-metal silicide active well resistive component.
  • the resistive element is a P+ type polysilicon resistance element, an N+ type polysilicon resistance element, a P+ type diffusion resistance element, an N+ type diffusion resistance element, a high resistance polysilicon resistance element or a well area resistance element.
  • the present invention further provides a semiconductor resistor element having a high resistivity, characterized in that the structure comprises: a semiconductor substrate having a resistive layer formed thereon; a plurality of strip-shaped barrier oxide layers formed on the impedance a surface of the layer, wherein the plurality of strip-shaped barrier oxide layers have a certain interval; and a plurality of metal silicides are formed on the surface of the resistive layer on each of the plurality of strip-blocking oxide layers on both sides of the barrier layer.
  • the semiconductor resistor element further includes an oxide layer covering the surface of the plurality of strip-shaped barrier oxide layers and the metal silicide layer, and only a portion of the metal silicide is exposed as a contact pad.
  • the above oxide layer is formed by a chemical vapor deposition method.
  • the plurality of strip-shaped barrier oxide layers have a set width.
  • the impedance is a polysilicon layer, an active injection layer or an active well layer.
  • the resistive component is a non-metal polysilicon resistive component, a non-metal silicide active implanted region resistive component, or a non-metal silicide active well resistive component.
  • the resistance element is a P+ type polysilicon resistance element, an N+ type polysilicon resistance element, and a P+ type expansion Dispersion resistance element, N+ type diffusion resistance element, high resistance polysilicon resistance element or well area resistance element.
  • a semiconductor resistor element having a high resistivity and a method of manufacturing the same according to the present invention wherein a plurality of strip-shaped barrier oxide layers having a certain interval are formed on a surface of a polysilicon layer, and an interface resistance is generated between the metal silicide and the barrier oxide layer.
  • a plurality of increased interfacial resistances are formed on the semiconductor resistive element processed in the above steps, thereby increasing the resistivity of the semiconductor resistive element, which does not require a process change, does not require additional etching, and can reduce the size of the semiconductor resistive element, thereby reducing Production costs, time savings, increased production efficiency and reduced negative impact on the yield of semiconductor components.
  • Figure 1 is a cross-sectional view showing the structure of a prior art resistive element
  • FIG. 2 is a top plan view showing the structure of a prior art resistive element
  • Figure 3 is a cross-sectional view showing the structure of a resistive element according to a preferred embodiment of the present invention.
  • FIG. 4 is a top plan view showing a construction of a preferred embodiment of the present invention. detailed description
  • FIG. 3 is a cross-sectional view showing the structure of a resistive element according to a preferred embodiment of the present invention
  • FIG. 4 is a top view showing the structure of a preferred embodiment of the present invention.
  • a method of fabricating a semiconductor resistive element having a high resistivity according to the present invention comprises the steps of: forming a resistive layer 22 on a half of the conductive substrate 20, and then using a chemical vapor deposition (CVD) method in conjunction with a photolithography process
  • a plurality of strip-shaped barrier oxide layers 24 spaced apart from each other as a self-aligned metal silicide are formed on the surface of the resistive layer 22, the thickness of which is determined by the process itself, and the plurality of strip-shaped barrier oxide layers 24 can be avoided.
  • Metal silicide is formed between the above-described resistive layer 22 and the plurality of strip-shaped barrier oxide layers 24 during the formation of the subsequent self-aligned metal silicide.
  • a self-aligned metal silicide process can then be performed to form a metal silicide layer 26 on the surface of the resistive layer 22 on both sides of the plurality of strip-shaped barrier oxide layers 24.
  • the impedance layer 22 is a polysilicon layer, an active injection layer or an active well layer.
  • the metal silicide layer 26 is formed by sputtering a metal layer on the surface of the polysilicon layer 22 and the plurality of strip-shaped barrier oxide layers 24; and performing the first high-temperature rapid heating (RTA).
  • the metal layer is contacted with the surface of the polysilicon layer 22 covered by the unimpeded oxide layer 24 to generate a silicidation reaction and the self-aligned metal silicide 26; while the metal layer remaining after the reaction or reaction is not wet etching Selectively remove and perform a second high temperature A rapid heating process allows a stable self-aligned metal silicide 26 structure to be formed on the semiconductor substrate 20.
  • an oxide layer 30 is deposited on the surface of the plurality of strip-shaped barrier oxide layers 24 and the metal silicide 26 by a chemical vapor deposition method, and only a portion of the metal silicide 26 is exposed to serve as the contact pad 28, and the contact pad 28 is used. Used to form an electrical connection with an external wire.
  • the plurality of strip-shaped barrier oxide layers 24 have a set width.
  • the spacing, the width and the slope of the plurality of strip-shaped barrier oxide layers 24 can be set according to actual needs to meet different resistance values, because the plurality of strip-shaped barrier oxide layers 24 are mutually There is a certain interval therebetween, so in the self-aligned germanium silicide process, only the metal silicide layer 26 is formed between the plurality of strip-shaped barrier oxide layers 24, when the resistive element is high resistivity, such as greater than ⁇ /m, an interface resistance is generated between the metal silicide 26 and the barrier oxide layer 24, so that an interface resistance is formed between each of the strip-shaped barrier oxide layer 24 and the metal silicide 26, that is, a plurality of interface resistances are generated. , thereby increasing the resistance of the number of the semiconductor elements and electrically ⁇ 1.
  • the resistive element is a non-metallic polysilicon resistive component, a non-metal silicide active implanted region resistive component, or a non-metal silicide active well resistive component.
  • the resistor element may be a P+ type polysilicon resistor element, an N+ type polysilicon resistor element, a P+ type diffusion resistance element, an N+ type diffusion resistance element, a high resistance polysilicon resistance element or a well area resistance element.
  • the present invention further provides a semiconductor resistor element having a high resistivity, the structure comprising: a semiconductor substrate 20 having a resistive layer 22 formed thereon; a plurality of strip-shaped barrier oxide layers 24 formed on the surface of the resistive layer 22, wherein The plurality of strip-shaped barrier oxide layers 24 are spaced apart from each other; and a plurality of metal silicides 26 are formed on the surface of the resistive layer 22 on each of the plurality of strip-shaped barrier oxide layers 24 on both sides of the barrier oxide layer.
  • the resistive layer 22 is a polysilicon layer, an active implant layer or an active well layer.
  • the plurality of strip-shaped barrier oxide layers 24 have a set width. At the same time, the spacing, width and slope of the plurality of strip-shaped barrier oxide layers 24 can be set according to actual needs to meet different resistance values because the plurality of strip-shaped barrier oxide layers 24 are spaced apart from each other.
  • the metal silicide layer 26 is formed between the plurality of strip-shaped barrier oxide layers 24, and when the resistive element has a high resistivity, such as greater than ⁇ /m, the metal An interface resistance is generated between the silicide 26 and the barrier oxide layer 24, so that an interface resistance is formed between each of the strip-shaped barrier oxide layer 24 and the metal silicide 26, that is, a plurality of interface resistances are generated, thereby increasing the The resistivity of the semiconductor resistive element.
  • the resistive element is a non-metallic polysilicon resistive component, a non-metal silicide active implanted region resistive component, or a non-metal silicide active well region resistive component.
  • the resistor element may further be a P+ type polysilicon resistance element, an N+ type polysilicon resistance element, a P+ type diffusion resistance element, an N+ type diffusion resistance element, a high resistance polysilicon resistance element or a well area resistance element.
  • a semiconductor resistor element having a high resistivity and a method of manufacturing the same according to the present invention wherein a plurality of strip-shaped barrier oxide layers having a certain interval are formed on a surface of a polysilicon layer, and an interface resistance is generated between the metal silicide and the barrier oxide layer.
  • a plurality of increased interfacial resistances are formed on the semiconductor resistive element processed in the above steps, thereby increasing the resistivity of the semiconductor resistive element, which does not require a process, and does not require additional etching while reducing the size of the semiconductor resistive element. Therefore, the production cost is reduced, the time is saved, the production efficiency is improved, and the negative impact on the yield of the semiconductor element is reduced.

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  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention porte sur un élément de résistance à semi-conducteurs à haute résistivité et sur le procédé associé, le procédé comprenant les étapes suivantes : une couche d'impédance (22) est formée sur un substrat semi-conducteur (20), de nombreuses couches d'oxydation barrières en bande (24) sont formées sur la surface de la couche d'impédance (22), des espaces sont définis entre les couches d'oxydation barrières en bande (24), et des couches de siliciure auto-aligné (26) sont formées sur la couche d'impédance (22) qui est en contact avec les deux côtés de chaque couche d'oxydation barrière en bande (24).
PCT/CN2008/001619 2008-09-16 2008-09-16 Élément de résistance à semi-conducteurs à haute résistivité Ceased WO2010031203A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2008/001619 WO2010031203A1 (fr) 2008-09-16 2008-09-16 Élément de résistance à semi-conducteurs à haute résistivité

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2008/001619 WO2010031203A1 (fr) 2008-09-16 2008-09-16 Élément de résistance à semi-conducteurs à haute résistivité

Publications (1)

Publication Number Publication Date
WO2010031203A1 true WO2010031203A1 (fr) 2010-03-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2008/001619 Ceased WO2010031203A1 (fr) 2008-09-16 2008-09-16 Élément de résistance à semi-conducteurs à haute résistivité

Country Status (1)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5362662A (en) * 1989-08-11 1994-11-08 Ricoh Company, Ltd. Method for producing semiconductor memory device having a planar cell structure
CN1146072A (zh) * 1995-06-30 1997-03-26 现代电子产业株式会社 用于制造半导体器件的方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5362662A (en) * 1989-08-11 1994-11-08 Ricoh Company, Ltd. Method for producing semiconductor memory device having a planar cell structure
CN1146072A (zh) * 1995-06-30 1997-03-26 现代电子产业株式会社 用于制造半导体器件的方法

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