WO2010031203A1 - High resistivity semiconductor resistance element - Google Patents
High resistivity semiconductor resistance element Download PDFInfo
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- WO2010031203A1 WO2010031203A1 PCT/CN2008/001619 CN2008001619W WO2010031203A1 WO 2010031203 A1 WO2010031203 A1 WO 2010031203A1 CN 2008001619 W CN2008001619 W CN 2008001619W WO 2010031203 A1 WO2010031203 A1 WO 2010031203A1
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- the present invention relates to a technique for fabricating a semiconductor resistor element, and more particularly to a semiconductor device having a high resistivity and an element and a method of fabricating the same.
- the polysilicon is a pure silicon material composed of small single crystal silicon grains of different crystal orientations, wherein each single crystal grain in the mother crystal silicon is composed of crystal grains.
- the interface (Grain Boundary) is separated. And because the grain interface contains various line defects and point defects, the diffusion ability of the dopants through these grain boundaries will be faster than that through the inside of the grains.
- the polysilicon may be doped to change its electrical properties and obtain a polysilicon material that meets the processing conditions; in other words, the fabrication of solid electronic components is usually performed by doping dopants of different properties and concentrations to adjust the polysilicon material.
- the characteristics of the electrical characteristics are used to design electronic components with different functionalities. Therefore, the use of polycrystalline silicon itself has a high electrical resistivity and can be used as a resistive element for IC design.
- Fig. 1 is a cross-sectional view showing the structure of a prior art resistive element
- Fig. 2 is a top plan view showing the structure of the prior art resistive element.
- the resistive element forms a layer of polycrystalline silicon 12 on the substrate 10, and a poly-seal layer 12 is formed at both ends thereof to form a salicide 16 having contact pads 18 for connection to external leads. Since the resistive element 'must be non-salicide, the surface of the polysilicon layer 12 is covered with a barrier oxide layer 14 to prevent the formation of the metal silicide 16 between the polysilicon layer 12 and the barrier oxide layer 14.
- the resistive element When the resistive element has a high resistivity, such as greater than ⁇ ⁇ /m, an interface resistance is generated between the metal silicide 16 and the non-metal silicide region caused by the oxide layer 14 being blocked, the interface The generation of the resistance increases the resistivity of the polysilicon resistor element, but since the interface resistance can only be generated at the boundary between the metal silicide 16 and the non-metal germanide region, the configuration of the existing resistor element produces a small amount of interface resistance. Therefore, a large increase in the resistivity of the polysilicon resistor element cannot be obtained.
- High-voltage integrated circuit products often use high-resistance resistive components and integrate them directly inside the integrated circuit to reduce the chip's geometry. For example, when ultra-low-power devices require resistive components with large resistivity. Usually, this requires an additional etching process for the semiconductor, such as doping or undoped polysilicon as the material of the high-resistance element, called high-resistance polysilicon, but because of the need to increase the etching and implantation process Not only does it increase costs, it wastes time, affects efficiency, and has a negative impact on the yield of semiconductor components. Summary of the invention
- An object of the present invention is to provide a semiconductor resistor element having a high resistivity and a method of manufacturing the same, which does not require a process change, does not require additional etching, and can reduce the size of the semiconductor resistor element.
- the present invention provides a method of fabricating a semiconductor resistive element having a high resistivity, comprising the steps of: forming a resistive layer on a semiconductor substrate; forming a plurality of spaced apart regions on the surface of the resistive layer a strip-shaped barrier oxide layer; each of the plurality of strip-shaped barrier oxide layers blocks f on both sides of the oxide layer and forms a metal silicide layer on the surface of the resist layer.
- the manufacturing method further includes forming an oxide layer covering the surface of the plurality of strip-shaped barrier oxide layers and the metal silicide layer, and exposing only a portion of the metal silicide as a contact pad.
- the above oxide layer is formed by a chemical vapor deposition method.
- the plurality of strip-shaped barrier oxide layers have a set width.
- the impedance layer is a polysilicon layer, an active injection layer or an active well layer
- the resistive component is a non-metal polysilicon resistive component, a non-metal silicide active implanted region resistive component, or a non-metal silicide active well resistive component.
- the resistive element is a P+ type polysilicon resistance element, an N+ type polysilicon resistance element, a P+ type diffusion resistance element, an N+ type diffusion resistance element, a high resistance polysilicon resistance element or a well area resistance element.
- the present invention further provides a semiconductor resistor element having a high resistivity, characterized in that the structure comprises: a semiconductor substrate having a resistive layer formed thereon; a plurality of strip-shaped barrier oxide layers formed on the impedance a surface of the layer, wherein the plurality of strip-shaped barrier oxide layers have a certain interval; and a plurality of metal silicides are formed on the surface of the resistive layer on each of the plurality of strip-blocking oxide layers on both sides of the barrier layer.
- the semiconductor resistor element further includes an oxide layer covering the surface of the plurality of strip-shaped barrier oxide layers and the metal silicide layer, and only a portion of the metal silicide is exposed as a contact pad.
- the above oxide layer is formed by a chemical vapor deposition method.
- the plurality of strip-shaped barrier oxide layers have a set width.
- the impedance is a polysilicon layer, an active injection layer or an active well layer.
- the resistive component is a non-metal polysilicon resistive component, a non-metal silicide active implanted region resistive component, or a non-metal silicide active well resistive component.
- the resistance element is a P+ type polysilicon resistance element, an N+ type polysilicon resistance element, and a P+ type expansion Dispersion resistance element, N+ type diffusion resistance element, high resistance polysilicon resistance element or well area resistance element.
- a semiconductor resistor element having a high resistivity and a method of manufacturing the same according to the present invention wherein a plurality of strip-shaped barrier oxide layers having a certain interval are formed on a surface of a polysilicon layer, and an interface resistance is generated between the metal silicide and the barrier oxide layer.
- a plurality of increased interfacial resistances are formed on the semiconductor resistive element processed in the above steps, thereby increasing the resistivity of the semiconductor resistive element, which does not require a process change, does not require additional etching, and can reduce the size of the semiconductor resistive element, thereby reducing Production costs, time savings, increased production efficiency and reduced negative impact on the yield of semiconductor components.
- Figure 1 is a cross-sectional view showing the structure of a prior art resistive element
- FIG. 2 is a top plan view showing the structure of a prior art resistive element
- Figure 3 is a cross-sectional view showing the structure of a resistive element according to a preferred embodiment of the present invention.
- FIG. 4 is a top plan view showing a construction of a preferred embodiment of the present invention. detailed description
- FIG. 3 is a cross-sectional view showing the structure of a resistive element according to a preferred embodiment of the present invention
- FIG. 4 is a top view showing the structure of a preferred embodiment of the present invention.
- a method of fabricating a semiconductor resistive element having a high resistivity according to the present invention comprises the steps of: forming a resistive layer 22 on a half of the conductive substrate 20, and then using a chemical vapor deposition (CVD) method in conjunction with a photolithography process
- a plurality of strip-shaped barrier oxide layers 24 spaced apart from each other as a self-aligned metal silicide are formed on the surface of the resistive layer 22, the thickness of which is determined by the process itself, and the plurality of strip-shaped barrier oxide layers 24 can be avoided.
- Metal silicide is formed between the above-described resistive layer 22 and the plurality of strip-shaped barrier oxide layers 24 during the formation of the subsequent self-aligned metal silicide.
- a self-aligned metal silicide process can then be performed to form a metal silicide layer 26 on the surface of the resistive layer 22 on both sides of the plurality of strip-shaped barrier oxide layers 24.
- the impedance layer 22 is a polysilicon layer, an active injection layer or an active well layer.
- the metal silicide layer 26 is formed by sputtering a metal layer on the surface of the polysilicon layer 22 and the plurality of strip-shaped barrier oxide layers 24; and performing the first high-temperature rapid heating (RTA).
- the metal layer is contacted with the surface of the polysilicon layer 22 covered by the unimpeded oxide layer 24 to generate a silicidation reaction and the self-aligned metal silicide 26; while the metal layer remaining after the reaction or reaction is not wet etching Selectively remove and perform a second high temperature A rapid heating process allows a stable self-aligned metal silicide 26 structure to be formed on the semiconductor substrate 20.
- an oxide layer 30 is deposited on the surface of the plurality of strip-shaped barrier oxide layers 24 and the metal silicide 26 by a chemical vapor deposition method, and only a portion of the metal silicide 26 is exposed to serve as the contact pad 28, and the contact pad 28 is used. Used to form an electrical connection with an external wire.
- the plurality of strip-shaped barrier oxide layers 24 have a set width.
- the spacing, the width and the slope of the plurality of strip-shaped barrier oxide layers 24 can be set according to actual needs to meet different resistance values, because the plurality of strip-shaped barrier oxide layers 24 are mutually There is a certain interval therebetween, so in the self-aligned germanium silicide process, only the metal silicide layer 26 is formed between the plurality of strip-shaped barrier oxide layers 24, when the resistive element is high resistivity, such as greater than ⁇ /m, an interface resistance is generated between the metal silicide 26 and the barrier oxide layer 24, so that an interface resistance is formed between each of the strip-shaped barrier oxide layer 24 and the metal silicide 26, that is, a plurality of interface resistances are generated. , thereby increasing the resistance of the number of the semiconductor elements and electrically ⁇ 1.
- the resistive element is a non-metallic polysilicon resistive component, a non-metal silicide active implanted region resistive component, or a non-metal silicide active well resistive component.
- the resistor element may be a P+ type polysilicon resistor element, an N+ type polysilicon resistor element, a P+ type diffusion resistance element, an N+ type diffusion resistance element, a high resistance polysilicon resistance element or a well area resistance element.
- the present invention further provides a semiconductor resistor element having a high resistivity, the structure comprising: a semiconductor substrate 20 having a resistive layer 22 formed thereon; a plurality of strip-shaped barrier oxide layers 24 formed on the surface of the resistive layer 22, wherein The plurality of strip-shaped barrier oxide layers 24 are spaced apart from each other; and a plurality of metal silicides 26 are formed on the surface of the resistive layer 22 on each of the plurality of strip-shaped barrier oxide layers 24 on both sides of the barrier oxide layer.
- the resistive layer 22 is a polysilicon layer, an active implant layer or an active well layer.
- the plurality of strip-shaped barrier oxide layers 24 have a set width. At the same time, the spacing, width and slope of the plurality of strip-shaped barrier oxide layers 24 can be set according to actual needs to meet different resistance values because the plurality of strip-shaped barrier oxide layers 24 are spaced apart from each other.
- the metal silicide layer 26 is formed between the plurality of strip-shaped barrier oxide layers 24, and when the resistive element has a high resistivity, such as greater than ⁇ /m, the metal An interface resistance is generated between the silicide 26 and the barrier oxide layer 24, so that an interface resistance is formed between each of the strip-shaped barrier oxide layer 24 and the metal silicide 26, that is, a plurality of interface resistances are generated, thereby increasing the The resistivity of the semiconductor resistive element.
- the resistive element is a non-metallic polysilicon resistive component, a non-metal silicide active implanted region resistive component, or a non-metal silicide active well region resistive component.
- the resistor element may further be a P+ type polysilicon resistance element, an N+ type polysilicon resistance element, a P+ type diffusion resistance element, an N+ type diffusion resistance element, a high resistance polysilicon resistance element or a well area resistance element.
- a semiconductor resistor element having a high resistivity and a method of manufacturing the same according to the present invention wherein a plurality of strip-shaped barrier oxide layers having a certain interval are formed on a surface of a polysilicon layer, and an interface resistance is generated between the metal silicide and the barrier oxide layer.
- a plurality of increased interfacial resistances are formed on the semiconductor resistive element processed in the above steps, thereby increasing the resistivity of the semiconductor resistive element, which does not require a process, and does not require additional etching while reducing the size of the semiconductor resistive element. Therefore, the production cost is reduced, the time is saved, the production efficiency is improved, and the negative impact on the yield of the semiconductor element is reduced.
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Abstract
Description
具有高电阻系数的半导体电阻元件及其制造方法 技术领域 Semiconductor resistance element having high resistivity and manufacturing method thereof
本发明涉及一种制造半导体电阻元件的技术， 且特别涉及一种具有高电阻系数的半导体 电且元件及其制造方法。 The present invention relates to a technique for fabricating a semiconductor resistor element, and more particularly to a semiconductor device having a high resistivity and an element and a method of fabricating the same.
背景技术 Background technique
目前， 所说的多晶硅（Polysilicon ), 就是一种由多种不同结晶方向的小单晶硅晶粒所组 成的纯硅物质， 其中乡晶硅内的每个单晶晶粒之间由晶粒界面（Grain Boundary )所隔开。 且 因晶粒界面内含有各种的线缺陷及点缺陷， 这使得掺质原于经过这些晶粒界面而进行的扩散 能力将比经由晶粒内部的还要快。 At present, the polysilicon is a pure silicon material composed of small single crystal silicon grains of different crystal orientations, wherein each single crystal grain in the mother crystal silicon is composed of crystal grains. The interface (Grain Boundary) is separated. And because the grain interface contains various line defects and point defects, the diffusion ability of the dopants through these grain boundaries will be faster than that through the inside of the grains.
基于上述的因素， 可以对多晶硅进行掺杂， 以改变其电性并获得符合制程条件的多晶硅 材质； 换言之， 固态电子元件的制作， 通常通过掺杂不同性质和浓度的掺质， 来调整多晶硅 材料的特性， 再利用电性的变化特性， 来设计出具有不同功能性的电子元件。 因此， 利用多 晶硅本身具有很高的电阻率， 可以作为 IC设计上所需要的电阻元件。 Based on the above factors, the polysilicon may be doped to change its electrical properties and obtain a polysilicon material that meets the processing conditions; in other words, the fabrication of solid electronic components is usually performed by doping dopants of different properties and concentrations to adjust the polysilicon material. The characteristics of the electrical characteristics are used to design electronic components with different functionalities. Therefore, the use of polycrystalline silicon itself has a high electrical resistivity and can be used as a resistive element for IC design.
当多晶硅作为电阻元件时， 如图 1和图 2所示， 图 1所示为现有技术的电阻元件的构造 剖视图， 图 2所示为现有技术的电阻元件的构造俯视图。该电阻元件在基底 10上形成一层多 晶硅层 12, 其多晶硅层 12两端可形成具有接触垫 18的自对准金属硅化物（ salicide ) 16， 用 于与外部导线连接。 由于电阻元件 '本身必须为非金属硅化物（non-salicide ), 所以在多晶硅层 12表面上覆盖有一阻碍氧化层 14,以防止在多晶硅层 12和阻碍氧化层 14之间形成金属硅化 物 16。 当电阻元件为高电阻系数时， 如大于 Ι Ω/m, 金属硅化物 16与因阻碍氧化层 14所产 生的非金属硅化物区域的之间的边界会产生一界面电阻（ interface resistance ), 界面电阻的产 生增加了多晶硅电阻元件的电阻系数，但因为界面电阻只能在金属硅化物 16和非金属珪化物 区域之间的边界产生， 现有电阻元件的构造所产生的界面电阻数量很少， 因此并不能使得多 晶硅电阻元件的电阻系数获得较大的增加。 When polycrystalline silicon is used as the resistive element, as shown in Figs. 1 and 2, Fig. 1 is a cross-sectional view showing the structure of a prior art resistive element, and Fig. 2 is a top plan view showing the structure of the prior art resistive element. The resistive element forms a layer of polycrystalline silicon 12 on the substrate 10, and a poly-seal layer 12 is formed at both ends thereof to form a salicide 16 having contact pads 18 for connection to external leads. Since the resistive element 'must be non-salicide, the surface of the polysilicon layer 12 is covered with a barrier oxide layer 14 to prevent the formation of the metal silicide 16 between the polysilicon layer 12 and the barrier oxide layer 14. When the resistive element has a high resistivity, such as greater than Ι Ω/m, an interface resistance is generated between the metal silicide 16 and the non-metal silicide region caused by the oxide layer 14 being blocked, the interface The generation of the resistance increases the resistivity of the polysilicon resistor element, but since the interface resistance can only be generated at the boundary between the metal silicide 16 and the non-metal germanide region, the configuration of the existing resistor element produces a small amount of interface resistance. Therefore, a large increase in the resistivity of the polysilicon resistor element cannot be obtained.
高压集成电路产品中常常要用到高阻值的电阻元件， 并且将其直接集成在集成电路的内 部， 以减小芯片的几何尺寸， 如超低功率装置需要电阻元件具有较大的电阻系数时， 通常情 况下这需要针对半导体进行额外的刻蚀工序， 例如用掺杂或者不掺杂的多晶硅作为高阻元件' 的材料， 称之为高阻多晶硅， 然而因为需要增加刻蚀和注入的工序不仅增加了成本， 浪费时 间， 影响效率而且对半导体元件的成品率带来负面影响。 发明内容 High-voltage integrated circuit products often use high-resistance resistive components and integrate them directly inside the integrated circuit to reduce the chip's geometry. For example, when ultra-low-power devices require resistive components with large resistivity. Usually, this requires an additional etching process for the semiconductor, such as doping or undoped polysilicon as the material of the high-resistance element, called high-resistance polysilicon, but because of the need to increase the etching and implantation process Not only does it increase costs, it wastes time, affects efficiency, and has a negative impact on the yield of semiconductor components. Summary of the invention
本发明的目的是提供一种具有高电阻系数的半导体电阻元件及其制造方法， 其不需要工 序改变， 不需要额外刻蚀同时能够减小半导体电阻元件的尺寸。 SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor resistor element having a high resistivity and a method of manufacturing the same, which does not require a process change, does not require additional etching, and can reduce the size of the semiconductor resistor element.
为了实现上述目的， 本发明提出一种具有高电阻系数的半导体电阻元件的制造方法， 其 包括下列步骤： 在一半导体基底上形成有一阻抗层； 在上述阻抗层表面形成多个彼此具有一 定间隔的条状阻碍氧化层； 在上述多个条状阻碍氧化层中每一个条状阻碍氧化层两侧的 f且抗 层表面形成金属硅化物层。 In order to achieve the above object, the present invention provides a method of fabricating a semiconductor resistive element having a high resistivity, comprising the steps of: forming a resistive layer on a semiconductor substrate; forming a plurality of spaced apart regions on the surface of the resistive layer a strip-shaped barrier oxide layer; each of the plurality of strip-shaped barrier oxide layers blocks f on both sides of the oxide layer and forms a metal silicide layer on the surface of the resist layer.
进一步的， 其中上述制造方法更包括形成一氧化层， 覆盖在上述多个条状阻碍氧化层与 上述金属硅化物层的表面， 仅露出部分上述金属硅化物以作为接触垫。 Further, the manufacturing method further includes forming an oxide layer covering the surface of the plurality of strip-shaped barrier oxide layers and the metal silicide layer, and exposing only a portion of the metal silicide as a contact pad.
进一步的， 其申上述氧化层是利用化学气相沉积方法形成的。 Further, it is claimed that the above oxide layer is formed by a chemical vapor deposition method.
进一步的， 其中上述多个条状阻碍氧化层具有一设定宽度。 Further, wherein the plurality of strip-shaped barrier oxide layers have a set width.
进一步的， 其中上述阻抗层为多晶硅层， 有源注入层或有源井层„ Further, wherein the impedance layer is a polysilicon layer, an active injection layer or an active well layer
进一步的， 其中上述电阻元件为非金属多晶硅电阻元件， 非金属硅化物有源注入区电阻 元件， 或非金属硅化物有源井区电阻元件。 Further, the resistive component is a non-metal polysilicon resistive component, a non-metal silicide active implanted region resistive component, or a non-metal silicide active well resistive component.
进一步的， 其中上述电阻元件为 P+型多晶硅电阻元件， N+型多晶硅电阻元件， P+型扩 散电阻元件， N+型扩散电阻元件， 高阻多晶硅电阻元件或井区电阻元件。 Further, the resistive element is a P+ type polysilicon resistance element, an N+ type polysilicon resistance element, a P+ type diffusion resistance element, an N+ type diffusion resistance element, a high resistance polysilicon resistance element or a well area resistance element.
为了实现上述目的， 本发明更提出一种具有高电阻系数的半导体电阻元件， 其特征在于 其结构包括： 一半导体基底， 其上形成有一阻抗层； 多个条状阻碍氧化层， 形成于上述阻抗 层表面， 其中上述多个条状阻碍氧化层之间具有一定间隔； 多个金属硅化物， 形成于上述多 个条 阻碍氧化层中每一个条状阻碍氧化层两侧的阻抗层表面。 In order to achieve the above object, the present invention further provides a semiconductor resistor element having a high resistivity, characterized in that the structure comprises: a semiconductor substrate having a resistive layer formed thereon; a plurality of strip-shaped barrier oxide layers formed on the impedance a surface of the layer, wherein the plurality of strip-shaped barrier oxide layers have a certain interval; and a plurality of metal silicides are formed on the surface of the resistive layer on each of the plurality of strip-blocking oxide layers on both sides of the barrier layer.
进一步的， 其中上述半导体电阻元件更包括一氧化层， 覆盖在上述多个条状阻碍氧化层 与上述金属硅化物层的表面， 仅露出部分上迷金属硅化物以作为接触垫。 Further, the semiconductor resistor element further includes an oxide layer covering the surface of the plurality of strip-shaped barrier oxide layers and the metal silicide layer, and only a portion of the metal silicide is exposed as a contact pad.
进一步的， 其中上述氧化层是利用化学气相沉积方法形成的。 Further, wherein the above oxide layer is formed by a chemical vapor deposition method.
进一步的， 其中上述多个条状阻碍氧化层具有一设定宽度。 Further, wherein the plurality of strip-shaped barrier oxide layers have a set width.
进一步^， 其中上述阻抗 为多晶硅层， 有源注入层或有源井层。 Further, wherein the impedance is a polysilicon layer, an active injection layer or an active well layer.
进一步的， 其中上述电阻元件为非金属多晶硅电阻元件， 非金属硅化物有源注入区电阻 元件， 或非金属硅化物有源井区电阻元件。 Further, the resistive component is a non-metal polysilicon resistive component, a non-metal silicide active implanted region resistive component, or a non-metal silicide active well resistive component.
进一步的， 其中上述电阻元件为 P+型多晶硅电阻元件， N+型多晶硅电阻元件， P+型扩 散电阻元件， N+型扩散电阻元件， 高阻多晶硅电阻元件或井区电阻元件。 Further, wherein the resistance element is a P+ type polysilicon resistance element, an N+ type polysilicon resistance element, and a P+ type expansion Dispersion resistance element, N+ type diffusion resistance element, high resistance polysilicon resistance element or well area resistance element.
本发明的具有高电阻系数的半导体电阻元件及其制造方法， 在多晶硅层表面形成多个具 有一定间隔的条状阻碍氧化层， 由于金属硅化物与阻碍氧化层之间会产生一界面电阻， 经过 上述步骤处理过后的半导体电阻元件上形成了多个增加的界面电阻， 如此提高了半导体电阻 元件电阻系数， 其不需要工序改变， 不需要额外刻蚀同时能够减小半导体电阻元件的尺寸， 因此降低了生产成本， 节省了时间， 提高了生产效率而且降低了对半导体元件的成品率带来 的负面影响。 附图说明 A semiconductor resistor element having a high resistivity and a method of manufacturing the same according to the present invention, wherein a plurality of strip-shaped barrier oxide layers having a certain interval are formed on a surface of a polysilicon layer, and an interface resistance is generated between the metal silicide and the barrier oxide layer. A plurality of increased interfacial resistances are formed on the semiconductor resistive element processed in the above steps, thereby increasing the resistivity of the semiconductor resistive element, which does not require a process change, does not require additional etching, and can reduce the size of the semiconductor resistive element, thereby reducing Production costs, time savings, increased production efficiency and reduced negative impact on the yield of semiconductor components. DRAWINGS
图 1所示^现有技术的电阻元件的构造剖视图； Figure 1 is a cross-sectional view showing the structure of a prior art resistive element;
图 2所示为现有技术的电阻元件的构造俯视图； 2 is a top plan view showing the structure of a prior art resistive element;
图 3所示为本发明一较佳实施例的电阻元件的构造剖视图； Figure 3 is a cross-sectional view showing the structure of a resistive element according to a preferred embodiment of the present invention;
图 4所示为本发明一较佳实施例的构造俯视图。 具体实施方式 4 is a top plan view showing a construction of a preferred embodiment of the present invention. detailed description
为了更了解本发明的技术内容， 特举较佳具体实施例并配合所附图式说明如下。 In order to better understand the technical content of the present invention, the preferred embodiments are described below in conjunction with the accompanying drawings.
请参考图 3和图 4, 图 3所示为本发明一较佳实施例的电阻元件的构造剖视图， 图 4所 示为本发明一较佳实施例的构造俯视图。 本发明的具有高电阻系数的半导体电阻元件的制造 方法， 其包括下列步骤： 在一半导休基底 20上先形成有一阻抗层 22， 而后再利用化学气相 沉积（ CVD )方法配合微影刻蚀制程， 在上述阻抗层 22表面形成作为自对准金属硅化物阻碍 的多个彼此具有一定间隔的条状阻碍氧化层 24， 其厚度由制程本身来决定， 上述多个条状阻 碍氧化层 24可避免在后续的自对准金属硅化物的形成过程中在上述阻抗层 22和上述多个条 状阻碍氧化层 24之间产生金属硅化物。 随后即可进行自对准金属硅化物制程，在上述多个条 状阻碍氧化层 24两侧的阻抗层 22表面形成金属硅化物层 26。 3 and FIG. 4, FIG. 3 is a cross-sectional view showing the structure of a resistive element according to a preferred embodiment of the present invention, and FIG. 4 is a top view showing the structure of a preferred embodiment of the present invention. A method of fabricating a semiconductor resistive element having a high resistivity according to the present invention comprises the steps of: forming a resistive layer 22 on a half of the conductive substrate 20, and then using a chemical vapor deposition (CVD) method in conjunction with a photolithography process A plurality of strip-shaped barrier oxide layers 24 spaced apart from each other as a self-aligned metal silicide are formed on the surface of the resistive layer 22, the thickness of which is determined by the process itself, and the plurality of strip-shaped barrier oxide layers 24 can be avoided. Metal silicide is formed between the above-described resistive layer 22 and the plurality of strip-shaped barrier oxide layers 24 during the formation of the subsequent self-aligned metal silicide. A self-aligned metal silicide process can then be performed to form a metal silicide layer 26 on the surface of the resistive layer 22 on both sides of the plurality of strip-shaped barrier oxide layers 24.
根据本发明一较佳实施例， 其中上述阻抗层 22为多晶硅层， 有源注入层或有源井层。 以 多晶硅层为例， 上述金属硅化物层 26的形成过程为在多晶硅层 22与上述多个条状阻碍氧化 层 24表面先溅镀形成一金属层； 再进行第一次高温快速加热（RTA )制程， 使金属层与未被 阻碍氧化层 24覆盖的多晶硅层 22表面相接触产生硅化反应而自对准形 金属硅化物 26; 而 未参与反应或反应后剩余的金属层将以湿蚀刻的方式选择性地加以去除， 并进行第二次高温 快速加热制程， 如此即可在半导体基底 20上形成稳定的自对准金属硅化物 26结构。 最后， 利用化学气相沉积方法在上述多个条状阻碍氧化层 24与金属硅化物 26的表面沉积一氧化层 30,仅露出部分上述金属硅化物 26以作为接触垫 28之用， 此接触垫 28用以与外部导线形成 电性连接。 According to a preferred embodiment of the present invention, the impedance layer 22 is a polysilicon layer, an active injection layer or an active well layer. Taking the polysilicon layer as an example, the metal silicide layer 26 is formed by sputtering a metal layer on the surface of the polysilicon layer 22 and the plurality of strip-shaped barrier oxide layers 24; and performing the first high-temperature rapid heating (RTA). The process, the metal layer is contacted with the surface of the polysilicon layer 22 covered by the unimpeded oxide layer 24 to generate a silicidation reaction and the self-aligned metal silicide 26; while the metal layer remaining after the reaction or reaction is not wet etching Selectively remove and perform a second high temperature A rapid heating process allows a stable self-aligned metal silicide 26 structure to be formed on the semiconductor substrate 20. Finally, an oxide layer 30 is deposited on the surface of the plurality of strip-shaped barrier oxide layers 24 and the metal silicide 26 by a chemical vapor deposition method, and only a portion of the metal silicide 26 is exposed to serve as the contact pad 28, and the contact pad 28 is used. Used to form an electrical connection with an external wire.
根据本发明一较佳实施例， 其中上述多个条状阻碍氧化层 24具有一设定宽度。 同时上述 图案化的多个条状阻碍氧化层 24的间隔， 宽度以及斜度都可以按照实际需要进行设定， 以满 足不同的电阻值的要求， 因为上述多个条状阻碍氧化层 24彼此之间具有一定间隔， 因此在进 行自对准佥属硅化物制程中， 只会在上述多个条状阻碍氧化层 24之间形成金属硅化物层 26, 当电阻元件为高电阻系数时， 如大于 ΙΚΩ/m, 金属硅化物 26与阻碍氧化层 24之间会产生一 界面电阻， 如此就会在每一个条状阻碍氧化层 24和金属硅化物 26之间形成界面电阻， 即产 生多个界面电阻， 从而增加了该半导体电 ί1且元件的电阻 数。 According to a preferred embodiment of the present invention, the plurality of strip-shaped barrier oxide layers 24 have a set width. At the same time, the spacing, the width and the slope of the plurality of strip-shaped barrier oxide layers 24 can be set according to actual needs to meet different resistance values, because the plurality of strip-shaped barrier oxide layers 24 are mutually There is a certain interval therebetween, so in the self-aligned germanium silicide process, only the metal silicide layer 26 is formed between the plurality of strip-shaped barrier oxide layers 24, when the resistive element is high resistivity, such as greater than ΙΚΩ/m, an interface resistance is generated between the metal silicide 26 and the barrier oxide layer 24, so that an interface resistance is formed between each of the strip-shaped barrier oxide layer 24 and the metal silicide 26, that is, a plurality of interface resistances are generated. , thereby increasing the resistance of the number of the semiconductor elements and electrically ί 1.
根据本发明一较佳实施例， 其中上述电阻元件为非金属多晶硅电阻元件， 非金属硅化物 有源注入区电阻元件， 或非金属硅化物有源井区电阻元件。 其中上述电阻元件更可为 P+型多 晶硅电阻元件， N+型多晶硅电阻元件， P+型扩散电阻元件， N+型扩散电阻元件， 高阻多晶 硅电阻元件或井区电阻元件。 According to a preferred embodiment of the present invention, the resistive element is a non-metallic polysilicon resistive component, a non-metal silicide active implanted region resistive component, or a non-metal silicide active well resistive component. The resistor element may be a P+ type polysilicon resistor element, an N+ type polysilicon resistor element, a P+ type diffusion resistance element, an N+ type diffusion resistance element, a high resistance polysilicon resistance element or a well area resistance element.
本发明更提出一种具有高电阻系数的半导体电阻元件， 其结构包括： 一半导体基底 20, 其上形成有一阻抗层 22; 多个条状阻碍氧化层 24, 形成于上述阻抗层 22表面， 其中上述多 个条状阻碍氧化层 24之间具有一定间隔； 多个金属硅化物 26， 形成于上述多个条状阻碍氧 化层 24中每一个条状阻碍氧化层两侧的阻抗层 22表面。 The present invention further provides a semiconductor resistor element having a high resistivity, the structure comprising: a semiconductor substrate 20 having a resistive layer 22 formed thereon; a plurality of strip-shaped barrier oxide layers 24 formed on the surface of the resistive layer 22, wherein The plurality of strip-shaped barrier oxide layers 24 are spaced apart from each other; and a plurality of metal silicides 26 are formed on the surface of the resistive layer 22 on each of the plurality of strip-shaped barrier oxide layers 24 on both sides of the barrier oxide layer.
另有一利用化学气相沉积（CVD )方法所形成的氧化层 30， 其覆盖于上述多个条状阻碍 氧化层 24与金属硅化物 26的表面， 仅露出部分该金属硅化物 26以作为接触垫 28之用。 根 据本发明一较佳实施例， 其中上述阻抗层 22为多晶硅层， 有源注入层或有源井层。 Another oxide layer 30 formed by a chemical vapor deposition (CVD) method covers the surface of the plurality of strip-shaped barrier oxide layers 24 and the metal silicide 26, and only a portion of the metal silicide 26 is exposed to serve as the contact pad 28. Use. According to a preferred embodiment of the present invention, the resistive layer 22 is a polysilicon layer, an active implant layer or an active well layer.
上述多个条状阻碍氧化层 24具有一设定宽度。同时上述多个条状阻碍氧化层 24的间隔， 宽度以及斜度都可以按照实际需要进行设定， 以满足不同的电阻值的要求 因为上述多个条 状阻碍氧化层 24彼此之间具有一定间隔， 因此在进行自对准金属硅化物制程中， 只会在上述 多个条状阻碍氧化层 24之间形成金属硅化物层 26， 当电阻元件为高电阻系数时， 如大于 ΙΚΩ/m, 金属硅化物 26与阻碍氧化层 24之间会产生一界面电阻， 如此就会在每一个条状阻 碍氧化层 24和金属硅化物 26之间形成界面电阻， 即产生多个界面电阻， 从而增加了该半导 体电阻元件的电阻系数。 上述电阻元件为非金属多晶硅电阻元件， 非金属硅化物有源注入区电阻元件， 或非金属 硅化物有源井区电阻元件。 其中上述电阻元件更可为 P+型多晶硅电阻元件， N+型多晶硅电 阻元件， P+型扩散电阻元件， N+型扩散电阻元件， 高阻多晶硅电阻元件或井区电阻元件。 The plurality of strip-shaped barrier oxide layers 24 have a set width. At the same time, the spacing, width and slope of the plurality of strip-shaped barrier oxide layers 24 can be set according to actual needs to meet different resistance values because the plurality of strip-shaped barrier oxide layers 24 are spaced apart from each other. Therefore, in the self-aligned metal silicide process, only the metal silicide layer 26 is formed between the plurality of strip-shaped barrier oxide layers 24, and when the resistive element has a high resistivity, such as greater than ΙΚΩ/m, the metal An interface resistance is generated between the silicide 26 and the barrier oxide layer 24, so that an interface resistance is formed between each of the strip-shaped barrier oxide layer 24 and the metal silicide 26, that is, a plurality of interface resistances are generated, thereby increasing the The resistivity of the semiconductor resistive element. The resistive element is a non-metallic polysilicon resistive component, a non-metal silicide active implanted region resistive component, or a non-metal silicide active well region resistive component. The resistor element may further be a P+ type polysilicon resistance element, an N+ type polysilicon resistance element, a P+ type diffusion resistance element, an N+ type diffusion resistance element, a high resistance polysilicon resistance element or a well area resistance element.
本发明的具有高电阻系数的半导体电阻元件及其制造方法， 在多晶硅层表面形成多个具 有一定间隔的条状阻碍氧化层， 由于金属硅化物与阻碍氧化层之间会产生一界面电阻， 经过 上述步骤处理过后的半导体电阻元件上形成了多个增加的界面电阻， 如此提高了半导体电阻 元件电阻系数， 其不需要工序?文变， 不需要额外刻蚀同时能够减小半导体电阻元件的尺寸， 因此降低了生产成本， 节省了时间， 提高了生产效率而且降低了对半导体元件的成品率带来 的负面影响。 A semiconductor resistor element having a high resistivity and a method of manufacturing the same according to the present invention, wherein a plurality of strip-shaped barrier oxide layers having a certain interval are formed on a surface of a polysilicon layer, and an interface resistance is generated between the metal silicide and the barrier oxide layer. A plurality of increased interfacial resistances are formed on the semiconductor resistive element processed in the above steps, thereby increasing the resistivity of the semiconductor resistive element, which does not require a process, and does not require additional etching while reducing the size of the semiconductor resistive element. Therefore, the production cost is reduced, the time is saved, the production efficiency is improved, and the negative impact on the yield of the semiconductor element is reduced.
虽然本发明已以较佳实施例揭露如上， 然其并非用以限定本发明。 本发明所属技术领域 中具有通常知识者， 在不脱离本发明的精神和范围内， 当可作各种的更动与润饰。 因此， 本 发明的保护范围当视权利要求书所界定者为准。 Although the present invention has been disclosed above in the preferred embodiments, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
Claims
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5362662A (en) * | 1989-08-11 | 1994-11-08 | Ricoh Company, Ltd. | Method for producing semiconductor memory device having a planar cell structure |
| CN1146072A (en) * | 1995-06-30 | 1997-03-26 | 现代电子产业株式会社 | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5362662A (en) * | 1989-08-11 | 1994-11-08 | Ricoh Company, Ltd. | Method for producing semiconductor memory device having a planar cell structure |
| CN1146072A (en) * | 1995-06-30 | 1997-03-26 | 现代电子产业株式会社 | Method for manufacturing semiconductor device |
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