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WO2010078343A3 - Procédé de formation des motifs à doublage de pas d'éléments de resist et d'espaceurs amovibles pour structures de pilier - Google Patents

Procédé de formation des motifs à doublage de pas d'éléments de resist et d'espaceurs amovibles pour structures de pilier Download PDF

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Publication number
WO2010078343A3
WO2010078343A3 PCT/US2009/069711 US2009069711W WO2010078343A3 WO 2010078343 A3 WO2010078343 A3 WO 2010078343A3 US 2009069711 W US2009069711 W US 2009069711W WO 2010078343 A3 WO2010078343 A3 WO 2010078343A3
Authority
WO
WIPO (PCT)
Prior art keywords
feature
patterning method
pillar structures
removable spacer
resist feature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2009/069711
Other languages
English (en)
Other versions
WO2010078343A2 (fr
Inventor
Yung-Tin Chen
Steven J. Radigan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk 3D LLC
Original Assignee
SanDisk 3D LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SanDisk 3D LLC filed Critical SanDisk 3D LLC
Priority to JP2011543713A priority Critical patent/JP5695575B2/ja
Priority to EP09799471.9A priority patent/EP2380189B8/fr
Priority to CN200980153246.XA priority patent/CN102272888B/zh
Publication of WO2010078343A2 publication Critical patent/WO2010078343A2/fr
Publication of WO2010078343A3 publication Critical patent/WO2010078343A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/068—Shaping switching materials by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10P76/2041—
    • H10P76/4085—
    • H10P76/4088—

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Inorganic Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

L'invention porte sur un procédé de fabrication d'un dispositif à semi-conducteurs qui comprend la formation d'au moins une couche sur un substrat, la formation d'au moins deux éléments de matériau sensible espacés l'un de l'autre sur l'au moins une couche, la formation d'espaceurs de paroi latérale sur les au moins deux éléments et le remplissage d'un espace compris entre un premier espaceur de paroi latérale sur un premier élément et un second espaceur de paroi latérale sur un second élément avec un élément de remplissage. Le procédé comprend également l'élimination sélective des espaceurs de paroi latérale pour laisser le premier élément, l'élément de remplissage et le second élément espacés l'un de l'autre, et la gravure de l'au moins une couche en utilisant le premier élément, l'élément de remplissage et le second élément en tant que masque.
PCT/US2009/069711 2008-12-31 2009-12-29 Procédé de formation des motifs à doublage de pas d'éléments de resist et d'espaceurs amovibles pour structures de pilier Ceased WO2010078343A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2011543713A JP5695575B2 (ja) 2008-12-31 2009-12-29 柱状構造のためのレジストフィーチャおよび除去可能スペーサピッチを倍増するパターニング法
EP09799471.9A EP2380189B8 (fr) 2008-12-31 2009-12-29 Procédé de formation des motifs à doublage de pas d'éléments de resist et d'espaceurs amovibles pour structures de pilier
CN200980153246.XA CN102272888B (zh) 2008-12-31 2009-12-29 柱形结构的阻剂结构元件和可移除间隔物间距加倍构图方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/318,609 2008-12-31
US12/318,609 US8084347B2 (en) 2008-12-31 2008-12-31 Resist feature and removable spacer pitch doubling patterning method for pillar structures

Publications (2)

Publication Number Publication Date
WO2010078343A2 WO2010078343A2 (fr) 2010-07-08
WO2010078343A3 true WO2010078343A3 (fr) 2010-09-10

Family

ID=42235718

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/069711 Ceased WO2010078343A2 (fr) 2008-12-31 2009-12-29 Procédé de formation des motifs à doublage de pas d'éléments de resist et d'espaceurs amovibles pour structures de pilier

Country Status (7)

Country Link
US (3) US8084347B2 (fr)
EP (1) EP2380189B8 (fr)
JP (1) JP5695575B2 (fr)
KR (1) KR101625892B1 (fr)
CN (1) CN102272888B (fr)
TW (1) TW201034051A (fr)
WO (1) WO2010078343A2 (fr)

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US8114765B2 (en) 2008-12-31 2012-02-14 Sandisk 3D Llc Methods for increased array feature density
US8084347B2 (en) 2008-12-31 2011-12-27 Sandisk 3D Llc Resist feature and removable spacer pitch doubling patterning method for pillar structures
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US8889559B2 (en) * 2012-12-12 2014-11-18 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8999852B2 (en) 2012-12-12 2015-04-07 Micron Technology, Inc. Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice pattern from an oblique lattice pattern, and methods of forming a pattern on a substrate
US8889558B2 (en) * 2012-12-12 2014-11-18 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8937018B2 (en) 2013-03-06 2015-01-20 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8815718B1 (en) * 2013-06-28 2014-08-26 International Business Machines Corporation Vertical surround gate formation compatible with CMOS integration
KR102212556B1 (ko) 2014-10-08 2021-02-08 삼성전자주식회사 반도체 장치
US10026609B2 (en) * 2014-10-23 2018-07-17 Board Of Regents, The University Of Texas System Nanoshape patterning techniques that allow high-speed and low-cost fabrication of nanoshape structures
KR102325201B1 (ko) 2015-04-22 2021-11-11 삼성전자주식회사 반도체 소자의 제조 방법
KR102359371B1 (ko) * 2015-12-23 2022-02-09 에스케이하이닉스 주식회사 벌집 형태로 배열된 패턴들 형성 방법
US9978563B2 (en) * 2016-01-27 2018-05-22 Tokyo Electron Limited Plasma treatment method to meet line edge roughness and other integration objectives
KR102463922B1 (ko) * 2016-03-21 2022-11-08 에스케이하이닉스 주식회사 미세 패턴 형성 방법
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Also Published As

Publication number Publication date
JP5695575B2 (ja) 2015-04-08
JP2012514339A (ja) 2012-06-21
US20130130467A1 (en) 2013-05-23
KR101625892B1 (ko) 2016-05-31
KR20110117069A (ko) 2011-10-26
US20100167520A1 (en) 2010-07-01
US8084347B2 (en) 2011-12-27
EP2380189A2 (fr) 2011-10-26
US20120094478A1 (en) 2012-04-19
CN102272888B (zh) 2014-05-28
TW201034051A (en) 2010-09-16
EP2380189B8 (fr) 2014-07-09
EP2380189B1 (fr) 2014-04-09
WO2010078343A2 (fr) 2010-07-08
US8357606B2 (en) 2013-01-22
US8637389B2 (en) 2014-01-28
CN102272888A (zh) 2011-12-07

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