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WO2009104668A1 - Tableau de connexions et dispositif semi-conducteur - Google Patents

Tableau de connexions et dispositif semi-conducteur Download PDF

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Publication number
WO2009104668A1
WO2009104668A1 PCT/JP2009/052862 JP2009052862W WO2009104668A1 WO 2009104668 A1 WO2009104668 A1 WO 2009104668A1 JP 2009052862 W JP2009052862 W JP 2009052862W WO 2009104668 A1 WO2009104668 A1 WO 2009104668A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring board
resin
insulating layer
pad
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2009/052862
Other languages
English (en)
Japanese (ja)
Inventor
朝夫 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2009554362A priority Critical patent/JP5515744B2/ja
Publication of WO2009104668A1 publication Critical patent/WO2009104668A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H10W90/701—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0133—Elastomeric or compliant polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H10W72/07251—
    • H10W72/20—
    • H10W72/29—
    • H10W72/983—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention is based on the priority claim of Japanese Patent Application No. 2008-040335 (filed on Feb. 21, 2008), the entire contents of which are incorporated herein by reference. Shall.
  • the present invention relates to a wiring board and a semiconductor device for mounting a semiconductor package or a semiconductor chip, and more particularly to a wiring board and a semiconductor device suitable for flip chip connection, CSP (Chip Scale Package) connection, and the like.
  • LSI Large Scale Integration
  • connection method used to package this LSI chip is also increased in number of pins. Shifting from wire bonding to flip chip connection to support high-speed signals.
  • the flip chip connection is suitable for increasing the number of pins because an electrode can be provided on the wiring side surface of the LSI chip. Further, the flip-chip connection does not require a lead wire as compared with a connection method such as wire bonding or tape automated bonding, so that the wiring length can be shortened.
  • the bump 130 formed on the electrode 121 of the LSI chip 120 and the mounting pad 112 formed on the wiring substrate 110 are firmly bonded, and then the LSI chip 120 is formed by the underfill resin 140.
  • a method of sealing between the wiring board 110 and the wiring board 110 is widely used (see FIG. 6).
  • Au, solder, or the like is used as a general bump material used for flip chip connection. Examples of solder materials include Sn—Pb eutectic solder, and other examples include Sn—Pb (excluding eutectic), Sn—Ag, Sn—Cu, Sn—Sb, Sn—Zn, Sn.
  • a conductive resin bump is used (see Patent Document 1), or a ball bump in which the metal layer 130 is applied around the resin core 131 is formed with a conductive adhesive. There exists what was joined (refer patent document 2; refer FIG. 7).
  • the possibility of improving the connection reliability is increased by sealing the gap between the LSI chip and the wiring board with an underfill resin for the purpose of relaxing the stress applied to the solder bumps.
  • the elastic modulus of the solder bump is much higher than that of the underfill resin.
  • the elastic modulus of the Sn-3AG-0.5Cu solder is about 40 GPa
  • the elastic modulus of the underfill resin is a filler.
  • the elastic modulus is increased by mixing, it is about 10 GPa. For this reason, stress is still concentrated on the solder bump having a high elastic modulus, and there is a risk that cracks may occur in the LSI circuit in the solder bump itself or in the LSI chip near the solder bump due to repeated temperature changes.
  • a protruding resin is formed on a conductive pad of a printed wiring board, and a metal thin film is formed on the surface of the resin. It is conceivable that the LSI chip and the wiring board are flip-chip connected via solder bumps using the electrode pad portion coated with the. In this case, although the stress applied to the solder bump is relieved by the presence of the resin, the conductive pad itself is fixed on the high-elasticity printed wiring board, so that there is a limit to obtaining a sufficient effect.
  • flip-chip connection is a structure suitable for high performance, so it is expected that demand will increase in the future.
  • problems such as cost reduction and mounting process reduction Remains.
  • the main problem of the present invention is to provide a wiring board and a semiconductor device capable of ensuring high reliability of a bump connection part in flip chip connection, CSP connection, or the like.
  • a wiring board for mounting a semiconductor package or a semiconductor chip wherein the insulating layer has a recess at a predetermined position, and is embedded in the recess, and more than the insulating layer.
  • a low-elasticity low-elasticity resin, and a pad disposed on the low-elasticity resin and having a region smaller than the region of the low-elasticity resin are provided.
  • the wiring board, a semiconductor chip or a semiconductor package having an electrode at a position corresponding to the pad of the wiring board, and the pad and the electrode are disposed. And a bump for electrically connecting the pad and the electrode.
  • the flip chip or CSP As shown in the figure, when the electrodes of the semiconductor chip and the mounting pads of the wiring board face each other and are connected via bumps, even if there is a difference in the thermal expansion coefficient between the semiconductor chip and the wiring board, the connection part is on the low elastic resin As a result, the mounting pad can absorb the stress due to the difference in coefficient of linear expansion between the semiconductor chip and the wiring board. This stress relaxation effect is effective not only in preventing the destruction of the bumps but also in preventing the occurrence of cracks in the semiconductor chip and the wiring board.
  • FIG. 1A is a cross-sectional view taken along a line XX and FIG. 2B is a plan view schematically showing the configuration of a part of a wiring board according to a first embodiment of the present invention; It is sectional drawing which showed typically the structure of a part of semiconductor device which mounted the semiconductor chip in the wiring board based on Example 1 of this invention. It is process sectional drawing which showed typically the manufacturing method of the wiring board which concerns on Example 1 of this invention. It is the top view which showed the structure of a part of wiring board which concerns on Example 2 of this invention.
  • FIG. 6 is a cross-sectional view schematically showing a partial configuration of a semiconductor device according to Conventional Example 1.
  • FIG. 10 is a cross-sectional view schematically showing a partial configuration of a semiconductor device according to Conventional Example 2.
  • an insulating layer having a recess at a predetermined position (13 in FIG. 2), and embedded in the recess, is less elastic than the insulating layer (13 in FIG. 2).
  • 12 the following forms are also possible. It is preferable that a metal layer provided at least on the bottom surface of the recess is provided in the insulating layer. It is preferable to provide wiring formed on the insulating layer and the low-elasticity resin and connected to the pad.
  • An outer peripheral portion made of the same material as the pad is disposed on the insulating layer in the outer periphery of the low elastic resin region, and between the mounting pad and the outer peripheral portion in the low elastic resin region. And one or a plurality of connection portions that are made of the same material as the pad and connect the mounting pad and the outer peripheral portion. It is preferable to provide wiring formed on the insulating layer and connected to the outer peripheral portion.
  • the connecting portion is preferably formed in a straight line shape, a curved line shape, a diagonal line shape, or a combination thereof.
  • the semiconductor device includes a bump.
  • FIG. 1 is a perspective view schematically showing a partial configuration of a wiring board according to the first embodiment of the present invention.
  • 2A and 2B are a cross-sectional view taken along a line XX ′ and a plan view of FIG. 2B schematically showing a partial configuration of the wiring board according to the first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view schematically showing a partial configuration of the semiconductor device in which the semiconductor chip is mounted on the wiring board according to the first embodiment of the present invention.
  • a wiring layer (not shown) is formed in an insulating layer 13, and a mounting pad 12 and a wiring 12 a are formed at predetermined positions on the surface of the insulating layer 13. It is a multilayer wiring board.
  • the wiring board 10 is not limited to a printed wiring board, and can be applied to other wiring boards such as a ceramic board.
  • the wiring board 10 includes an insulating layer 13, a low elastic resin 11, a mounting pad 12, and a metal layer 14 as main components.
  • the insulating layer 13 has a wiring layer (not shown) and a metal layer 14 formed therein, and a mounting pad 12 and a wiring 12a are formed at predetermined positions on the surface.
  • the insulating layer 13 is formed with a bottomed hole (corresponding to 13a in FIG. 4B) in the layer between the metal layer 14 and the mounting pad 12, and has a lower elasticity than the insulating layer 13 in the hole.
  • An elastic resin 11 is embedded.
  • the hole in the insulating layer 13 is formed to be a larger area than the area of the mounting pad 12.
  • an epoxy resin for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide Resin, BCB (Benzocyclobutene), PBO (Polybenzoxazole), polynorbornene resin, and the like can be used.
  • the low elastic resin 11 is an insulating resin having a lower elasticity than the insulating layer 13, and is embedded in a hole (corresponding to 13a in FIG. 4B) formed in the insulating layer 13.
  • the low elastic resin 11 is an area larger than the area of the mounting pad 12.
  • a mounting pad 12 is formed in the region of the surface of the low elastic resin 11.
  • the low elastic resin 11 can be a resin whose elastic modulus is kept low in the apparatus operating temperature range.
  • a silicone resin, a composite resin obtained by adding a thermoplastic component to an epoxy resin, a low melt viscosity epoxy resin, or the like can be used. Can be used.
  • the mounting pad 12 is a pad for mounting the semiconductor chip 20 via the bump 30 and is joined to the bump 30 (see FIG. 3).
  • the mounting pad 12 is formed in the region of the surface of the low elastic resin 11. As a result, the joint between the mounting pad 12 and the bump 30 floats on the low-elasticity resin 11, and the stress due to the difference in linear expansion coefficient between the semiconductor chip 20 and the insulating layer 13 can be relaxed.
  • the mounting pad 12 has a wiring 12a drawn out from the outer periphery, and is configured integrally with the wiring 12a.
  • the wiring 12 a is formed on the insulating layer 13 and the low elastic resin 11.
  • the metal layer 14 is a layer made of metal formed in the insulating layer 13.
  • the metal layer 14 can be formed at the same time as a wiring layer (not shown) formed in the insulating layer 13, and the same material (for example, copper) as the wiring layer can be used.
  • the metal layer 14 serves as an etching stopper (laser stopper) when forming a hole (corresponding to 13a in FIG. 4B) for embedding the low-elasticity resin 11 in the insulating layer 13.
  • the semiconductor chip 20 is a semiconductor component such as an LSI chip and has an electrode 21 on the surface on the wiring board 10 side (see FIG. 3).
  • the electrode 21 is electrically connected to the mounting pad 12 via the bump 30 and is bonded to the bump 30.
  • a semiconductor package may be mounted on the wiring board 10 instead of the semiconductor chip 20.
  • the bumps 30 are conductive members that electrically connect the electrodes 21 of the semiconductor chip 20 and the mounting pads 12 of the wiring board 10 (see FIG. 3).
  • a general material used for flip chip connection can be used for the bump 30, and for example, Au, solder, or the like can be used.
  • FIG. 4 is a process cross-sectional view schematically showing the method for manufacturing a wiring board according to the first embodiment of the present invention.
  • a printed wiring board will be described as an example of the wiring board 10.
  • the wiring board 10 in which no wiring exists in the outermost layer is formed by a known printed wiring board forming method (step A1; see FIG. 4A).
  • a pattern of the metal layer 14 in a region larger than the region of the mounting pad 12 is formed in the insulating layer 13 around the position of the mounting pad (12 in FIG. 4D).
  • the metal layer 14 serves as a laser stopper that is necessary when forming a hole (13a in FIG. 4C) for embedding the low-elasticity resin (11 in FIG. 4C) in step A2.
  • the pattern of the metal layer 14 may be the same shape as the planar shape of the mounting pad (12 in FIG. 4D), and is not limited to a circle but may be various shapes such as a square shape. Further, the pattern of the metal layer 14 is made larger than the region of the hole 13a in consideration of the positional deviation at the time of laser drilling.
  • a hole 13a is formed by a laser (not shown) so as to be an area larger than the area of the mounting pad 12 around the position of the mounting pad (12 in FIG. 4D) (step A2; (See FIG. 4B).
  • a laser a carbon dioxide laser, an excimer laser, or the like can be used. Laser drilling stops at the pattern of the metal layer 14, and a hole 13a having a certain depth can be obtained.
  • a laser method is shown here, but the method is not limited to this method, and the hole 13a can be formed by a photographic technique using a photosensitive material as the insulating layer 13. Various construction methods can be used.
  • a desired resin is filled in the hole (13a in FIG. 4B) by a printing method using a squeegee, and stored in a heating furnace for a predetermined time, and the resin is cured to form a low-elasticity resin 11.
  • the hole filling method is not limited to a printing method, and it is sufficient that a desired resin can be formed in the hole 13a.
  • the mounting pad 12 and the wiring 12a are formed on the insulating layer 13 and the low elastic resin 11 by a known circuit forming method (step A4; see FIG. 4D). At this time, the mounting pad 12 is formed in the region of the low elastic resin 11. That is, the entire mounting pad 12 is formed on the low-elasticity resin 11 except for the extracted wiring 12a.
  • solder resist is formed at a desired position by a known solder resist forming method as necessary.
  • the wiring substrate 10 similar to that of FIG. 1 can be obtained.
  • bumps 30 are formed on the electrodes 21 of the semiconductor chip 20, and then a known flip chip is formed.
  • the connection method the mounting pads 12 and the bumps 30 of the wiring board 10 are bonded. Since the wiring board 10 has a structure that relieves stress, the material of the bump 30 is not particularly limited, and a conventionally used solder bump or the like can be used.
  • a flip-chip connection form is shown here, a form such as CSP (Chip Scale Package), BGA (Ball Grid Arrey), or a bare chip may be used depending on the electronic component to be mounted, and is not particularly limited. .
  • CSP Chip Scale Package
  • BGA Ball Grid Arrey
  • bare chip may be used depending on the electronic component to be mounted, and is not particularly limited.
  • the mounting pad 12 is formed in the region of the low elastic resin 11, it is possible to create a state where the mounting pad 12 is floating on the low elastic resin 11. Therefore, even if the material of the bump 30 formed on the electrode 21 of the semiconductor device 20 is a conventional high-elasticity solder, the stress generated by the difference in thermal expansion between the semiconductor device 20 and the wiring board 10 is absorbed by the low-elasticity resin 11. And can be relaxed.
  • This stress relaxation effect has an effect of preventing not only the destruction of the bumps 30 but also the occurrence of cracks in the semiconductor device 20 and the wiring substrate 10. As a result, it is possible to provide a highly reliable connection structure for a semiconductor device having a fragile insulating layer such as an ASIC for high end which will be developed in the future.
  • FIG. 5 is a plan view showing a partial configuration of the wiring board according to the second embodiment of the present invention.
  • the mounting pads (12 in FIG. 2; excluding the wiring 12a) are arranged in the region of the low elastic resin (11 in FIG. 2).
  • the mounting pads are mounted in the region of the low elastic resin 11.
  • the pad 12, the outer peripheral part 12b, and the connection part 12c are arranged.
  • Other configurations are the same as those of the first embodiment.
  • a mounting pad 12, a wiring 12a, an outer peripheral part 12b, and a connection part 12c made of a conductor (for example, copper) are integrally arranged.
  • the mounting pad 12 is disposed in the center, and a connection portion 12c for connecting the mounting pad 12 and the outer peripheral portion 12b is disposed in a part of the region between the mounting pad 12 and the outer peripheral portion 12b.
  • An outer peripheral portion 12 b is disposed on the insulating layer 13 on the outer periphery of the region of the low elastic resin 11.
  • the outer peripheral part 12b is arrange
  • the planar shape of the portion where the low-elasticity resin 11 is exposed is, for example, C-shaped (see FIG. 5A), arch-shaped (see FIG. 5B), or wedge-shaped (see FIG. 5C). Can be.
  • C-shape see FIG. 5A
  • arch type see FIG. 5B
  • wedge type windmill type; see FIG.
  • connection portions 12c there are four connection portions 12c, and the width of the connection portion 12c changes.
  • the planar shape of the portion where the low-elasticity resin 11 is exposed is not limited to the pattern of FIG. 5, and the shape and the number of connections can be freely combined according to the effect.
  • the connecting portion 12c can be formed in a straight line shape, a curved line shape, a diagonal line shape, or a combination thereof.
  • the mounting pad 12 on the low elastic resin 11 is stressed by dividing the mounting pad 12 and the outer peripheral portion 12b and connecting the mounting pad 12 and the outer peripheral portion 12b with one or a plurality of connection portions 12c. It becomes easier to follow the physical movement when buffering.
  • connection parts 12c even if buffering in a certain direction is achieved, even if the connection part 12c loaded in that direction breaks, the other connection parts 12c can be electrically connected. As a result, connection reliability can be improved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)

Abstract

Une fiabilité élevée d'une section connexion de bosses est garantie pour une connexion par billes, une connexion CSP et analogue. Un tableau de connexions est muni d'une couche isolante comportant une section en creux en une position prescrite ; d'une résine de faible élasticité qui est incluse dans la section en creux et présente une élasticité inférieure à celle de la couche isolante ; d'une plage de contact qui est destinée à une région plus petite que celle de la résine à faible élasticité et qui est disposée sur la résine à faible élasticité ; d'une couche métallique qui est disposée au moins sur la surface inférieure de la section en creux dans la couche isolante ; et d'un câblage qui est formé sur la couche isolante et la résine de faible élasticité et qui est connecté à la plage de contact.
PCT/JP2009/052862 2008-02-21 2009-02-19 Tableau de connexions et dispositif semi-conducteur Ceased WO2009104668A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009554362A JP5515744B2 (ja) 2008-02-21 2009-02-19 配線基板及び半導体装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008040335 2008-02-21
JP2008-040335 2008-02-21

Publications (1)

Publication Number Publication Date
WO2009104668A1 true WO2009104668A1 (fr) 2009-08-27

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PCT/JP2009/052862 Ceased WO2009104668A1 (fr) 2008-02-21 2009-02-19 Tableau de connexions et dispositif semi-conducteur

Country Status (2)

Country Link
JP (1) JP5515744B2 (fr)
WO (1) WO2009104668A1 (fr)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012126852A1 (fr) * 2011-03-21 2012-09-27 Osram Opto Semiconductors Gmbh Support de connexion pour puces semi-conductrices et composant à semi-conducteur
WO2012078709A3 (fr) * 2010-12-08 2012-10-18 Tessera, Inc. Interconnexions conformes dans des tranches
US8405196B2 (en) 2007-03-05 2013-03-26 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US9070678B2 (en) 2006-11-22 2015-06-30 Tessera, Inc. Packaged semiconductor chips with array
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream

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JP2000277923A (ja) * 1999-03-29 2000-10-06 Nec Corp マザーボードプリント配線板およびその製造方法
JP2004247549A (ja) * 2003-02-14 2004-09-02 Fujitsu Ltd 配線基板の作製方法および多層配線基板の作製方法

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JP2001094227A (ja) * 1999-09-20 2001-04-06 Shinko Electric Ind Co Ltd 半導体チップ実装用の配線基板と該基板を用いた半導体チップの実装方法
JP2003198068A (ja) * 2001-12-27 2003-07-11 Nec Corp プリント基板、半導体装置、およびプリント基板と部品との電気的接続構造

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000277923A (ja) * 1999-03-29 2000-10-06 Nec Corp マザーボードプリント配線板およびその製造方法
JP2004247549A (ja) * 2003-02-14 2004-09-02 Fujitsu Ltd 配線基板の作製方法および多層配線基板の作製方法

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
US9070678B2 (en) 2006-11-22 2015-06-30 Tessera, Inc. Packaged semiconductor chips with array
US8405196B2 (en) 2007-03-05 2013-03-26 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8735205B2 (en) 2007-03-05 2014-05-27 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8809190B2 (en) 2010-09-17 2014-08-19 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US9355948B2 (en) 2010-09-17 2016-05-31 Tessera, Inc. Multi-function and shielded 3D interconnects
US10354942B2 (en) 2010-09-17 2019-07-16 Tessera, Inc. Staged via formation from both sides of chip
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US9099296B2 (en) 2010-12-02 2015-08-04 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages with plural active chips
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