[go: up one dir, main page]

WO2009013879A1 - メモリーコントローラ、及びこれを用いた不揮発性記憶装置 - Google Patents

メモリーコントローラ、及びこれを用いた不揮発性記憶装置 Download PDF

Info

Publication number
WO2009013879A1
WO2009013879A1 PCT/JP2008/001904 JP2008001904W WO2009013879A1 WO 2009013879 A1 WO2009013879 A1 WO 2009013879A1 JP 2008001904 W JP2008001904 W JP 2008001904W WO 2009013879 A1 WO2009013879 A1 WO 2009013879A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory controller
page
storage device
same
physical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/001904
Other languages
English (en)
French (fr)
Inventor
Toshiyuki Honda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Priority to US12/526,224 priority Critical patent/US20100325342A1/en
Priority to JP2008551592A priority patent/JPWO2009013879A1/ja
Publication of WO2009013879A1 publication Critical patent/WO2009013879A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)

Abstract

　多値メモリセルを物理ブロックに用いた第１及び第２のフラッシュメモリ（不揮発性メモリ）（３ａ、３ｂ）の駆動制御を行うコントローラ（メモリーコントローラ）（２）において、複数の物理ブロック（８）に対して、これらの各物理ブロック（８）に設けられた物理ページ（９）を含んだページグループを６４個設定するとともに、ページグループの境界が、第ｎページの物理ページ（９）の後に設けられるように、上記複数の物理ブロック（８）の物理ページ（９）をグループ化する。
PCT/JP2008/001904 2007-07-20 2008-07-16 メモリーコントローラ、及びこれを用いた不揮発性記憶装置 Ceased WO2009013879A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/526,224 US20100325342A1 (en) 2007-07-20 2008-07-16 Memory controller and nonvolatile storage device using same
JP2008551592A JPWO2009013879A1 (ja) 2007-07-20 2008-07-16 メモリーコントローラ、及びこれを用いた不揮発性記憶装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007190004 2007-07-20
JP2007-190004 2007-07-20

Publications (1)

Publication Number Publication Date
WO2009013879A1 true WO2009013879A1 (ja) 2009-01-29

Family

ID=40281140

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/001904 Ceased WO2009013879A1 (ja) 2007-07-20 2008-07-16 メモリーコントローラ、及びこれを用いた不揮発性記憶装置

Country Status (3)

Country Link
US (1) US20100325342A1 (ja)
JP (1) JPWO2009013879A1 (ja)
WO (1) WO2009013879A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010020715A (ja) * 2008-07-14 2010-01-28 Toshiba Corp 半導体メモリコントローラおよび半導体メモリシステム
JP2011059889A (ja) * 2009-09-08 2011-03-24 Toshiba Corp メモリシステム
KR20120055544A (ko) * 2009-07-08 2012-05-31 샌디스크 테크놀로지스, 인코포레이티드 비휘발성 메모리를 위한 최적화된 페이지 프로그래밍 순서
JP2013536959A (ja) * 2010-08-31 2013-09-26 マイクロン テクノロジー， インク． ストライプに基づく不揮発性多値メモリ操作
US8606988B2 (en) 2009-06-16 2013-12-10 Phison Electronics Corp. Flash memory control circuit for interleavingly transmitting data into flash memories, flash memory storage system thereof, and data transfer method thereof

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100332922A1 (en) * 2009-06-30 2010-12-30 Mediatek Inc. Method for managing device and solid state disk drive utilizing the same
US9092340B2 (en) * 2009-12-18 2015-07-28 Sandisk Technologies Inc. Method and system for achieving die parallelism through block interleaving
US20110153912A1 (en) * 2009-12-18 2011-06-23 Sergey Anatolievich Gorobets Maintaining Updates of Multi-Level Non-Volatile Memory in Binary Non-Volatile Memory
TWI514141B (zh) * 2013-08-08 2015-12-21 Phison Electronics Corp 記憶體位址管理方法、記憶體控制器與記憶體儲存裝置
KR20240115575A (ko) * 2023-01-19 2024-07-26 삼성전자주식회사 컨트롤러의 클록을 제어하는 방법 및 스토리지 시스템

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11224221A (ja) * 1998-02-04 1999-08-17 Matsushita Electric Ind Co Ltd メモリ制御装置および方法
JP2002202911A (ja) * 2000-12-28 2002-07-19 Hitachi Ltd 不揮発性メモリ装置
JP2003036681A (ja) * 2001-07-23 2003-02-07 Hitachi Ltd 不揮発性記憶装置
JP2003317487A (ja) * 2002-04-18 2003-11-07 Hitachi Ltd 半導体記憶装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3105092B2 (ja) * 1992-10-06 2000-10-30 株式会社東芝 半導体メモリ装置
EP0935199B1 (en) * 1998-02-04 2011-05-04 Panasonic Corporation Memory control unit and memory control method and medium containing program for realizing the same
US7934074B2 (en) * 1999-08-04 2011-04-26 Super Talent Electronics Flash module with plane-interleaved sequential writes to restricted-write flash chips
JP3983969B2 (ja) * 2000-03-08 2007-09-26 株式会社東芝 不揮発性半導体記憶装置
JP4061272B2 (ja) * 2002-01-09 2008-03-12 株式会社ルネサステクノロジ メモリシステム及びメモリカード
US6657891B1 (en) * 2002-11-29 2003-12-02 Kabushiki Kaisha Toshiba Semiconductor memory device for storing multivalued data

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11224221A (ja) * 1998-02-04 1999-08-17 Matsushita Electric Ind Co Ltd メモリ制御装置および方法
JP2002202911A (ja) * 2000-12-28 2002-07-19 Hitachi Ltd 不揮発性メモリ装置
JP2003036681A (ja) * 2001-07-23 2003-02-07 Hitachi Ltd 不揮発性記憶装置
JP2003317487A (ja) * 2002-04-18 2003-11-07 Hitachi Ltd 半導体記憶装置

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010020715A (ja) * 2008-07-14 2010-01-28 Toshiba Corp 半導体メモリコントローラおよび半導体メモリシステム
US8606988B2 (en) 2009-06-16 2013-12-10 Phison Electronics Corp. Flash memory control circuit for interleavingly transmitting data into flash memories, flash memory storage system thereof, and data transfer method thereof
TWI425512B (zh) * 2009-06-16 2014-02-01 Phison Electronics Corp 快閃記憶體控制電路及其儲存系統與資料傳輸方法
KR20120055544A (ko) * 2009-07-08 2012-05-31 샌디스크 테크놀로지스, 인코포레이티드 비휘발성 메모리를 위한 최적화된 페이지 프로그래밍 순서
JP2012533139A (ja) * 2009-07-08 2012-12-20 サンディスク テクノロジーズ インコーポレイテッド 不揮発性メモリの最適化ページプログラミング順序
KR101701361B1 (ko) 2009-07-08 2017-02-01 샌디스크 테크놀로지스 엘엘씨 비휘발성 메모리를 위한 최적화된 페이지 프로그래밍 순서
JP2011059889A (ja) * 2009-09-08 2011-03-24 Toshiba Corp メモリシステム
US8301850B2 (en) 2009-09-08 2012-10-30 Kabushiki Kaisha Toshiba Memory system which writes data to multi-level flash memory by zigzag interleave operation
JP2013536959A (ja) * 2010-08-31 2013-09-26 マイクロン テクノロジー， インク． ストライプに基づく不揮発性多値メモリ操作
US9235503B2 (en) 2010-08-31 2016-01-12 Micron Technology, Inc. Stripe-based non-volatile multilevel memory operation

Also Published As

Publication number Publication date
US20100325342A1 (en) 2010-12-23
JPWO2009013879A1 (ja) 2010-09-30

Similar Documents

Publication Publication Date Title
WO2009013879A1 (ja) メモリーコントローラ、及びこれを用いた不揮発性記憶装置
TWI368223B (en) Flash memory data writing method and controller using the same
ES2498096T3 (es) Esquema de control de sistema de memoria Flash
WO2007028026A3 (en) Flash drive fast wear leveling
WO2009139567A3 (en) Memory device and memory programming method
WO2009089612A8 (en) Nonvolatile semiconductor memory device
TW200707189A (en) Memory block erasing in a flash memory device
SG156590A1 (en) Storage device including a memory cell having multiple memory layers
EP1914757A3 (en) Storage device and storing method
WO2009009076A3 (en) Error correction for memory
EP1840722A3 (en) Storage system using flash memories, wear-leveling method for the same system and wear-leveling program for the same system
WO2011034673A3 (en) Memory device and method
TWI373045B (en) Flash memory storage apparatus, flash memory controller and switching method thereof
WO2009097677A8 (en) Non-volatile memory device having configurable page size
GB2446355B (en) A controller for non-volatile memories, and methods of operating the memory controller
WO2009097681A8 (en) Flexible memory operations in nand flash devices
WO2010033975A3 (en) Programming a memory device to increase data reliability
TWI346955B (en) Non-volatile memory device and method of programming a multi level cell in the same
TWI346957B (en) Method, system, and memory device for generating soft bits in flash memories
WO2012024079A3 (en) Variable resistance memory array architecture
DE602005007960D1 (de) Nichtflüchtiger Halbleiterspeicher, Methode zum gleichzeitigen Löschen mehrerer Speicherblöcke und zugehörige Decoderschaltung
JP2008269775A5 (ja)
WO2010032998A3 (ko) 멀티-레벨 셀 플래시 메모리 장치에서의 lsb 페이지 복구 방법
WO2009038780A3 (en) Nand-structured series variable-resistance material memories, processes of forming same, and methods of using same
WO2015047962A8 (en) Volatile memory architecture in non-volatile memory devices and related controllers

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2008551592

Country of ref document: JP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08790206

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 12526224

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08790206

Country of ref document: EP

Kind code of ref document: A1