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WO2009000921A3 - Halbleiterstruktur zur herstellung eines traegerwaferkontaktes in einer graben-isolierten soi-scheibe - Google Patents

Halbleiterstruktur zur herstellung eines traegerwaferkontaktes in einer graben-isolierten soi-scheibe Download PDF

Info

Publication number
WO2009000921A3
WO2009000921A3 PCT/EP2008/058292 EP2008058292W WO2009000921A3 WO 2009000921 A3 WO2009000921 A3 WO 2009000921A3 EP 2008058292 W EP2008058292 W EP 2008058292W WO 2009000921 A3 WO2009000921 A3 WO 2009000921A3
Authority
WO
WIPO (PCT)
Prior art keywords
carrier wafer
semiconductor structure
trench
production
wafer contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2008/058292
Other languages
English (en)
French (fr)
Other versions
WO2009000921A2 (de
Inventor
Ralf Lerner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X Fab Semiconductor Foundries GmbH
Original Assignee
X Fab Semiconductor Foundries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X Fab Semiconductor Foundries GmbH filed Critical X Fab Semiconductor Foundries GmbH
Priority to US12/666,880 priority Critical patent/US8247884B2/en
Publication of WO2009000921A2 publication Critical patent/WO2009000921A2/de
Publication of WO2009000921A3 publication Critical patent/WO2009000921A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10W20/021—
    • H10P90/1906—
    • H10W10/041—
    • H10W10/061—
    • H10W10/181—
    • H10W10/40—

Landscapes

  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Packaging Frangible Articles (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

Es wird eine Halbleiterstruktur zur Herstellung eines Trägerwaferkontaktes in grabenisolierten SOI-Scheiben angegeben, die sowohl als tiefer Kontakt (7, 6, 30') zum Trägerwafer (1) einer dicken SOI-Scheibe als auch als Grabenisolation (40) verwendet werden kann. Dabei kommen für beide Strukturen die gleichen Verfahrensschritte zum Einsatz, die sowohl als tiefer Kontakt zum Trägerwafer der dicken SOI-Scheibe als auch als Grabenisolation verwendet werden.
PCT/EP2008/058292 2007-06-27 2008-06-27 Halbleiterstruktur zur herstellung eines traegerwaferkontaktes in einer graben-isolierten soi-scheibe Ceased WO2009000921A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/666,880 US8247884B2 (en) 2007-06-27 2008-06-27 Semiconductor structure for fabricating a handle wafer contact in a trench insulated SOI disc

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102007029756A DE102007029756A1 (de) 2007-06-27 2007-06-27 Halbleiterstruktur zur Herstellung eines Trägerwaferkontaktes in grabenisolierten SOI-Scheiben
DE102007029756.6 2007-06-27

Publications (2)

Publication Number Publication Date
WO2009000921A2 WO2009000921A2 (de) 2008-12-31
WO2009000921A3 true WO2009000921A3 (de) 2009-03-05

Family

ID=40030215

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2008/058292 Ceased WO2009000921A2 (de) 2007-06-27 2008-06-27 Halbleiterstruktur zur herstellung eines traegerwaferkontaktes in einer graben-isolierten soi-scheibe

Country Status (3)

Country Link
US (1) US8247884B2 (de)
DE (1) DE102007029756A1 (de)
WO (1) WO2009000921A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2956869B1 (fr) 2010-03-01 2014-05-16 Alex Hr Roustaei Systeme de production de film flexible a haute capacite destine a des cellules photovoltaiques et oled par deposition cyclique des couches
US8951915B2 (en) * 2012-09-11 2015-02-10 Infineon Technologies Ag Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6348363B1 (en) * 1999-07-06 2002-02-19 Samsung Electronics Co., Ltd. Method for manufacturing a semiconductor package
US20020163041A1 (en) * 2000-03-30 2002-11-07 Min-Su Kim Silicon-on-insulator (SOI) substrate, method for fabricating SOI substrate and SOI MOSFET using the SOI substrate
DE102005010944A1 (de) * 2005-03-10 2006-09-14 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung eines Trägerscheibenkontaktes in grabenisolierten integrierten SOI Schaltungen mit Hochspannungsbauelementen
US20060255406A1 (en) * 2005-05-16 2006-11-16 Matsushita Electric Industrial Co., Ltd. Semiconductor device

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US5241210A (en) * 1987-02-26 1993-08-31 Kabushiki Kaisha Toshiba High breakdown voltage semiconductor device
NL8700640A (nl) * 1987-03-18 1988-10-17 Philips Nv Halfgeleiderinrichting en werkwijze ter vervaardiging daarvan.
US5200354A (en) * 1988-07-22 1993-04-06 Hyundai Electronics Industries Co. Ltd. Method for manufacturing dynamic random access memory cell
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DE4127925C2 (de) * 1990-02-27 1994-01-13 Fraunhofer Ges Forschung Verfahren zum Erzeugen einer isolierten, einkristallinen Siliziuminsel
DE4233773C2 (de) * 1992-10-07 1996-09-19 Daimler Benz Ag Halbleiterstruktur für Halbleiterbauelemente mit hoher Durchbruchspannung
US5314841A (en) 1993-04-30 1994-05-24 International Business Machines Corporation Method of forming a frontside contact to the silicon substrate of a SOI wafer
US5360758A (en) * 1993-12-03 1994-11-01 International Business Machines Corporation Self-aligned buried strap for trench type DRAM cells
EP0766312B1 (de) * 1995-09-26 2002-01-16 Infineon Technologies AG Selbstverstärkende DRAM-Speicherzellenanordnung
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DE19735542A1 (de) * 1997-08-16 1999-02-18 Bosch Gmbh Robert Hochspannungsbauelement und Verfahren zu seiner Herstellung
DE19812212A1 (de) * 1998-03-19 1999-09-23 Siemens Ag MOS-Transistor in einer Ein-Transistor-Speicherzelle mit einem lokal verdickten Gateoxid und Herstellverfahren
US6037620A (en) * 1998-06-08 2000-03-14 International Business Machines Corporation DRAM cell with transfer device extending along perimeter of trench storage capacitor
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JP4206543B2 (ja) * 1999-02-02 2009-01-14 株式会社デンソー 半導体装置
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EP1083607A3 (de) * 1999-08-31 2005-09-21 Matsushita Electric Industrial Co., Ltd. SOI-Hochspannungshalbleiteranordnung
TW501227B (en) 2000-08-11 2002-09-01 Samsung Electronics Co Ltd SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same
KR100374554B1 (ko) 2000-09-22 2003-03-04 주식회사 하이닉스반도체 에스오아이 소자의 반도체 몸체-기판 접촉 구조 및 그제조방법
FR2830123A1 (fr) * 2001-09-26 2003-03-28 St Microelectronics Sa Peripherie haute tension
US6943396B2 (en) * 2003-06-17 2005-09-13 Infineon Technologies Ag Electro-static discharge protection circuit and method for making the same
DE102004004942A1 (de) * 2004-01-31 2005-08-18 X-Fab Semiconductor Foundries Ag Passivierung isolierender Trenngräben von integrierten Schaltungen
KR101078757B1 (ko) * 2004-04-27 2011-11-02 페어차일드코리아반도체 주식회사 고전압 접합 커패시터 및 고전압 수평형 디모스트랜지스터를 포함하는 고전압 게이트 드라이버 집적회로
DE102005059034B4 (de) * 2005-12-10 2007-10-11 X-Fab Semiconductor Foundries Ag SOI-Isolationsgrabenstrukturen

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6348363B1 (en) * 1999-07-06 2002-02-19 Samsung Electronics Co., Ltd. Method for manufacturing a semiconductor package
US20020163041A1 (en) * 2000-03-30 2002-11-07 Min-Su Kim Silicon-on-insulator (SOI) substrate, method for fabricating SOI substrate and SOI MOSFET using the SOI substrate
DE102005010944A1 (de) * 2005-03-10 2006-09-14 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung eines Trägerscheibenkontaktes in grabenisolierten integrierten SOI Schaltungen mit Hochspannungsbauelementen
US20060255406A1 (en) * 2005-05-16 2006-11-16 Matsushita Electric Industrial Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
US20100308432A1 (en) 2010-12-09
WO2009000921A2 (de) 2008-12-31
US8247884B2 (en) 2012-08-21
DE102007029756A1 (de) 2009-01-02

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