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WO2009072421A1 - Ｃｍｏｓ半導体装置およびその製造方法 - Google Patents

Ｃｍｏｓ半導体装置およびその製造方法 Download PDF

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Publication number
WO2009072421A1
WO2009072421A1 PCT/JP2008/071392 JP2008071392W WO2009072421A1 WO 2009072421 A1 WO2009072421 A1 WO 2009072421A1 JP 2008071392 W JP2008071392 W JP 2008071392W WO 2009072421 A1 WO2009072421 A1 WO 2009072421A1
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WIPO (PCT)
Prior art keywords
insulating layer
semiconductor device
same
manufacturing
cmos semiconductor
Prior art date
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Ceased
Application number
PCT/JP2008/071392
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English (en)
French (fr)
Inventor
Nobuyuki Mise
Takahisa Eimori
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Renesas Technology Corp
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Renesas Technology Corp
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Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to US12/745,638 priority Critical patent/US20100258878A1/en
Priority to JP2009544638A priority patent/JP5284276B2/ja
Priority to CN200880119004.4A priority patent/CN101884101B/zh
Publication of WO2009072421A1 publication Critical patent/WO2009072421A1/ja
Anticipated expiration legal-status Critical
Priority to US13/567,869 priority patent/US8698249B2/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H10D64/01342—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

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  • Engineering & Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

　ｎ型ＭＯＳＦＥＴとｐ型ＭＯＳＦＥＴとを含むＣＭＯＳ半導体装置において、ｎ型ＭＯＳＦＥＴのゲート電極は、ｈｉｇｈ－ｋ材料からなる第１絶縁層と、第１絶縁層の上に設けられ金属材料からなる第１金属層を有し、ｐ型ＭＯＳＦＥＴのゲート電極は、ｈｉｇｈ－ｋ材料からなる第２絶縁層と、第２絶縁層の上に設けられ金属材料からなる第２金属層を有し、第１絶縁層と第２絶縁層が異なるｈｉｇｈ－ｋ材料からなり、第１金属層と第２金属層が同一の金属材料からなる。
PCT/JP2008/071392 2007-12-03 2008-11-26 Ｃｍｏｓ半導体装置およびその製造方法 Ceased WO2009072421A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US12/745,638 US20100258878A1 (en) 2007-12-03 2008-11-26 Cmos semiconductor device and method for manufacturing the same
JP2009544638A JP5284276B2 (ja) 2007-12-03 2008-11-26 Ｃｍｏｓ半導体装置およびその製造方法
CN200880119004.4A CN101884101B (zh) 2007-12-03 2008-11-26 Cmos半导体装置及其制造方法
US13/567,869 US8698249B2 (en) 2007-12-03 2012-08-06 CMOS semiconductor device and method for manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007312010 2007-12-03
JP2007-312010 2007-12-03

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/745,638 A-371-Of-International US20100258878A1 (en) 2007-12-03 2008-11-26 Cmos semiconductor device and method for manufacturing the same
US13/567,869 Division US8698249B2 (en) 2007-12-03 2012-08-06 CMOS semiconductor device and method for manufacturing the same

Publications (1)

Publication Number Publication Date
WO2009072421A1 true WO2009072421A1 (ja) 2009-06-11

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US (2) US20100258878A1 (ja)
JP (1) JP5284276B2 (ja)
CN (1) CN101884101B (ja)
TW (1) TWI492367B (ja)
WO (1) WO2009072421A1 (ja)

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JP2010135735A (ja) * 2008-07-01 2010-06-17 Panasonic Corp 半導体装置及びその製造方法
JP2010262977A (ja) * 2009-04-30 2010-11-18 Renesas Electronics Corp 半導体装置の製造方法
WO2010150332A1 (ja) * 2009-06-24 2010-12-29 パナソニック株式会社 半導体装置及びその製造方法
WO2010149058A1 (zh) * 2009-06-26 2010-12-29 中国科学院微电子研究所 控制器件阀值电压的cmosfet结构及其制造方法
DE102009031155A1 (de) * 2009-06-30 2011-01-05 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Gleichmäßige Metallgatestapel mit großem ε durch Einstellen einer Schwellwertspannung für komplexe Transistoren durch Diffundieren einer Metallsorte vor der Gatestrukturierung
JP2011003664A (ja) * 2009-06-17 2011-01-06 Renesas Electronics Corp 半導体装置およびその製造方法
JP2011009373A (ja) * 2009-06-24 2011-01-13 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
JP2011009321A (ja) * 2009-06-24 2011-01-13 Fujitsu Semiconductor Ltd 半導体装置の製造方法
JP2011029483A (ja) * 2009-07-28 2011-02-10 Renesas Electronics Corp 半導体装置およびその製造方法
JP2011035229A (ja) * 2009-08-04 2011-02-17 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法
JP2011077421A (ja) * 2009-10-01 2011-04-14 Renesas Electronics Corp 半導体装置の製造方法
US8288221B2 (en) 2008-08-13 2012-10-16 Renesas Electronics Corporation Method of manufacturing semiconductor device and semiconductor device
JP2013506289A (ja) * 2009-09-28 2013-02-21 フリースケール セミコンダクター インコーポレイテッド 酸素拡散バリア層を有する半導体デバイスおよびそれを製造するための方法
JP5456150B2 (ja) * 2010-02-17 2014-03-26 パナソニック株式会社 半導体装置及びその製造方法

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KR101656444B1 (ko) * 2010-01-25 2016-09-09 삼성전자주식회사 상보형 ｍｏｓ 트랜지스터, 상기 상보형 ｍｏｓ 트랜지스터를 포함하는 반도체 장치, 및 상기 반도체 장치를 포함하는 반도체 모듈
KR101131891B1 (ko) * 2010-07-30 2012-04-03 주식회사 하이닉스반도체 매립게이트를 구비한 반도체 장치 제조방법
JP2012204652A (ja) * 2011-03-25 2012-10-22 Toshiba Corp 半導体装置の製造方法
US8440520B2 (en) 2011-08-23 2013-05-14 Tokyo Electron Limited Diffused cap layers for modifying high-k gate dielectrics and interface layers
US8633118B2 (en) 2012-02-01 2014-01-21 Tokyo Electron Limited Method of forming thin metal and semi-metal layers by thermal remote oxygen scavenging
US8865538B2 (en) 2012-03-30 2014-10-21 Tokyo Electron Limited Method of integrating buried threshold voltage adjustment layers for CMOS processing
US8865581B2 (en) 2012-10-19 2014-10-21 Tokyo Electron Limited Hybrid gate last integration scheme for multi-layer high-k gate stacks
KR102066851B1 (ko) 2013-02-25 2020-02-11 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US10431583B2 (en) 2016-02-11 2019-10-01 Samsung Electronics Co., Ltd. Semiconductor device including transistors with adjusted threshold voltages
US10128347B2 (en) * 2017-01-04 2018-11-13 International Business Machines Corporation Gate-all-around field effect transistor having multiple threshold voltages
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Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010135735A (ja) * 2008-07-01 2010-06-17 Panasonic Corp 半導体装置及びその製造方法
US8288221B2 (en) 2008-08-13 2012-10-16 Renesas Electronics Corporation Method of manufacturing semiconductor device and semiconductor device
JP2010262977A (ja) * 2009-04-30 2010-11-18 Renesas Electronics Corp 半導体装置の製造方法
JP2011003664A (ja) * 2009-06-17 2011-01-06 Renesas Electronics Corp 半導体装置およびその製造方法
JP2011009321A (ja) * 2009-06-24 2011-01-13 Fujitsu Semiconductor Ltd 半導体装置の製造方法
WO2010150332A1 (ja) * 2009-06-24 2010-12-29 パナソニック株式会社 半導体装置及びその製造方法
JP2011009373A (ja) * 2009-06-24 2011-01-13 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
JP2011009313A (ja) * 2009-06-24 2011-01-13 Panasonic Corp 半導体装置及びその製造方法
WO2010149058A1 (zh) * 2009-06-26 2010-12-29 中国科学院微电子研究所 控制器件阀值电压的cmosfet结构及其制造方法
US8410555B2 (en) 2009-06-26 2013-04-02 Institute of Microelectronics, Chinese Academy of Sciences CMOSFET device with controlled threshold voltage and method of fabricating the same
WO2011008401A1 (en) * 2009-06-30 2011-01-20 Globalfoundries Inc. Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterning
DE102009031155A1 (de) * 2009-06-30 2011-01-05 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Gleichmäßige Metallgatestapel mit großem ε durch Einstellen einer Schwellwertspannung für komplexe Transistoren durch Diffundieren einer Metallsorte vor der Gatestrukturierung
US8445344B2 (en) 2009-06-30 2013-05-21 Globalfoundries Inc. Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterning
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US8698249B2 (en) 2014-04-15
JP5284276B2 (ja) 2013-09-11
TW200935589A (en) 2009-08-16
JPWO2009072421A1 (ja) 2011-04-21
CN101884101B (zh) 2017-06-13
US20130034953A1 (en) 2013-02-07

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