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WO2009066993A2 - Utilisation de l'exclusion de bords d'une tranche sélective pour obtenir une topographie presque plane - Google Patents

Utilisation de l'exclusion de bords d'une tranche sélective pour obtenir une topographie presque plane Download PDF

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Publication number
WO2009066993A2
WO2009066993A2 PCT/MY2008/000159 MY2008000159W WO2009066993A2 WO 2009066993 A2 WO2009066993 A2 WO 2009066993A2 MY 2008000159 W MY2008000159 W MY 2008000159W WO 2009066993 A2 WO2009066993 A2 WO 2009066993A2
Authority
WO
WIPO (PCT)
Prior art keywords
wee
wafer
selective
planar topography
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/MY2008/000159
Other languages
English (en)
Other versions
WO2009066993A3 (fr
Inventor
Wan Idrus
Khairil Mazwan Mohd Zaini
Anifah Zakaria
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mimos Bhd
Original Assignee
Mimos Bhd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Bhd filed Critical Mimos Bhd
Publication of WO2009066993A2 publication Critical patent/WO2009066993A2/fr
Publication of WO2009066993A3 publication Critical patent/WO2009066993A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G03F7/2026—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure for the removal of unwanted material, e.g. image or background correction
    • G03F7/2028—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure for the removal of unwanted material, e.g. image or background correction of an edge bead on wafers

Definitions

  • the present invention is directed to a method to obtain a near planar topography around the wafer coding area for removing photoresist; and, more particularly to remove pattern defects which will affects the yield arising from the non-planar topography near the wafer coding area.
  • Wafer Edge Exclusion is used to remove the photoresist such as at the wafer coding area, leaving the layer beneath the photoresist exposed. In this way the exposed layer will be etched away during the etching process. However, since all the layers at the WEE area are etched away, the overall thickness of this area would be lesser than the other area/s. This causes the photoresist thickness at WEE area to differ during photoresist coating. Therefore, the thickness of the photoresist is thinner at the edge of WEE as compared to the rest of the wafer. This is illustrated in figure 1.
  • the photoresist produces smaller patterns (metal lines / via holes) and at some instances completely breaks the line or merges the holes during the wafer patterning process step. This problem is carried on to the next step of etching.
  • the thin photoresist is unable to provide enough protection to the layers beneath it thus causing over etching. This will cause pattern defect on the layers being etched
  • a primary object of the present invention to provide an improved method capable of obtaining a near planar topography around the wafer coding area, which further reduces the occurrences of metal pattern defects around the wafer coding area.
  • a method for selective exposing one or more parts of the wafer using a WEE process is provided.
  • Wafer Edge Exposure is used to remove resist at the wafer coding area so that the wafer coding can be visible throughout the wafer processing.
  • WEE Wafer Edge Exposure
  • Figure 1 shows the resultant cross section when WEE is used at all layers. A severe topography gradient is visible at the edge of the WEE valley.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

L'invention concerne un procédé pour éliminer une photorésine à l'aide de l'exclusion de bords d'une tranche (WEE) à partir du codage de tranche. La WEE est utilisée au niveau de couches sélectives de la tranche afin de réduire le défaut topographique autour de la zone de codage de tranche.
PCT/MY2008/000159 2007-11-22 2008-11-24 Utilisation de l'exclusion de bords d'une tranche sélective pour obtenir une topographie presque plane Ceased WO2009066993A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
MYPI20072075 2007-11-22
MYPI20072075 2007-11-22

Publications (2)

Publication Number Publication Date
WO2009066993A2 true WO2009066993A2 (fr) 2009-05-28
WO2009066993A3 WO2009066993A3 (fr) 2009-10-15

Family

ID=40668027

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/MY2008/000159 Ceased WO2009066993A2 (fr) 2007-11-22 2008-11-24 Utilisation de l'exclusion de bords d'une tranche sélective pour obtenir une topographie presque plane

Country Status (1)

Country Link
WO (1) WO2009066993A2 (fr)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010059550A (ko) * 1999-12-30 2001-07-06 박종섭 반도체 소자의 제조 방법
US6743735B2 (en) * 2002-03-19 2004-06-01 Taiwan Semiconductor Manufacturing Co., Ltd Photoresist removal from alignment marks through wafer edge exposure

Also Published As

Publication number Publication date
WO2009066993A3 (fr) 2009-10-15

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