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WO2009044444A1 - クロック生成装置およびクロック生成方法 - Google Patents

クロック生成装置およびクロック生成方法 Download PDF

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Publication number
WO2009044444A1
WO2009044444A1 PCT/JP2007/069202 JP2007069202W WO2009044444A1 WO 2009044444 A1 WO2009044444 A1 WO 2009044444A1 JP 2007069202 W JP2007069202 W JP 2007069202W WO 2009044444 A1 WO2009044444 A1 WO 2009044444A1
Authority
WO
WIPO (PCT)
Prior art keywords
clock
output clock
generated
generating device
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/069202
Other languages
English (en)
French (fr)
Inventor
Yasutaka Kanayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2007/069202 priority Critical patent/WO2009044444A1/ja
Priority to JP2009535902A priority patent/JP4669563B2/ja
Publication of WO2009044444A1 publication Critical patent/WO2009044444A1/ja
Priority to US12/724,868 priority patent/US7986176B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Measuring Phase Differences (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

　逓倍器によって逓倍された高速クロックを用いて、基準クロックと、分周器によって生成された返還クロックとの位相の差を測定する位相差測定器と、測定された位相の差を平均化する平均化器と、自己が生成した出力クロックを逓倍器および分周器に返還し、平均化された位相の差と、生成された動作クロックとを用いて基準クロックと同期した出力クロックを生成する出力クロック生成器と、返還された出力クロックを逓倍して、高速クロックを生成する逓倍器と、返還された出力クロックを分周して、返還クロックを生成する分周器とを有し、基準クロックと同期した出力クロックを生成するクロック生成装置において、周波数が大きく変動した出力クロックを生成して、生成された出力クロックを使用するデジタル同期網内の各装置の動作に悪影響を及ぼすことを課題とし、出力クロック生成器における出力クロックの生成頻度を増加させる。
PCT/JP2007/069202 2007-10-01 2007-10-01 クロック生成装置およびクロック生成方法 Ceased WO2009044444A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/069202 WO2009044444A1 (ja) 2007-10-01 2007-10-01 クロック生成装置およびクロック生成方法
JP2009535902A JP4669563B2 (ja) 2007-10-01 2007-10-01 クロック生成装置、電子装置およびクロック生成方法
US12/724,868 US7986176B2 (en) 2007-10-01 2010-03-16 Clock generating apparatus and clock generating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/069202 WO2009044444A1 (ja) 2007-10-01 2007-10-01 クロック生成装置およびクロック生成方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/724,868 Continuation US7986176B2 (en) 2007-10-01 2010-03-16 Clock generating apparatus and clock generating method

Publications (1)

Publication Number Publication Date
WO2009044444A1 true WO2009044444A1 (ja) 2009-04-09

Family

ID=40525877

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/069202 Ceased WO2009044444A1 (ja) 2007-10-01 2007-10-01 クロック生成装置およびクロック生成方法

Country Status (3)

Country Link
US (1) US7986176B2 (ja)
JP (1) JP4669563B2 (ja)
WO (1) WO2009044444A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109039309A (zh) * 2018-08-06 2018-12-18 电子科技大学 基于锁相环机理的高平坦度宽带梳状谱发生器及发生方法
US20220329248A1 (en) * 2022-06-16 2022-10-13 Intel Corporation Apparatus, system, and method of a digitally-controlled frequency multiplier

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102215799B1 (ko) * 2013-07-08 2021-02-16 에스케이하이닉스 주식회사 위상 탐지기, 위상 주파수 탐지기 및 디지털 위상 고정 루프
US9337849B2 (en) * 2013-07-08 2016-05-10 SK Hynix Inc. Phase detector, phase-frequency detector, and digital phase locked loop
CN108427234B (zh) * 2017-02-13 2020-10-02 工业和信息化部电信研究院 一种基于光学频率梳的超高精度基准源
US10983554B2 (en) * 2019-02-15 2021-04-20 Wipro Limited Method and system for clock synchronization based on time based control

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05110427A (ja) * 1991-05-08 1993-04-30 Nec Corp 位相同期回路
JP2005150868A (ja) * 2003-11-12 2005-06-09 Fujitsu Ltd シンセサイザ
JP2007027809A (ja) * 2005-07-12 2007-02-01 Fujitsu Ltd デジタルｐｌｌ回路およびその同期制御方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6873670B1 (en) * 2002-10-04 2005-03-29 National Semiconductor Corporation Automatic pre-scaler control for a phase-locked loop
KR100547831B1 (ko) * 2003-06-18 2006-01-31 삼성전자주식회사 가변 데이터 전송률에 대응이 가능한 클럭 및 데이터 복원장치
JP2005244648A (ja) 2004-02-26 2005-09-08 Matsushita Electric Ind Co Ltd デジタルｐｌｌ回路
JP4468196B2 (ja) * 2005-02-03 2010-05-26 富士通株式会社 デジタルｐｌｌ回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05110427A (ja) * 1991-05-08 1993-04-30 Nec Corp 位相同期回路
JP2005150868A (ja) * 2003-11-12 2005-06-09 Fujitsu Ltd シンセサイザ
JP2007027809A (ja) * 2005-07-12 2007-02-01 Fujitsu Ltd デジタルｐｌｌ回路およびその同期制御方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109039309A (zh) * 2018-08-06 2018-12-18 电子科技大学 基于锁相环机理的高平坦度宽带梳状谱发生器及发生方法
US20220329248A1 (en) * 2022-06-16 2022-10-13 Intel Corporation Apparatus, system, and method of a digitally-controlled frequency multiplier

Also Published As

Publication number Publication date
JPWO2009044444A1 (ja) 2011-01-27
JP4669563B2 (ja) 2011-04-13
US7986176B2 (en) 2011-07-26
US20100171534A1 (en) 2010-07-08

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