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WO2008136332A1 - メモリアクセス制御装置 - Google Patents

メモリアクセス制御装置 Download PDF

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Publication number
WO2008136332A1
WO2008136332A1 PCT/JP2008/057884 JP2008057884W WO2008136332A1 WO 2008136332 A1 WO2008136332 A1 WO 2008136332A1 JP 2008057884 W JP2008057884 W JP 2008057884W WO 2008136332 A1 WO2008136332 A1 WO 2008136332A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
arbiter
access
memory access
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/057884
Other languages
English (en)
French (fr)
Inventor
Tetsuro Takizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to US12/595,661 priority Critical patent/US20100082877A1/en
Priority to CN2008800135656A priority patent/CN101669096B/zh
Priority to EP08740811A priority patent/EP2141600B1/en
Publication of WO2008136332A1 publication Critical patent/WO2008136332A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

　本発明は、ユニファイドメモリアーキテクチャやマルチプロセッサのシステムにおいて、特定のメモリマスタからのアクセスのメモリアクセスレイテンシを低減することが可能なメモリアクセス制御装置を提供する。複数のメモリマスタ１１～１４からのアクセス要求を受け調停を行うアービタ２０とサブアービタ３０と、メモリコントローラ４０と、複数のバンクからなるメモリ５０を備え、アービタ２０により許可され現在実行中のアクセス要求で使用されるメモリのバンクと、サブアービタ３０によるアクセス要求がアクセスしようとするメモリのバンクが異なり、アービタ２０により許可され現在実行中のアクセス要求の種類と前記サブアービタが行おうとするメモリアクセスの種類が同一の場合にアクセス効率が低下しないと判断し、アービタ２０によるメモリアクセスを中断し、サブアービタ３０によるメモリアクセスを割り込ませる（図１）。
PCT/JP2008/057884 2007-04-26 2008-04-24 メモリアクセス制御装置 Ceased WO2008136332A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/595,661 US20100082877A1 (en) 2007-04-26 2008-04-24 Memory access control apparatus
CN2008800135656A CN101669096B (zh) 2007-04-26 2008-04-24 存储器访问控制装置
EP08740811A EP2141600B1 (en) 2007-04-26 2008-04-24 Memory access control device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007117318A JP4715801B2 (ja) 2007-04-26 2007-04-26 メモリアクセス制御装置
JP2007-117318 2007-04-26

Publications (1)

Publication Number Publication Date
WO2008136332A1 true WO2008136332A1 (ja) 2008-11-13

Family

ID=39943443

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/057884 Ceased WO2008136332A1 (ja) 2007-04-26 2008-04-24 メモリアクセス制御装置

Country Status (5)

Country Link
US (1) US20100082877A1 (ja)
EP (1) EP2141600B1 (ja)
JP (1) JP4715801B2 (ja)
CN (1) CN101669096B (ja)
WO (1) WO2008136332A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021060726A (ja) * 2019-10-04 2021-04-15 キヤノン株式会社 データ処理システムおよびデータ処理システムの制御方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5125890B2 (ja) * 2008-08-28 2013-01-23 富士通セミコンダクター株式会社 調停装置及び電子機器
US8244987B2 (en) 2008-12-04 2012-08-14 Electronics And Telecommunications Research Institute Memory access device including multiple processors
US20110246688A1 (en) * 2010-04-01 2011-10-06 Irwin Vaz Memory arbitration to ensure low latency for high priority memory requests
JP5776022B2 (ja) * 2011-04-13 2015-09-09 パナソニックＩｐマネジメント株式会社 制御装置
CN102609378B (zh) * 2012-01-18 2016-03-30 中国科学院计算技术研究所 一种消息式内存访问装置及其访问方法
JP2013196321A (ja) * 2012-03-19 2013-09-30 Pfu Ltd 電子回路及び調停方法
CN103902472B (zh) 2012-12-28 2018-04-20 华为技术有限公司 基于内存芯片互连的内存访问处理方法、内存芯片及系统
KR20150093004A (ko) * 2014-02-06 2015-08-17 삼성전자주식회사 불휘발성 저장 장치의 동작 방법 및 불휘발성 저장 장치를 액세스하는 컴퓨팅 장치의 동작 방법
CN106339329B (zh) * 2015-12-04 2019-09-13 深圳开阳电子股份有限公司 控制多请求源访问存储器的方法、控制器和视频处理装置
CN105824768B (zh) * 2016-03-15 2018-09-07 杭州中天微系统有限公司 一种支持多层中断优先级控制的矢量中断控制器
CN113051195A (zh) * 2021-03-02 2021-06-29 长沙景嘉微电子股份有限公司 存储器、gpu及电子设备

Citations (7)

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JPS59225426A (ja) 1983-06-06 1984-12-18 Nec Corp 入出力制御装置
JP2001135079A (ja) 1999-11-04 2001-05-18 Ricoh Co Ltd メモリ制御装置
JP2001175530A (ja) * 1999-12-22 2001-06-29 Nec Ic Microcomput Syst Ltd メモリアクセス調停装置およびメモリアクセス調停方法
JP2002007203A (ja) * 2000-06-19 2002-01-11 Brother Ind Ltd メモリアクセス制御装置および記憶媒体
JP2002123420A (ja) 2000-10-13 2002-04-26 Matsushita Electric Ind Co Ltd メモリアクセス装置
JP2005316609A (ja) 2004-04-27 2005-11-10 Sony Corp バス調停装置およびバス調停方法
WO2007004696A1 (ja) * 2005-07-06 2007-01-11 Matsushita Electric Industrial Co., Ltd. アクセス制御装置、アクセス制御集積回路、及びアクセス制御方法

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US6119196A (en) * 1997-06-30 2000-09-12 Sun Microsystems, Inc. System having multiple arbitrating levels for arbitrating access to a shared memory by network ports operating at different data rates
JP2001356961A (ja) * 2000-06-13 2001-12-26 Nec Corp 調停装置
JP2003030042A (ja) * 2001-07-11 2003-01-31 Fujitsu Ten Ltd 複数コア付マイクロコンピュータ装置
JP4209648B2 (ja) * 2002-09-05 2009-01-14 パナソニック株式会社 メモリ装置
WO2004068349A1 (ja) * 2003-01-27 2004-08-12 Matsushita Electric Industrial Co., Ltd. メモリ制御装置
KR100585116B1 (ko) * 2003-12-13 2006-06-01 삼성전자주식회사 멀티 뱅크 메모리의 억세스 효율을 개선한 아비터, 이를구비한 메모리 억세스 중재 시스템 및 그 방법
US7716387B2 (en) * 2005-07-14 2010-05-11 Canon Kabushiki Kaisha Memory control apparatus and method
US7603503B1 (en) * 2006-09-18 2009-10-13 Nvidia Corporation Efficiency based arbiter

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59225426A (ja) 1983-06-06 1984-12-18 Nec Corp 入出力制御装置
JP2001135079A (ja) 1999-11-04 2001-05-18 Ricoh Co Ltd メモリ制御装置
JP2001175530A (ja) * 1999-12-22 2001-06-29 Nec Ic Microcomput Syst Ltd メモリアクセス調停装置およびメモリアクセス調停方法
JP2002007203A (ja) * 2000-06-19 2002-01-11 Brother Ind Ltd メモリアクセス制御装置および記憶媒体
JP2002123420A (ja) 2000-10-13 2002-04-26 Matsushita Electric Ind Co Ltd メモリアクセス装置
JP2005316609A (ja) 2004-04-27 2005-11-10 Sony Corp バス調停装置およびバス調停方法
WO2007004696A1 (ja) * 2005-07-06 2007-01-11 Matsushita Electric Industrial Co., Ltd. アクセス制御装置、アクセス制御集積回路、及びアクセス制御方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2141600A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021060726A (ja) * 2019-10-04 2021-04-15 キヤノン株式会社 データ処理システムおよびデータ処理システムの制御方法
JP7419010B2 (ja) 2019-10-04 2024-01-22 キヤノン株式会社 データ処理システムおよびデータ処理システムの制御方法

Also Published As

Publication number Publication date
JP2008276391A (ja) 2008-11-13
EP2141600A1 (en) 2010-01-06
EP2141600B1 (en) 2013-01-30
CN101669096B (zh) 2013-03-27
US20100082877A1 (en) 2010-04-01
JP4715801B2 (ja) 2011-07-06
EP2141600A4 (en) 2011-03-16
CN101669096A (zh) 2010-03-10

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