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WO2008126661A1 - 多層セラミック基板およびその製造方法 - Google Patents

多層セラミック基板およびその製造方法 Download PDF

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Publication number
WO2008126661A1
WO2008126661A1 PCT/JP2008/055496 JP2008055496W WO2008126661A1 WO 2008126661 A1 WO2008126661 A1 WO 2008126661A1 JP 2008055496 W JP2008055496 W JP 2008055496W WO 2008126661 A1 WO2008126661 A1 WO 2008126661A1
Authority
WO
WIPO (PCT)
Prior art keywords
interlayer
ceramic substrate
layer
multilayer ceramic
base material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/055496
Other languages
English (en)
French (fr)
Inventor
Yuichi Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2008538063A priority Critical patent/JP4821855B2/ja
Publication of WO2008126661A1 publication Critical patent/WO2008126661A1/ja
Priority to US12/265,984 priority patent/US7670672B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H10W70/685—
    • H10W70/692—
    • H10W76/15—
    • H10W99/00—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/308—Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • H10W70/682—
    • H10W72/07251—
    • H10W72/20—
    • H10W72/884—
    • H10W90/734—
    • H10W90/754—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

　いわゆる無収縮プロセスによりキャビティ付き多層セラミック基板を製造するとき、キャビティの底面の周縁部においてクラック等が発生しやすい。 　底部（２）とキャビティ（４）を規定する壁部（５）との境界面（８）を挟んで、底部（２）側に基材層（６）を配置し、壁部（５）側に層間拘束層（７）を配置する。境界面（８）を挟んで配置される基材層（６）と層間拘束層（７）との間に、導体膜（９）を配置し、導体膜（９）の作用により、層間拘束層（７）の、基材層（６）に対する密着性を高め、層間拘束層（７）による収縮抑制効果を高める。
PCT/JP2008/055496 2007-04-11 2008-03-25 多層セラミック基板およびその製造方法 Ceased WO2008126661A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008538063A JP4821855B2 (ja) 2007-04-11 2008-03-25 多層セラミック基板およびその製造方法
US12/265,984 US7670672B2 (en) 2007-04-11 2008-11-06 Multilayer ceramic substrate and method for producing same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007103439 2007-04-11
JP2007-103439 2007-04-11

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/265,984 Continuation US7670672B2 (en) 2007-04-11 2008-11-06 Multilayer ceramic substrate and method for producing same

Publications (1)

Publication Number Publication Date
WO2008126661A1 true WO2008126661A1 (ja) 2008-10-23

Family

ID=39863779

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/055496 Ceased WO2008126661A1 (ja) 2007-04-11 2008-03-25 多層セラミック基板およびその製造方法

Country Status (3)

Country Link
US (1) US7670672B2 (ja)
JP (1) JP4821855B2 (ja)
WO (1) WO2008126661A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010186881A (ja) * 2009-02-12 2010-08-26 Hitachi Metals Ltd 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法
JP2010186880A (ja) * 2009-02-12 2010-08-26 Hitachi Metals Ltd 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法
JP2011151307A (ja) * 2010-01-25 2011-08-04 Kyocera Corp 配線基板の製造方法
JP2012248798A (ja) * 2011-05-31 2012-12-13 Kyocera Corp 配線基板の製造方法および配線基板
JP2013051389A (ja) * 2011-08-01 2013-03-14 Ngk Spark Plug Co Ltd 回路基板、半導体パワーモジュール、製造方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104589738A (zh) * 2008-05-15 2015-05-06 株式会社村田制作所 多层陶瓷基板及其制造方法
WO2010122822A1 (ja) * 2009-04-21 2010-10-28 株式会社村田製作所 多層セラミック基板の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001135933A (ja) * 1999-11-04 2001-05-18 Murata Mfg Co Ltd 多層セラミック基板
JP2003273513A (ja) * 2002-03-14 2003-09-26 Murata Mfg Co Ltd キャビティ付き多層セラミック基板の製造方法およびキャビティ付き多層セラミック基板
JP2005116938A (ja) * 2003-10-10 2005-04-28 Ngk Spark Plug Co Ltd キャビティ付き多層セラミック基板およびその製造方法
JP2007067364A (ja) * 2004-09-03 2007-03-15 Murata Mfg Co Ltd チップ型電子部品を搭載したセラミック基板及びその製造方法

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DE69006609T2 (de) * 1989-03-15 1994-06-30 Ngk Insulators Ltd Keramischer Deckel zum Verschliessen eines Halbleiterelements und Verfahren zum Verschliessen eines Halbleiterelements in einer keramischen Packung.
US5702985A (en) * 1992-06-26 1997-12-30 Staktek Corporation Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method
JP3225666B2 (ja) * 1993-01-27 2001-11-05 株式会社村田製作所 キャビティ付きセラミック多層ブロックの製造方法
US6248429B1 (en) * 1998-07-06 2001-06-19 Micron Technology, Inc. Metallized recess in a substrate
JP3656484B2 (ja) * 1999-03-03 2005-06-08 株式会社村田製作所 セラミック多層基板の製造方法
JP3687443B2 (ja) * 1999-10-12 2005-08-24 株式会社村田製作所 低温焼成セラミック組成物及びセラミック多層基板
JP4158338B2 (ja) 2000-06-06 2008-10-01 株式会社デンソー インジェクタ用圧電体素子
JP3757788B2 (ja) * 2000-11-27 2006-03-22 株式会社村田製作所 多層セラミック基板およびその製造方法
JP3709802B2 (ja) * 2001-03-28 2005-10-26 株式会社村田製作所 多層セラミック基板の製造方法
JP2002368420A (ja) * 2001-06-05 2002-12-20 Murata Mfg Co Ltd ガラスセラミック多層基板の製造方法およびガラスセラミック多層基板
US20080223606A1 (en) 2004-09-03 2008-09-18 Murata Manufacturing Co., Ltd. Ceramic Substrate and Method for Manufacturing the Same
JP4687333B2 (ja) * 2005-08-29 2011-05-25 株式会社村田製作所 多層セラミック基板およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001135933A (ja) * 1999-11-04 2001-05-18 Murata Mfg Co Ltd 多層セラミック基板
JP2003273513A (ja) * 2002-03-14 2003-09-26 Murata Mfg Co Ltd キャビティ付き多層セラミック基板の製造方法およびキャビティ付き多層セラミック基板
JP2005116938A (ja) * 2003-10-10 2005-04-28 Ngk Spark Plug Co Ltd キャビティ付き多層セラミック基板およびその製造方法
JP2007067364A (ja) * 2004-09-03 2007-03-15 Murata Mfg Co Ltd チップ型電子部品を搭載したセラミック基板及びその製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010186881A (ja) * 2009-02-12 2010-08-26 Hitachi Metals Ltd 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法
JP2010186880A (ja) * 2009-02-12 2010-08-26 Hitachi Metals Ltd 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法
JP2011151307A (ja) * 2010-01-25 2011-08-04 Kyocera Corp 配線基板の製造方法
JP2012248798A (ja) * 2011-05-31 2012-12-13 Kyocera Corp 配線基板の製造方法および配線基板
JP2013051389A (ja) * 2011-08-01 2013-03-14 Ngk Spark Plug Co Ltd 回路基板、半導体パワーモジュール、製造方法

Also Published As

Publication number Publication date
JPWO2008126661A1 (ja) 2010-07-22
US7670672B2 (en) 2010-03-02
JP4821855B2 (ja) 2011-11-24
US20090053532A1 (en) 2009-02-26

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