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WO2008147012A1 - Structure de cristallisation, procédé de cristallisation, procédé de formation d'une couche active d'une couche de silicium amorphe semi-conducteur, et procédé de fabrication d'un transistor à film mince utilisant celle-ci - Google Patents

Structure de cristallisation, procédé de cristallisation, procédé de formation d'une couche active d'une couche de silicium amorphe semi-conducteur, et procédé de fabrication d'un transistor à film mince utilisant celle-ci Download PDF

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Publication number
WO2008147012A1
WO2008147012A1 PCT/KR2008/000161 KR2008000161W WO2008147012A1 WO 2008147012 A1 WO2008147012 A1 WO 2008147012A1 KR 2008000161 W KR2008000161 W KR 2008000161W WO 2008147012 A1 WO2008147012 A1 WO 2008147012A1
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Prior art keywords
regions
amorphous silicon
silicon layer
crystallization
flat bottom
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PCT/KR2008/000161
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English (en)
Inventor
Tae Hoon Jeong
Hyun Jae Kim
Choong Hee Lee
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Industry Academic Cooperation Foundation of Yonsei University
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Industry Academic Cooperation Foundation of Yonsei University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67109—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67115—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0227—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using structural arrangements to control crystal growth, e.g. placement of grain filters

Definitions

  • the present invention relates to a method of crystallizing an amorphous silicon layer, and more particularly, to a method of forming an amorphous silicon layer and crystallizing the amorphous silicon layer into a polysilicon layer by locally applying energy to the amorphous silicon layer using heat, light, gas or plasma without deformation of a substrate due to temperature.
  • LCD liquid crystal display
  • OLED organic light emitting diode
  • an LCD device displays an image according to light transmittance changed due to movement of molecules of a liquid crystal material injected between two substrates, which have an electric field generating electrode, respectively, wherein the electrodes are formed on surfaces of the substrates disposed to face each other, and a voltage is applied to the electrodes to generate an electric field, thereby moving liquid crystal molecules.
  • Active matrix LCD displays including thin film transistors as switching devices turning on/off voltages by pixels, i.e., the smallest units for displaying an image, are in a main stream, and LCD devices employing thin film transistors using polysilicon (poly-Si) are being widely researched and developed in recent years.
  • poly-Si polysilicon
  • Poly-Si is generally formed by crystallizing amorphous silicon using solid phase crystallization (SPC), metal induced crystallization MIC) or excimer laser annealing (ELA).
  • SPC is a method of crystallizing amorphous silicon at high temperature, for example,
  • [8] MIC is a method of crystallizing amorphous silicon by depositing a metal thereon and applying heat thereto.
  • the metal serves to lower enthalpy of the amorphous silicon to be crystallized. Accordingly, although this method can be applied to a low temperature (approximately 500 0 C) process, the quality of the crystallized silicon surface is poor and an electrical characteristic thereof deteriorates due to the metal. Since this method also performs crystallization in a solid phase, a lot of defects generate in a grain.
  • ELA is an annealing method using a pulsed UV beam, excimer laser, which is the most widely used.
  • the annealing method using laser was first developed by Khaibullin in 1976, and then developed in order to anneal silicon into which impurity ions are injected in a large-scale integration (LSI) process. Thereafter, this method has been applied to development of large-scale display devices, and is recently applied to manufacturing small-to-medium scale low temperature polycrystalline silicon TFT-LCD products.
  • LSI large-scale integration
  • the ELA method has a problem in which since a laser beam is irradiated approximately 20 times while moving it little by little to get a large grain, the annealing process takes a long time.
  • sequential lateral solidification (SLS) was developed, which is a lateral growth technique using a slit mask.
  • a method of forming a crystallization seed by implanting silicon ions and a method of forming a crystallization seed by planting a metal in an amorphous silicon layer in a predetermined size are disclosed.
  • such methods also have problems in which crystallinity is poor, a process is complicated, a subsequent process is required or specially designed equipment is required.
  • heat having a temperature of at least 400 0 C applies to a substrate. In this case, a glass substrate can be seriously deformed, and a plastic substrate, which is weaker at high temperature than the glass substrate, cannot be actually used.
  • the ELA method which is the most widely used, is known to rarely damage a substrate due to performing a thermal treatment process in a short time, a certain amount of heat still transfers to the substrate even by this method. Accordingly, it is difficult to use a plastic substrate. Further, except for the deformation of the substrate, the ELA method is a high-cost process, thereby not producing devices with lower production cost. [17] For the problems described above, new technological developments are still eagerly required.
  • an object of the present invention is to provide an apparatus and method for forming a semiconductor layer in a selected region.
  • Another object of the present invention is to form a semiconductor layer capable of being used as an active layer on a substrate and minimize deformation of the substrate.
  • Still another object of the present invention is to form a semiconductor layer at low temperature and low cost.
  • Yet another object of the present invention is to provide a method of crystallizing an amorphous silicon layer by a low temperature process.
  • Still yet another object of the present invention is to provide a method of locally applying heat to an amorphous silicon layer grown on a plastic or glass substrate to crystallize.
  • a structure for crystallization includes: a board-shaped support disposed at a lower part thereof; and a plurality of projections having flat bottom surfaces, which project from the support and are spaced a predetermined distance apart from each other, wherein the flat bottom surfaces are set to a temperature higher than the support when the flat bottom surfaces are heated to a temperature by approaching an object.
  • a structure for crystallization includes: a board-shaped support disposed at a lower part thereof; and interconnections formed in a matrix having a first resistance and disposed on the board-shaped support, and a plurality of resistors selectively inserted into the interconnections to disconnect the interconnections, having flat bottom surfaces, and having a second resistance to be spaced a predetermined distance apart from each other, wherein the resistors generates heat as a voltage is applied to the interconnections, the generated heat is intensively applied to portions of an object at a predetermined interval, and the second resistance is higher than the first resistance.
  • a method of crystallizing an amorphous silicon layer includes the steps of: preparing a substrate on which an amorphous silicon layer is deposited; positioning a structure for crystallization to be in contact with or disposing the structure in a predetermined distance apart from a top surface of the amorphous silicon layer; and heating a plurality of regions having a predetermined area in the amorphous silicon layer at a higher temperature than other regions around the plurality of regions in the amorphous silicon layer by the structure to crystallize the predetermined regions of the amorphous silicon layer by changing a characteristic of the predetermined regions of the amorphous silicon layer.
  • the step of heating the plurality of regions in the amorphous silicon layer at a higher temperature than other regions around the plurality of regions in the amorphous silicon layer may comprise performing using the structure for crystallization including a board-shaped support disposed at a lower part thereof, and a plurality of projections having flat bottom surfaces, which project from the support and are spaced a predetermined distance apart from each other, wherein the flat bottom surfaces are set to a temperature higher than the support.
  • the step of heating the plurality of regions in the amorphous silicon layer at a higher temperature than other regions around the plurality of regions in the amorphous silicon layer may comprise performing using a board-shaped support disposed at a lower part thereof; and interconnections formed in a matrix having a first resistance and disposed on the board-shaped support, and a plurality of resistors se- lectively inserted into the interconnections to disconnect the interconnections, having flat bottom surfaces, and having a second resistance to be spaced a predetermined distance apart from each other, wherein the resistors generates heat as a voltage is applied to the interconnections, and the generated heat is intensively applied to portions of an object at a predetermined interval.
  • the step of heating the plurality of regions in the amorphous silicon layer at a higher temperature than other regions around the plurality of regions in the amorphous silicon layer may comprise preparing a mask exposing the plurality of regions on the amorphous silicon layer; and applying heat, light, gas or plasma to the exposed regions.
  • a method of forming a semiconductor active layer includes the steps of: forming a first semiconductor layer on a substrate; positioning a structure for crystallization to be in contact with or disposing the structure in a predetermined distance apart from a top surface of the first semiconductor layer; heating a plurality of selected regions having a predetermined area, in which active regions are formed in at least one portion of the first semiconductor layer, at a higher temperature than other regions around the selected regions by the structure to change a characteristic of the selected regions; and patterning at least one portion of the selected regions to form an active layer.
  • a method of manufacturing a thin film transistor includes the steps of: forming a semiconductor active layer; forming a gate insulating layer over the active layer; and forming a gate electrode, and source and drain electrodes over the gate insulating layer, the source and drain electrodes being connected to the active layer.
  • a method of manufacturing a thin film transistor may include the steps of: forming a gate electrode and a gate insulating layer on a substrate; forming a semiconductor active layer; forming a gate insulating layer over the active layer; and forming a gate electrode, and source and drain electrodes over the gate insulating layer, the source and drain electrodes being connected to the active layer.
  • the present invention it is possible to crystallize a channel region without deformation of a substrate by locally annealing a semiconductor layer (for example, an amorphous silicon layer) deposited on the flexible substrate and crystallizing the semiconductor layer.
  • a semiconductor layer for example, an amorphous silicon layer
  • crystallization temperature of amorphous silicon depends on the substrate.
  • a choice of the substrate is not limited, and the amorphous silicon is crystallized without deformation of the flexible substrate. Therefore, the present invention can be applied to manufacturing of an organic light emitting diode device and an electronic paper as next generation display devices.
  • FIGS. 1 and 2 are a perspective view and a cross-sectional view of a structure for crystallization according to an exemplary embodiment of the present invention, respectively.
  • FIG. 3 is a view illustrating a process of locally applying heat to a sample using a structure for crystallization according to an exemplary embodiment of the present invention.
  • FIG. 4 is another view illustrating the process of locally applying heat to a sample using a structure for crystallization according to the exemplary embodiment of the present invention.
  • FIG. 5 illustrates a different modified example of a structure for crystallization according to an exemplary embodiment of the present invention.
  • FIG. 6 is a view illustrating a process of locally applying heat to a sample using a structure for crystallization according to another exemplary embodiment of the present invention.
  • FIG. 7 is an enlarged view of an interconnection 320 and a resistor 330 of FIG. 6.
  • FIG. 8 is a view illustrating a method of crystallizing an amorphous silicon layer according to an exemplary embodiment of the present invention.
  • FIG. 9 is a view illustrating a method of crystallizing an amorphous silicon layer according to another exemplary embodiment of the present invention.
  • FIG. 10 is a view illustrating a method of crystallizing an amorphous silicon layer according to still another exemplary embodiment of the present invention.
  • FIG. 11 illustrates a mask for crystallization according to an exemplary embodiment of the present invention.
  • FIGS. 12 to 15 are cross-sectional views illustrating a process of manufacturing a thin film transistor by a crystallization method according to an exemplary embodiment of the present invention.
  • FIGS. 16 to 19 are cross-sectional views illustrating a process of manufacturing a thin film transistor by a crystallization method according to another exemplary embodiment of the present invention. Mode for the Invention
  • FIGS. 1 and 2 are a perspective view and a cross-sectional view of a structure for crystallization according to an exemplary embodiment of the present invention, respectively.
  • a structure for crystallization includes a board-shaped support 120 disposed at a lower part thereof, and a plurality of projections 110 having flat bottom surfaces S, which project from the support 120 and are spaced a predetermined distance apart from each other.
  • the structure for crystallization may include transparent regions in seme parts, and therein an alignment key 112 may be formed.
  • the structure further includes a blocking part 130 for preventing transmission of temperature to the other regions except the flat bottom surfaces S of the projection 110 in FIGS. 1 and 2, the blocking part 130 may be selectively added.
  • the flat bottom surfaces S when the flat bottom surfaces S are heated by approaching an object, the flat bottom surfaces S are set to a higher temperature than regions around the flat bottom surfaces S. Thus, when the structure approaches the substrate and is heated, only the flat bottom surfaces S can be locally heated. Thus, by a process of crystallizing an amorphous silicon layer formed on a substrate using such a structure for crystallization, an amount of heat transmitted to the entire substrate is reduced and only the flat bottom surfaces S are heated, and thus deformation of the entire substrate is significantly prevented. To this end, the exemplary embodiment emphasizes that temperature of the flat bottom surface S is set as high as possible but transmission of the temperature to the other regions except the flat bottom surfaces S should be effectively prevented.
  • a main body and projections of the support 120 are formed of the same material in FIGS. 1 and 2, they may be formed of different materials. In this case, it can be more effective that the main body has a lower resistance than the projection.
  • the flat bottom surface S of the projection may be set to a temperature of 200 to
  • 1500 0 C, and the other regions except the flat bottom surfaces S may be set to 200 0 C or less, preferably 100 0 C or less, and more preferably room temperature when the flat bottom surfaces S approach the object.
  • an area of the flat bottom surface S may be set enough to form a channel of a thin film transistor on the substrate.
  • the area of the flat bottom surface S has to include the area of the channel (e.g., 5/M X 20 IM), and may selectively include a source/drain contact area.
  • an area ratio of the flat bottom surfaces S to the entire substrate is 400/20000, that is, 2%. Accordingly, heated areas in the entire substrate are significantly small, so that the deformation of the entire substrate caused by local heating may be prevented. Thereby, a higher temperature may be applied to the local area.
  • the flat bottom surface S may have an area of 10/M to 2000/M , and preferably 10/M
  • the flat bottom surface S may be formed as small as possible, and have the smallest area to include a channel region.
  • a proper area ratio of the flat bottom surfaces S with respect to the entire substrate can be selected.
  • the area ratio of the flat bottom surfaces to the other regions may be 0.2% to 10%.
  • the lowest limit of the ratio depends on the smallest area of the flat bottom surface S, and the upper limit thereof corresponds to a ratio, which does not cause the deformation of the substrate.
  • the support 120 may be formed of any material, which does not transmit heat to the substrate more than necessary. While there are a variety of methods of applying heat to the flat bottom surfaces S of the projection, only the flat bottom surfaces S may generate heat by flowing current through a metal resistor such as a nichrome wire. IVbreover, amount and time of applying heat to the flat bottom surfaces S can be adjusted, and metals forming the flat bottom surfaces S may be various metals in addition to a resistance heater such as nichrome.
  • the blocking part 130 is surrounded by a dielectric layer having low thermal conductivity around the projections 110 to selectively apply heat to only the projections 110 having the flat bottom surfaces S.
  • the blocking part 130 may be spaced apart from the support 120 to reduce heat transmission.
  • this process is performed in a vacuum chamber, when the blocking part 130 is supported by the support 120, spaced apart therefrom, the heat transmission to the other regions except the flat bottom surfaces S of the projections 110 may be effectively prevented.
  • the blocking part 130 may be formed of a plurality of pieces of sheet, which are spaced apart from each other.
  • the support 110 may be formed of a transparent material to easily form an alignment key thereon, or partially formed of a transparent material to form an alignment key in the transparent part.
  • FIG. 3 is a view illustrating a process of locally applying heat to a sample using a structure for crystallization according to an exemplary embodiment of the present invention.
  • a substrate 155 is prepared, on which an amorphous silicon layer is formed to a thickness of several mm.
  • the amorphous silicon layer may be formed by any deposition method such as a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method or a method using an organic solvent.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • the substrate may be formed of plastic, glass, silicon, or a transparent material such as quartz or sapphire.
  • this embodiment has a characteristic effect of minimizing thermal deformation of the substrate, and therefore a plastic substrate which needs a low temperature process will be a better option.
  • a flat bottom surface of a projection to which heat is applied may be in contact with or spaced a predetermined distance apart from an amorphous silicon layer for predetermined time in order to locally crystallize the amorphous silicon layer.
  • the crystallization process may be performed in a vacuum chamber 180 to protect the silicon layer from reacting with impurities, and a desired gas may be applied through a gas inlet if necessary.
  • a sensor for checking a phase of silicon in real-time may be installed, and an apparatus for directly monitoring a side surface making a contact may be installed in some cases.
  • a heater 165 may be installed.
  • FIG. 4 is another view illustrating a process of locally applying heat to a sample using a structure for crystallization according to an exemplary embodiment of the present invention.
  • a blocking part 135 is not fixed to projections 130, but separated from each other.
  • the blocking part 135 may be disposed to cover an entire sample, or disposed over a part of a substrate. According to the structure illustrated in FIG. 4, it has an advantage that the projections 130 may be automatically aligned over the sample through guide holes in the blocking part 135 after the blocking part 135 and the sample are properly disposed.
  • FIG. 5 illustrates another example of a structure for crystallization according to an exemplary embodiment.
  • FIG. 6 is a view illustrating a process of locally applying heat to a sample using a structure for crystallization according to another exemplary embodiment of the present invention.
  • a structure for crystallization includes a board-shaped support
  • the resistor 330 generates heat as a voltage is applied to the interconnection 320, and thus transmits concentrated heat to an object at a predetermined distance.
  • the second resistance is set higher than the first resistance.
  • FIG. 7 is an enlarged view of the interconnection 320 and the resistor 330 of FIG. 6.
  • the interconnection 320 may be formed of any material, which is not specified, but preferably a low resistance material.
  • FIG. 8 is a view illustrating a process of crystallizing an amorphous silicon layer according to an exemplary embodiment of the present invention.
  • a sample having an amorphous silicon layer thereon is prepared, and a mask for crystallization 445 is disposed on the sample, which exposes a plurality of regions of the prepared sample.
  • Light of a lamp 480 is passed through the exposed regions, so that the plurality of regions having a predetermined area are heated to a higher temperature than the surrounding thereof.
  • the crystallization mask 445 used to apply heat to a desired portion of the amorphous silicon layer may be formed in any size, and may form a hole therethrough in any size and shape according to a channel of a thin film transistor.
  • the crystallization mask 445 may be formed of a light- shielding material.
  • An alignment key may be formed to dispose the crystallization mask 445 on the underlying substrate. In the case of a metal mask, the key may be formed by directly punching the mask, and in the case of a transparent mask, the key may be painted with an opaque color. In this case, only the region having the alignment key is transparent as described above.
  • the lamp 480 may be a halogen lamp or a xeon lamp, and the lamp, the mask and the sample may be covered not to penetrate light into a chamber.
  • a phase change sensor may be installed, and to observe an effect according to an injected gas, an apparatus for freely applying gas may be installed.
  • FIG. 9 is a view illustrating a process of crystallizing an amorphous silicon layer according to another exemplary embodiment of the present invention.
  • FIG. 9 shows a structure having a gas provider, instead of the lamp of FIG. 8.
  • a gas provider instead of the lamp of FIG. 8.
  • an inert gas such as nitrogen or argon
  • a heater is installed to apply heat behind gas, and the gas expanded by heat is sprayed through a nozzle, thereby applying heat to the amorphous silicon layer.
  • a mask has to be used, and the heated portion is very small, so there is no problem with a plastic substrate, which is sensitive to heat.
  • FIG. 10 is a view illustrating a process of crystallizing an amorphous silicon layer according to still another exemplary embodiment of the present invention.
  • FIG. 10 shows a structure having a plasma generator 650 instead of the lamp of FIG.
  • the plasma generator 650 is used to irradiate plasma to a prepared thin film to provide energy, thereby crystallizing an amorphous silicon layer.
  • An inert gas preferably argon
  • An inert gas is filled between copper and tungsten, and then high DC voltage is applied thereto, plasma is generated due to gas breakdown.
  • the generated plasma is exhausted through a hole under the generator by high expansive force.
  • heat generated from copper is cooled down by cooling water.
  • the plasma may be processed at low temperature, so that a plastic substrate cannot be deformed. Meanwhile, to attenuate obstacles to moving plasma to a silicon thin film, the process may be performed in vacuum equipment having a vacuum level of 10 Torr or less.
  • a plasma generator has to be very large. For this reason, a method of applying plasma to a mask disposed over a silicon thin film using the limited-sized plasma generator may be used.
  • a principle of generating plasma is the same as described above, and the entire silicon thin film has to be scanned while plasma is generated. The plasma is provided only to a hole in the mask, so that only a desired part of the silicon thin film may be crystallized.
  • the crystallization may be performed by applying an electric field or a magnetic field, or heating a substrate to a predetermined temperature.
  • the method of applying a magnetic field may uniformly crystallize the entire substrate since the uniform magnetic field can be applied due to the nature of the magnetic field, and thus the crystallization may be more effectively performed by applying the magnetic field before or after the crystallization method as described above, or by a different method together with the application of the magnetic field.
  • FIG. 11 illustrates another sample of a crystallization mask according to an exemplary embodiment of the present invention.
  • the crystallization mask includes a main body 710, an opening 730, and an alignment key 720.
  • the alignment key 720 is formed in a transparent region, and the main body 710 may be formed in a non- transmissive region. Light, heat, gas and plasma may pass through the opening 730 using the mask for crystallization.
  • FIGS. 12 to 15 are cross-sectional views illustrating a process of manufacturing a thin film transistor using a crystallization method according to an exemplary embodiment of the present invention.
  • a substrate 800 is prepared, and a buffer layer 810 and an amorphous silicon layer 820 are formed thereon.
  • a type of the substrate 800 is not limited, for example, which may be a glass substrate, a plastic substrate or a flexible substrate.
  • the buffer layer 810 serves to prevent crystallized silicon from being contaminated by impurities contained in the substrate 800 when the amorphous silicon layer 820 is deposited and crystallized into a polycrystalline silicon layer in a subsequent process. Accordingly, the buffer layer 810 can be omitted in some cases.
  • the buffer layer 810 may be an insulating layer, which may be formed of any insulating material known in the art, for example, silicon oxide or silicon nitride using plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the buffer layer 810 may be formed to a thickness of 1000 to IOOOOA and preferably 2000 to 5000A.
  • the amorphous silicon layer 820 is formed on the buffer layer. That is, the amorphous silicon layer 820 may be formed on the buffer layer 810 by depositing monosilane (SiH ), as a source gas, diluted with argon (Ar) gas using PECVD. The amorphous silicon layer 820 may be formed to a thickness of 300 to 2000A and preferably approximately 500A. [87] Then, a structure for crystallization including a support 840 and projections 850 having flat bottom surfaces is aligned to the substrate 800. [88] Referring to FIG. 13, heat is applied to the aligned projections 850 to crystallize regions of the amorphous silicon layer 820 which correspond to the projections 850.
  • SiH monosilane
  • Ar argon
  • FIG. 13 simply illustrates the crystallization of the amorphous silicon layer by heating the projections, it can be clearly understood that the amorphous silicon layer may be partially crystallized by any method described above.
  • FIG. 14 is a plan view illustrating crystallization after the process of FIG. 13 is completed. A heated portion corresponds to a channel of the thin film transistor. As described above, only the channels can be crystallized without deformation of the substrate by such local heating. [90] A process of manufacturing a thin film transistor will now be described. A channel
  • a gate insulating layer 50 having a predetermined thickness is formed.
  • the gate insulating layer is generally formed to a thickness of 500 to 2000A.
  • a gate electrode 70 is formed on the gate insulating layer 50. Then, predetermined regions of the active layer are doped with n+ type and p+ type ions using the gate electrode 70 as a mask to form a source and a drain, respectively.
  • the gate electrode 70 is formed on the gate insulating layer 50. Then, predetermined regions of the active layer are doped with n+ type and p+ type ions using the gate electrode 70 as a mask to form a source and a drain, respectively.
  • an interlayer insulating layer 60 is formed on the gate electrode 70 and patterned, thereby forming a contact, and a metal layer 80 is deposited and patterned to connect the source and drain of the active layer to data lines through the contact.
  • the interlayer insulating layer 60 may be formed to a thickness of 2000 to 8000A.
  • an n- or p-type polysilicon thin film transistor may be formed by the above-described process, and a known lightly-doped drain (LDD) structure may be applied to this embodiment.
  • the LDD structure is completed by lightly doping using the gate electrode 70 as a doping mask, by forming a spacer or photoresist, which can serve as a doping mask at one or both sides of the gate electrode 70 using a spacer process, and then by highly doping the spacer and photoresist as masks to form a source or drain electrode.
  • FIGS. 16 to 19 are cross-sectional views illustrating a process of manufacturing a thin film transistor using a crystallization method according to another exemplary embodiment of the present invention.
  • an electrode layer is formed on a substrate 920, and etched to form a gate electrode 910.
  • a gate insulating layer 922, an amorphous silicon layer 924 and an n+ doped amorphous silicon layer 926 are sequentially formed over the gate electrode 910 by a known method such as PECVD. Then, a structure for crystallization including a support 940 and projections 950 having flat bottom surfaces is aligned over the substrate 920. Here, the structure for crystallization may be aligned using a pattern having the gate electrode 910.
  • FIG. 17 shows that the gate insulating layer 922, the amorphous silicon layer 924 and the n+ doped amorphous silicon layer 926 are sequentially formed over the gate electrode 910 and then crystallized, in seme cases, the gate insulating layer 922 and the amorphous silicon layer 924 may be sequentially deposited and then crystallized.
  • the n+ doped amorphous silicon layer 926 may be deposited over the crystallized silicon layer.
  • a conductive layer is formed to form a source and a drain connected to an active layer on the above structure, and then patterned, thereby forming source and drain electrodes 930.
  • An interlayer insulating layer is formed on the electrodes.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention fournit une structure de cristallisation, un procédé de cristallisation utilisant celle-ci, un procédé de formation d'une couche active semi-conductrice, et un procédé de fabrication de transistor à film mince. La structure de cristallisation comprend un support en forme de carte disposé au niveau d'une partie inférieure de celle-ci ; et une pluralité de saillies ayant des surfaces inférieures plates, qui font saillie à partir du support et sont espacées d'une distance prédéterminée les unes des autres, les surfaces inférieures plates étant fixées à une température plus élevée que le support lorsque les surfaces inférieures plates sont chauffées à une température en approchant un objet.
PCT/KR2008/000161 2007-05-30 2008-01-10 Structure de cristallisation, procédé de cristallisation, procédé de formation d'une couche active d'une couche de silicium amorphe semi-conducteur, et procédé de fabrication d'un transistor à film mince utilisant celle-ci Ceased WO2008147012A1 (fr)

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KR1020070052852A KR101336455B1 (ko) 2007-05-30 2007-05-30 결정화용 구조물, 이를 이용한 결정화 방법, 반도체 활성층형성방법 및 박막트랜지스터 형성방법 이를 이용한 박막트랜지스터의 제조방법
KR10-2007-0052852 2007-05-30

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WO2008147012A1 true WO2008147012A1 (fr) 2008-12-04

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10270363A (ja) * 1997-03-27 1998-10-09 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
KR20060007521A (ko) * 2004-07-20 2006-01-26 비오이 하이디스 테크놀로지 주식회사 다결정실리콘막 형성방법
US20060054896A1 (en) * 2002-05-22 2006-03-16 Van Der Zaag Pieter J Active matrix display devices and the manufacture thereof
US20060154452A1 (en) * 2005-01-08 2006-07-13 Jal-Yong Han Silicon film, crystalline film and method for manufacturing the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3458953B2 (ja) 2000-07-27 2003-10-20 洋太郎 畑村 マイクロチップのアライメント装置及びアライメント方法
JP2002237375A (ja) 2000-12-05 2002-08-23 Ibiden Co Ltd 半導体製造・検査装置用セラミック基板およびその製造方法
JP5055756B2 (ja) 2005-09-21 2012-10-24 東京エレクトロン株式会社 熱処理装置及び記憶媒体

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10270363A (ja) * 1997-03-27 1998-10-09 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US20060054896A1 (en) * 2002-05-22 2006-03-16 Van Der Zaag Pieter J Active matrix display devices and the manufacture thereof
KR20060007521A (ko) * 2004-07-20 2006-01-26 비오이 하이디스 테크놀로지 주식회사 다결정실리콘막 형성방법
US20060154452A1 (en) * 2005-01-08 2006-07-13 Jal-Yong Han Silicon film, crystalline film and method for manufacturing the same

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