WO2008147012A1

WO2008147012A1 - Structure for crystallization, method of crystallization, method of forming active layer of semiconductor amorphous silicon layer, and manufacturing method of thin film transistor using the same

Info

Publication number: WO2008147012A1
Application number: PCT/KR2008/000161
Authority: WO
Inventors: Tae Hoon Jeong; Hyun Jae Kim; Choong Hee Lee
Original assignee: Industry Academic Cooperation Foundation of Yonsei University
Current assignee: Industry Academic Cooperation Foundation of Yonsei University
Priority date: 2007-05-30
Filing date: 2008-01-10
Publication date: 2008-12-04
Anticipated expiration: 2009-11-30
Also published as: KR101336455B1; KR20080105362A

Abstract

Provided are a structure for crystallization, a crystallization method using the same, a method of forming a semiconductor active layer, and a method of manufacturing a thin film transistor. The structure for crystallization includes: a board-shaped support disposed at a lower part thereof; and a plurality of projections having flat bottom surfaces, which project from the support and are spaced a predetermined distance apart from each other, wherein the flat bottom surfaces are set to a temperature higher than the support when the flat bottom surfaces are heated to a temperature by approaching an object.

Description

STRUCTURE FOR CRYSTALLIZATION, METHOD OF CRYSTALLIZATION, METHOD OF FORMING ACTIVE LAYER OF SEMICONDUCTOR AMORPHOUS SILICON LAYER, AND MANUFACTURING METHOD OF THIN

FILM TRANSISTOR USING THE SAME Technical Field

[1] The present invention relates to a method of crystallizing an amorphous silicon layer, and more particularly, to a method of forming an amorphous silicon layer and crystallizing the amorphous silicon layer into a polysilicon layer by locally applying energy to the amorphous silicon layer using heat, light, gas or plasma without deformation of a substrate due to temperature. Background Art

[2] With rapid development of the information society, importance of thin, lightweight and low power consumption flat panel displays has increased, and thus liquid crystal display (LCD) devices, organic light emitting diode (OLED) devices and electronic paper display devices are being actively developed in recent times.

[3] Generally, an LCD device displays an image according to light transmittance changed due to movement of molecules of a liquid crystal material injected between two substrates, which have an electric field generating electrode, respectively, wherein the electrodes are formed on surfaces of the substrates disposed to face each other, and a voltage is applied to the electrodes to generate an electric field, thereby moving liquid crystal molecules.

[4] Active matrix LCD displays including thin film transistors as switching devices turning on/off voltages by pixels, i.e., the smallest units for displaying an image, are in a main stream, and LCD devices employing thin film transistors using polysilicon (poly-Si) are being widely researched and developed in recent years.

[5] In the LCD device using poly-Si, since a thin film transistor and a driving circuit are formed on the same substrate and a process of connecting the film transistor to the driving circuit is not required, the manufacturing process is simplified. Further, since poly-Si has a field effect mobility, which is 100 to 200 times higher than mobility of amorphous silicon, the LCD device using poly-Si has fast response time and high stability to temperature and light. [6] Poly-Si is generally formed by crystallizing amorphous silicon using solid phase crystallization (SPC), metal induced crystallization MIC) or excimer laser annealing (ELA).

[7] SPC is a method of crystallizing amorphous silicon at high temperature, for example,

600⁰C. This method performs crystallization in a solid phase, so that grains have a lot of defects, resulting in low crystallinity. To make up for this drawback, a thermal oxide layer formed at high temperature (~1000°C) is used as a gate insulating layer. Accordingly, there is a problem in which an expensive material such as crystal, which is endurable at 1000⁰C or more, has to be used.

[8] MIC is a method of crystallizing amorphous silicon by depositing a metal thereon and applying heat thereto. Here, the metal serves to lower enthalpy of the amorphous silicon to be crystallized. Accordingly, although this method can be applied to a low temperature (approximately 500⁰C) process, the quality of the crystallized silicon surface is poor and an electrical characteristic thereof deteriorates due to the metal. Since this method also performs crystallization in a solid phase, a lot of defects generate in a grain.

[9] ELA is an annealing method using a pulsed UV beam, excimer laser, which is the most widely used. The annealing method using laser was first developed by Khaibullin in 1976, and then developed in order to anneal silicon into which impurity ions are injected in a large-scale integration (LSI) process. Thereafter, this method has been applied to development of large-scale display devices, and is recently applied to manufacturing small-to-medium scale low temperature polycrystalline silicon TFT-LCD products.

[10] The method of forming a high-quality poly-Si layer by annealing amorphous silicon layer using laser is the most promising technique, which does not damage a substrate since the silicon is shortly annealed even though it has a high melting point, and

2 ensures mobility of a manufactured thin film transistor of 100cm /Vsec or more.

[11] However, the ELA method has a problem in which since a laser beam is irradiated approximately 20 times while moving it little by little to get a large grain, the annealing process takes a long time. To get a larger grain rapidly, sequential lateral solidification (SLS) was developed, which is a lateral growth technique using a slit mask.

[12] Since these conventional methods still have a variety of problems, various efforts to find an effective method of crystallizing an amorphous silicon layer into a polysilicon layer are being made.

[13] As parts of such endeavors, for example, a method of forming a crystallization seed by implanting silicon ions and a method of forming a crystallization seed by planting a metal in an amorphous silicon layer in a predetermined size are disclosed. [14] However, such methods also have problems in which crystallinity is poor, a process is complicated, a subsequent process is required or specially designed equipment is required. [15] Moreover, in the SPC and MIC methods, heat having a temperature of at least 400⁰C applies to a substrate. In this case, a glass substrate can be seriously deformed, and a plastic substrate, which is weaker at high temperature than the glass substrate, cannot be actually used. [16] Although the ELA method, which is the most widely used, is known to rarely damage a substrate due to performing a thermal treatment process in a short time, a certain amount of heat still transfers to the substrate even by this method. Accordingly, it is difficult to use a plastic substrate. Further, except for the deformation of the substrate, the ELA method is a high-cost process, thereby not producing devices with lower production cost. [17] For the problems described above, new technological developments are still eagerly required.

Disclosure of Invention

Technical Problem [18] To solve the above-described problems, an object of the present invention is to provide an apparatus and method for forming a semiconductor layer in a selected region. [19] Another object of the present invention is to form a semiconductor layer capable of being used as an active layer on a substrate and minimize deformation of the substrate. [20] Still another object of the present invention is to form a semiconductor layer at low temperature and low cost. [21] Yet another object of the present invention is to provide a method of crystallizing an amorphous silicon layer by a low temperature process. [22] Still yet another object of the present invention is to provide a method of locally applying heat to an amorphous silicon layer grown on a plastic or glass substrate to crystallize.

Technical Solution [23] As technical means in order to solve the above-described problems, in a first aspect of the present invention, a structure for crystallization includes: a board-shaped support disposed at a lower part thereof; and a plurality of projections having flat bottom surfaces, which project from the support and are spaced a predetermined distance apart from each other, wherein the flat bottom surfaces are set to a temperature higher than the support when the flat bottom surfaces are heated to a temperature by approaching an object.

[24] In a second aspect of the present invention, a structure for crystallization includes: a board-shaped support disposed at a lower part thereof; and interconnections formed in a matrix having a first resistance and disposed on the board-shaped support, and a plurality of resistors selectively inserted into the interconnections to disconnect the interconnections, having flat bottom surfaces, and having a second resistance to be spaced a predetermined distance apart from each other, wherein the resistors generates heat as a voltage is applied to the interconnections, the generated heat is intensively applied to portions of an object at a predetermined interval, and the second resistance is higher than the first resistance.

[25] In a third aspect of the present invention, a method of crystallizing an amorphous silicon layer includes the steps of: preparing a substrate on which an amorphous silicon layer is deposited; positioning a structure for crystallization to be in contact with or disposing the structure in a predetermined distance apart from a top surface of the amorphous silicon layer; and heating a plurality of regions having a predetermined area in the amorphous silicon layer at a higher temperature than other regions around the plurality of regions in the amorphous silicon layer by the structure to crystallize the predetermined regions of the amorphous silicon layer by changing a characteristic of the predetermined regions of the amorphous silicon layer.

[26] The step of heating the plurality of regions in the amorphous silicon layer at a higher temperature than other regions around the plurality of regions in the amorphous silicon layer may comprise performing using the structure for crystallization including a board-shaped support disposed at a lower part thereof, and a plurality of projections having flat bottom surfaces, which project from the support and are spaced a predetermined distance apart from each other, wherein the flat bottom surfaces are set to a temperature higher than the support.

[27] Alternatively, the step of heating the plurality of regions in the amorphous silicon layer at a higher temperature than other regions around the plurality of regions in the amorphous silicon layer may comprise performing using a board-shaped support disposed at a lower part thereof; and interconnections formed in a matrix having a first resistance and disposed on the board-shaped support, and a plurality of resistors se- lectively inserted into the interconnections to disconnect the interconnections, having flat bottom surfaces, and having a second resistance to be spaced a predetermined distance apart from each other, wherein the resistors generates heat as a voltage is applied to the interconnections, and the generated heat is intensively applied to portions of an object at a predetermined interval.

[28] Further, the step of heating the plurality of regions in the amorphous silicon layer at a higher temperature than other regions around the plurality of regions in the amorphous silicon layer may comprise preparing a mask exposing the plurality of regions on the amorphous silicon layer; and applying heat, light, gas or plasma to the exposed regions.

[29] In a fourth aspect of the present invention, a method of forming a semiconductor active layer includes the steps of: forming a first semiconductor layer on a substrate; positioning a structure for crystallization to be in contact with or disposing the structure in a predetermined distance apart from a top surface of the first semiconductor layer; heating a plurality of selected regions having a predetermined area, in which active regions are formed in at least one portion of the first semiconductor layer, at a higher temperature than other regions around the selected regions by the structure to change a characteristic of the selected regions; and patterning at least one portion of the selected regions to form an active layer.

[30] In a fifth aspect of the present invention, a method of manufacturing a thin film transistor includes the steps of: forming a semiconductor active layer; forming a gate insulating layer over the active layer; and forming a gate electrode, and source and drain electrodes over the gate insulating layer, the source and drain electrodes being connected to the active layer.

[31] In a sixth aspect of the present invention, a method of manufacturing a thin film transistor may include the steps of: forming a gate electrode and a gate insulating layer on a substrate; forming a semiconductor active layer; forming a gate insulating layer over the active layer; and forming a gate electrode, and source and drain electrodes over the gate insulating layer, the source and drain electrodes being connected to the active layer.

Advantageous Effects

[32] According to the present invention, it is possible to crystallize a channel region without deformation of a substrate by locally annealing a semiconductor layer (for example, an amorphous silicon layer) deposited on the flexible substrate and crystallizing the semiconductor layer. [33] Conventionally, crystallization temperature of amorphous silicon depends on the substrate. However, because of the local annealing process, a choice of the substrate is not limited, and the amorphous silicon is crystallized without deformation of the flexible substrate. Therefore, the present invention can be applied to manufacturing of an organic light emitting diode device and an electronic paper as next generation display devices.

Brief Description of the Drawings [34] FIGS. 1 and 2 are a perspective view and a cross-sectional view of a structure for crystallization according to an exemplary embodiment of the present invention, respectively. [35] FIG. 3 is a view illustrating a process of locally applying heat to a sample using a structure for crystallization according to an exemplary embodiment of the present invention. [36] FIG. 4 is another view illustrating the process of locally applying heat to a sample using a structure for crystallization according to the exemplary embodiment of the present invention. [37] FIG. 5 illustrates a different modified example of a structure for crystallization according to an exemplary embodiment of the present invention. [38] FIG. 6 is a view illustrating a process of locally applying heat to a sample using a structure for crystallization according to another exemplary embodiment of the present invention.

[39] FIG. 7 is an enlarged view of an interconnection 320 and a resistor 330 of FIG. 6.

[40] FIG. 8 is a view illustrating a method of crystallizing an amorphous silicon layer according to an exemplary embodiment of the present invention. [41] FIG. 9 is a view illustrating a method of crystallizing an amorphous silicon layer according to another exemplary embodiment of the present invention. [42] FIG. 10 is a view illustrating a method of crystallizing an amorphous silicon layer according to still another exemplary embodiment of the present invention. [43] FIG. 11 illustrates a mask for crystallization according to an exemplary embodiment of the present invention. [44] FIGS. 12 to 15 are cross-sectional views illustrating a process of manufacturing a thin film transistor by a crystallization method according to an exemplary embodiment of the present invention. [45] FIGS. 16 to 19 are cross-sectional views illustrating a process of manufacturing a thin film transistor by a crystallization method according to another exemplary embodiment of the present invention. Mode for the Invention

[46] Hereinafter, exemplary embodiments of the present invention will be described in detail. However, the present invention is not limited to the exemplary embodiments disclosed below, but can be implemented in various types. Therefore, the present exemplary embodiments are provided for complete disclosure of the present invention and to fully inform the scope of the present invention to those ordinarily skilled in the art. In the drawings, like reference numerals denote like elements, and thus descriptions of repeated elements will be emitted.

[47] (Structure for selective crystallization)

[48] FIGS. 1 and 2 are a perspective view and a cross-sectional view of a structure for crystallization according to an exemplary embodiment of the present invention, respectively.

[49] Referring to FIGS. 1 and 2, a structure for crystallization includes a board-shaped support 120 disposed at a lower part thereof, and a plurality of projections 110 having flat bottom surfaces S, which project from the support 120 and are spaced a predetermined distance apart from each other. Alternatively, the structure for crystallization may include transparent regions in seme parts, and therein an alignment key 112 may be formed.

[50] Although the structure further includes a blocking part 130 for preventing transmission of temperature to the other regions except the flat bottom surfaces S of the projection 110 in FIGS. 1 and 2, the blocking part 130 may be selectively added.

[51] In the structure for crystallization, when the flat bottom surfaces S are heated by approaching an object, the flat bottom surfaces S are set to a higher temperature than regions around the flat bottom surfaces S. Thus, when the structure approaches the substrate and is heated, only the flat bottom surfaces S can be locally heated. Thus, by a process of crystallizing an amorphous silicon layer formed on a substrate using such a structure for crystallization, an amount of heat transmitted to the entire substrate is reduced and only the flat bottom surfaces S are heated, and thus deformation of the entire substrate is significantly prevented. To this end, the exemplary embodiment emphasizes that temperature of the flat bottom surface S is set as high as possible but transmission of the temperature to the other regions except the flat bottom surfaces S should be effectively prevented.

[52] Accordingly, while a main body and projections of the support 120 are formed of the same material in FIGS. 1 and 2, they may be formed of different materials. In this case, it can be more effective that the main body has a lower resistance than the projection.

[53] The flat bottom surface S of the projection may be set to a temperature of 200 to

1500⁰C, and the other regions except the flat bottom surfaces S may be set to 200⁰C or less, preferably 100⁰C or less, and more preferably room temperature when the flat bottom surfaces S approach the object.

[54] Moreover, to more easily achieve the effect of the present invention, a plan for setting an area ratio of the flat bottom surfaces S to the other regions is needed. First, an area of the flat bottom surface S may be set enough to form a channel of a thin film transistor on the substrate. For example, when one pixel has an area of 100/M X 200/M, the area of the flat bottom surface S has to include the area of the channel (e.g., 5/M X 20 IM), and may selectively include a source/drain contact area. In this case, when the area of the flat bottom surface is set to 20/M X 20/M, in a region where a pixel is formed (not a peripheral circuit region), an area ratio of the flat bottom surfaces S to the entire substrate is 400/20000, that is, 2%. Accordingly, heated areas in the entire substrate are significantly small, so that the deformation of the entire substrate caused by local heating may be prevented. Thereby, a higher temperature may be applied to the local area.

2 2

[55] The flat bottom surface S may have an area of 10/M to 2000/M , and preferably 10/M

2 2 to 500/M to include the size of the channel. If the flat bottom surface is equal to or

2 smaller than 10/M , it cannot be generally used as a channel, and if the flat bottom surface is equal to or larger than 200/M , the entire substrate may be deformed a bit. Accordingly, to minimize the deformation of the substrate, the flat bottom surface S may be formed as small as possible, and have the smallest area to include a channel region.

[56] Meanwhile, to reduce the deformation of the substrate, a proper area ratio of the flat bottom surfaces S with respect to the entire substrate can be selected. The area ratio of the flat bottom surfaces to the other regions may be 0.2% to 10%. The lowest limit of the ratio depends on the smallest area of the flat bottom surface S, and the upper limit thereof corresponds to a ratio, which does not cause the deformation of the substrate.

[57] The support 120 may be formed of any material, which does not transmit heat to the substrate more than necessary. While there are a variety of methods of applying heat to the flat bottom surfaces S of the projection, only the flat bottom surfaces S may generate heat by flowing current through a metal resistor such as a nichrome wire. IVbreover, amount and time of applying heat to the flat bottom surfaces S can be adjusted, and metals forming the flat bottom surfaces S may be various metals in addition to a resistance heater such as nichrome.

[58] The blocking part 130 is surrounded by a dielectric layer having low thermal conductivity around the projections 110 to selectively apply heat to only the projections 110 having the flat bottom surfaces S. The blocking part 130 may be spaced apart from the support 120 to reduce heat transmission. Generally, since this process is performed in a vacuum chamber, when the blocking part 130 is supported by the support 120, spaced apart therefrom, the heat transmission to the other regions except the flat bottom surfaces S of the projections 110 may be effectively prevented. Also, it will be more effective that the blocking part 130 may be formed of a plurality of pieces of sheet, which are spaced apart from each other.

[59] By the way, the support 110 may be formed of a transparent material to easily form an alignment key thereon, or partially formed of a transparent material to form an alignment key in the transparent part.

[60] FIG. 3 is a view illustrating a process of locally applying heat to a sample using a structure for crystallization according to an exemplary embodiment of the present invention.

[61] For example, a substrate 155 is prepared, on which an amorphous silicon layer is formed to a thickness of several mm. The amorphous silicon layer may be formed by any deposition method such as a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method or a method using an organic solvent. Kinds of the substrate are not limited, and the substrate may be formed of plastic, glass, silicon, or a transparent material such as quartz or sapphire. However, this embodiment has a characteristic effect of minimizing thermal deformation of the substrate, and therefore a plastic substrate which needs a low temperature process will be a better option.

[62] A flat bottom surface of a projection to which heat is applied may be in contact with or spaced a predetermined distance apart from an amorphous silicon layer for predetermined time in order to locally crystallize the amorphous silicon layer. The crystallization process may be performed in a vacuum chamber 180 to protect the silicon layer from reacting with impurities, and a desired gas may be applied through a gas inlet if necessary. For the crystallization of the amorphous silicon layer, a sensor for checking a phase of silicon in real-time may be installed, and an apparatus for directly monitoring a side surface making a contact may be installed in some cases. Also, to directly apply heat to a bottom of the amorphous silicon layer, a heater 165 may be installed.

[63] FIG. 4 is another view illustrating a process of locally applying heat to a sample using a structure for crystallization according to an exemplary embodiment of the present invention.

[64] Referring to FIG. 4, while there is not much difference from the process illustrated in

FIG. 3, a blocking part 135 is not fixed to projections 130, but separated from each other. The blocking part 135 may be disposed to cover an entire sample, or disposed over a part of a substrate. According to the structure illustrated in FIG. 4, it has an advantage that the projections 130 may be automatically aligned over the sample through guide holes in the blocking part 135 after the blocking part 135 and the sample are properly disposed.

[65] While, in FIGS. 3 and 4, one piston has a plurality of projections, each piston may have a single projection. Accordingly, FIG. 5 illustrates another example of a structure for crystallization according to an exemplary embodiment.

[66] FIG. 6 is a view illustrating a process of locally applying heat to a sample using a structure for crystallization according to another exemplary embodiment of the present invention.

[67] Referring to FIG. 6, a structure for crystallization includes a board-shaped support

310 disposed at a lower part thereof, and a resistor, interconnections 320 formed in a matrix and having a first resistance, and a plurality of resistors 330 inserted between the interconnections 320 to disconnect the interconnections 320, having flat bottom surfaces, and having a second resistance to be spaced a predetermined distance apart from each other. For this structure, the resistor 330 generates heat as a voltage is applied to the interconnection 320, and thus transmits concentrated heat to an object at a predetermined distance. At this time, the second resistance is set higher than the first resistance.

[68] FIG. 7 is an enlarged view of the interconnection 320 and the resistor 330 of FIG. 6.

Referring to FIG. 7, when a voltage is applied to the interconnection 320, the resistor 330 generates heat by Joule heating, but the interconnection 320 scarcely generates heat. The principle of Joule heating is explained by using SiC having high resistance as

2 a resistor by Ohm s law P=IV=I R and calculating resistance of the single SiC by reactive ion etching (RIE; etching rate: SiC 200nm/min), wherein the resistance of the sin ¹Cgl¹e SiC is as follows.

[70] As a result, when a voltage is applied to the interconnection 320, mostly the voltage is applied to the resistor 330 to generate heat. The interconnection 320 may be formed of any material, which is not specified, but preferably a low resistance material.

[71] FIG. 8 is a view illustrating a process of crystallizing an amorphous silicon layer according to an exemplary embodiment of the present invention.

[72] Referring to FIG. 8, a sample having an amorphous silicon layer thereon is prepared, and a mask for crystallization 445 is disposed on the sample, which exposes a plurality of regions of the prepared sample. Light of a lamp 480 is passed through the exposed regions, so that the plurality of regions having a predetermined area are heated to a higher temperature than the surrounding thereof.

[73] The crystallization mask 445 used to apply heat to a desired portion of the amorphous silicon layer may be formed in any size, and may form a hole therethrough in any size and shape according to a channel of a thin film transistor. The crystallization mask 445 may be formed of a light- shielding material. An alignment key may be formed to dispose the crystallization mask 445 on the underlying substrate. In the case of a metal mask, the key may be formed by directly punching the mask, and in the case of a transparent mask, the key may be painted with an opaque color. In this case, only the region having the alignment key is transparent as described above.

[74] The lamp 480 may be a halogen lamp or a xeon lamp, and the lamp, the mask and the sample may be covered not to penetrate light into a chamber. Here, to check a phase change of the sample, a phase change sensor may be installed, and to observe an effect according to an injected gas, an apparatus for freely applying gas may be installed.

[75] FIG. 9 is a view illustrating a process of crystallizing an amorphous silicon layer according to another exemplary embodiment of the present invention.

[76] FIG. 9 shows a structure having a gas provider, instead of the lamp of FIG. 8. There is no limitation to the gas to be used, but an inert gas, such as nitrogen or argon, may be used. A heater is installed to apply heat behind gas, and the gas expanded by heat is sprayed through a nozzle, thereby applying heat to the amorphous silicon layer. As in FIG. 8, to provide heat to a desired portion, a mask has to be used, and the heated portion is very small, so there is no problem with a plastic substrate, which is sensitive to heat.

[77] FIG. 10 is a view illustrating a process of crystallizing an amorphous silicon layer according to still another exemplary embodiment of the present invention.

[78] FIG. 10 shows a structure having a plasma generator 650 instead of the lamp of FIG.

8. The plasma generator 650 is used to irradiate plasma to a prepared thin film to provide energy, thereby crystallizing an amorphous silicon layer. An inert gas, preferably argon, is filled between copper and tungsten, and then high DC voltage is applied thereto, plasma is generated due to gas breakdown. The generated plasma is exhausted through a hole under the generator by high expansive force. Here, heat generated from copper is cooled down by cooling water. By this method, the plasma may be processed at low temperature, so that a plastic substrate cannot be deformed. Meanwhile, to attenuate obstacles to moving plasma to a silicon thin film, the process may be performed in vacuum equipment having a vacuum level of 10 Torr or less.

[79] However, to crystallize a large-scaled silicon thin film, a plasma generator has to be very large. For this reason, a method of applying plasma to a mask disposed over a silicon thin film using the limited-sized plasma generator may be used. A principle of generating plasma is the same as described above, and the entire silicon thin film has to be scanned while plasma is generated. The plasma is provided only to a hole in the mask, so that only a desired part of the silicon thin film may be crystallized.

[80] Meanwhile, various methods for stimulating the crystallization may be applied to the present embodiment. For example, the crystallization may be performed by applying an electric field or a magnetic field, or heating a substrate to a predetermined temperature. In this case, the method of applying a magnetic field may uniformly crystallize the entire substrate since the uniform magnetic field can be applied due to the nature of the magnetic field, and thus the crystallization may be more effectively performed by applying the magnetic field before or after the crystallization method as described above, or by a different method together with the application of the magnetic field.

[81] FIG. 11 illustrates another sample of a crystallization mask according to an exemplary embodiment of the present invention. The crystallization mask includes a main body 710, an opening 730, and an alignment key 720. The alignment key 720 is formed in a transparent region, and the main body 710 may be formed in a non- transmissive region. Light, heat, gas and plasma may pass through the opening 730 using the mask for crystallization.

[82] Method of manufacturing thin film transistor having upper gate structure)

[83] FIGS. 12 to 15 are cross-sectional views illustrating a process of manufacturing a thin film transistor using a crystallization method according to an exemplary embodiment of the present invention.

[84] Referring to FIG. 12, a substrate 800 is prepared, and a buffer layer 810 and an amorphous silicon layer 820 are formed thereon. A type of the substrate 800 is not limited, for example, which may be a glass substrate, a plastic substrate or a flexible substrate. In addition, the buffer layer 810 serves to prevent crystallized silicon from being contaminated by impurities contained in the substrate 800 when the amorphous silicon layer 820 is deposited and crystallized into a polycrystalline silicon layer in a subsequent process. Accordingly, the buffer layer 810 can be omitted in some cases.

[85] The buffer layer 810 may be an insulating layer, which may be formed of any insulating material known in the art, for example, silicon oxide or silicon nitride using plasma enhanced chemical vapor deposition (PECVD). The buffer layer 810 may be formed to a thickness of 1000 to IOOOOA and preferably 2000 to 5000A.

[86] Thereafter, the amorphous silicon layer 820 is formed on the buffer layer. That is, the amorphous silicon layer 820 may be formed on the buffer layer 810 by depositing monosilane (SiH ), as a source gas, diluted with argon (Ar) gas using PECVD. The amorphous silicon layer 820 may be formed to a thickness of 300 to 2000A and preferably approximately 500A. [87] Then, a structure for crystallization including a support 840 and projections 850 having flat bottom surfaces is aligned to the substrate 800. [88] Referring to FIG. 13, heat is applied to the aligned projections 850 to crystallize regions of the amorphous silicon layer 820 which correspond to the projections 850.

While FIG. 13 simply illustrates the crystallization of the amorphous silicon layer by heating the projections, it can be clearly understood that the amorphous silicon layer may be partially crystallized by any method described above. [89] FIG. 14 is a plan view illustrating crystallization after the process of FIG. 13 is completed. A heated portion corresponds to a channel of the thin film transistor. As described above, only the channels can be crystallized without deformation of the substrate by such local heating. [90] A process of manufacturing a thin film transistor will now be described. A channel

40 of the polysilicon layer is formed by a selective patterning technique. A gate insulating layer 50 having a predetermined thickness is formed. For example, the gate insulating layer is generally formed to a thickness of 500 to 2000A.

[91] A gate electrode 70 is formed on the gate insulating layer 50. Then, predetermined regions of the active layer are doped with n+ type and p+ type ions using the gate electrode 70 as a mask to form a source and a drain, respectively. The gate electrode

70 may be formed to a thickness of 1500 to 4000A and preferably approximately 3000A. [92] Thereafter, an interlayer insulating layer 60 is formed on the gate electrode 70 and patterned, thereby forming a contact, and a metal layer 80 is deposited and patterned to connect the source and drain of the active layer to data lines through the contact. The interlayer insulating layer 60 may be formed to a thickness of 2000 to 8000A.

[93] However, it may be certain that an n- or p-type polysilicon thin film transistor may be formed by the above-described process, and a known lightly-doped drain (LDD) structure may be applied to this embodiment. The LDD structure is completed by lightly doping using the gate electrode 70 as a doping mask, by forming a spacer or photoresist, which can serve as a doping mask at one or both sides of the gate electrode 70 using a spacer process, and then by highly doping the spacer and photoresist as masks to form a source or drain electrode.

[94] fVlethod of manufacturing thin film transistor having lower gate structure)

[95] FIGS. 16 to 19 are cross-sectional views illustrating a process of manufacturing a thin film transistor using a crystallization method according to another exemplary embodiment of the present invention.

[96] Referring to FIG. 16, an electrode layer is formed on a substrate 920, and etched to form a gate electrode 910.

[97] Further, a gate insulating layer 922, an amorphous silicon layer 924 and an n+ doped amorphous silicon layer 926 are sequentially formed over the gate electrode 910 by a known method such as PECVD. Then, a structure for crystallization including a support 940 and projections 950 having flat bottom surfaces is aligned over the substrate 920. Here, the structure for crystallization may be aligned using a pattern having the gate electrode 910.

[98] While the FIG. 17 shows that the gate insulating layer 922, the amorphous silicon layer 924 and the n+ doped amorphous silicon layer 926 are sequentially formed over the gate electrode 910 and then crystallized, in seme cases, the gate insulating layer 922 and the amorphous silicon layer 924 may be sequentially deposited and then crystallized. Here, the n+ doped amorphous silicon layer 926 may be deposited over the crystallized silicon layer.

[99] Thereafter, referring to FIG. 19, a conductive layer is formed to form a source and a drain connected to an active layer on the above structure, and then patterned, thereby forming source and drain electrodes 930. An interlayer insulating layer is formed on the electrodes.

[100] The invention have been shown and described with reference to certain exemplary embodiments thereof, the invention will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

[1] A structure for crystallization, comprising: a board-shaped support disposed at a lower part thereof; and a plurality of projections having flat bottom surfaces, which project from the support and are spaced a predetermined distance apart from each other, wherein the flat bottom surfaces are set to a temperature higher than the support when the flat bottom surfaces are heated to a temperature by approaching an object.

[2] A structure for crystallization, comprising: a board-shaped support disposed at a lower part thereof; and interconnections formed in a matrix having a first resistance and disposed on the board-shaped support, and a plurality of resistors selectively inserted into the interconnections to disconnect the interconnections, having flat bottom surfaces, and having a second resistance to be spaced a predetermined distance apart from each other, wherein the resistors generates heat as a voltage is applied to the interconnections, the generated heat is intensively applied to portions of an object at a predetermined interval, and the second resistance is higher than the first resistance.

[3] The structure according to claim 1 or 2, further comprising: a blocking part for preventing transmission of temperature to the other regions except the flat bottom surfaces.

[4] The structure according to claim 2, wherein the blocking part is supported by the support spaced apart a certain distance therefrom to reduce thermal transmission.

[5] The structure according to claim 1 or 2, wherein the flat bottom surface is

2 formed to have an area of 10 to 500/M .

[6] The structure according to claim 1 or 2, wherein the projection has a temperature of 200 to 1500⁰C.

[7] The structure according to claim 1 or 2, wherein an area ratio of the flat bottom surfaces to the other regions except the flat bottom surfaces is 0.2 to 10%.

[8] The structure according to claim 1 or 2, wherein the support has a transparent region, on which an alignment key is formed.

[9] The structure according to claim 1, wherein the projection is capable of moving up and down on the basis of the support.

[10] The structure according to claim 1, wherein the projection is formed of a material having a higher resistance than the support.

[11] A method of crystallizing an amorphous silicon layer, comprising the steps of: preparing a substrate on which an amorphous silicon layer is deposited; positioning a structure for crystallization to be in contact with or disposing the structure in a predetermined distance apart from a top surface of the amorphous silicon layer; and heating a plurality of regions having a predetermined area in the amorphous silicon layer at a higher temperature than other regions around the plurality of regions in the amorphous silicon layer by the structure to crystallize the predetermined regions of the amorphous silicon layer by changing a characteristic of the predetermined regions of the amorphous silicon layer.

[12] The method according to claim 11, wherein the step of heating the plurality of regions in the amorphous silicon layer at a higher temperature than other regions around the plurality of regions in the amorphous silicon layer comprises performing using the structure for crystallization including a board-shaped support disposed at a lower part thereof, and a plurality of projections having flat bottom surfaces, which project from the support and are spaced a predetermined distance apart from each other, wherein the flat bottom surfaces are set to a temperature higher than the support.

[13] The method according to claim 11, wherein the step of heating the plurality of regions in the amorphous silicon layer at a higher temperature than other regions around the plurality of regions in the amorphous silicon layer comprises performing using a board-shaped support disposed at a lower part thereof; and interconnections formed in a matrix having a first resistance and disposed on the board-shaped support, and a plurality of resistors selectively inserted into the interconnections to disconnect the interconnections, having flat bottom surfaces, and having a second resistance to be spaced a predetermined distance apart from each other, wherein the resistors generates heat as a voltage is applied to the interconnections, and the generated heat is intensively applied to portions of an object at a predetermined interval.

[14] The method according to claim 11, wherein the step of heating the plurality of regions in the amorphous silicon layer at a higher temperature than other regions around the plurality of regions in the amorphous silicon layer comprises: preparing a mask exposing the plurality of regions on the amorphous silicon layer; and applying heat, light, gas or plasma to the exposed regions.

[15] The method according to claim 11, wherein the flat bottom surface is formed to have an area of 10 to 500/M .

[16] The method according to claim 11, wherein the temperature of the projection is

200 to 1500⁰C.

[17] The method according to claim 11, wherein an area percentage of the flat bottom surfaces to the other regions except the flat bottom surfaces is 0.2 to 10%.

[18] The method according to claim 11, further comprising the step of: after the step of preparing the substrate on which the amorphous silicon layer is deposited, aligning the structure for crystallization to the amorphous silicon layer.

[19] The method according to claim 11, wherein the step of positioning a structure for crystallization to be in contact with or disposing the structure in a predetermined distance apart from a top surface of the amorphous silicon layer is performed by moving the structure up and down over the amorphous silicon layer several times.

[20] The method according to claim 11, further comprising the step of: forming a buffer layer on or under the amorphous silicon layer.

[21] The method according to claim 11, further comprising the step of: in the step of crystallizing the amorphous silicon layer, applying an electric or magnetic field to facilitate crystallization.

[22] A method of forming a semiconductor active layer, comprising the steps of: forming a first semiconductor layer on a substrate; positioning a structure for crystallization to be in contact with or disposing the structure in a predetermined distance apart from a top surface of the first semiconductor layer; heating a plurality of selected regions having a predetermined area, in which active regions are formed in at least one portion of the first semiconductor layer, at a higher temperature than other regions around the selected regions by the structure to change a characteristic of the selected regions; and patterning at least one portion of the selected regions to form an active layer.

[23] The method according to claim 22, wherein the step of heating the plurality of regions in the first semiconductor layer at a higher temperature than other regions around the plurality of regions in the first semiconductor layer comprises: preparing a mask exposing the plurality of regions in the first semiconductor layer; and applying heat, light, gas or plasma to the exposed regions. [24] The method according to claim 22, wherein the step of heating the plurality of regions in the first semiconductor layer at a higher temperature than other regions around the plurality of regions in the first semiconductor layer comprises: performing using the structure for crystallization including a board-shaped support disposed at a lower part thereof, and a plurality of projections having flat bottom surfaces, which project from the support and are spaced a predetermined distance apart from each other, setting the flat bottom surfaces to have a temperature higher than the support. [25] A method of manufacturing a thin film transistor, comprising the steps of: forming a semiconductor active layer according to any one of claims 22 to 25; forming a gate insulating layer over the active layer; and forming a gate electrode, and source and drain electrodes over the gate insulating layer, the source and drain electrodes being connected to the active layer. [26] A method of manufacturing a thin film transistor, comprising the steps of: forming a gate electrode and a gate insulating layer on a substrate; forming a semiconductor active layer according to any one of claims 22 to 25; forming a gate insulating layer over the active layer; and forming a gate electrode, and source and drain electrodes over the gate insulating layer, the source and drain electrodes being connected to the active layer.