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WO2008016951A3 - Procédé et appareil pour bus hiérarchique de polarisation de ligne de bits pour matrice mémoire à blocs sélectionnables - Google Patents

Procédé et appareil pour bus hiérarchique de polarisation de ligne de bits pour matrice mémoire à blocs sélectionnables Download PDF

Info

Publication number
WO2008016951A3
WO2008016951A3 PCT/US2007/074904 US2007074904W WO2008016951A3 WO 2008016951 A3 WO2008016951 A3 WO 2008016951A3 US 2007074904 W US2007074904 W US 2007074904W WO 2008016951 A3 WO2008016951 A3 WO 2008016951A3
Authority
WO
WIPO (PCT)
Prior art keywords
array blocks
bit line
memory array
memory
line bias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/074904
Other languages
English (en)
Other versions
WO2008016951A2 (fr
Inventor
Roy E Scheuerlein
Luca G Fasoli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk 3D LLC
Original Assignee
SanDisk 3D LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/461,376 external-priority patent/US7596050B2/en
Priority claimed from US11/461,362 external-priority patent/US7633828B2/en
Application filed by SanDisk 3D LLC filed Critical SanDisk 3D LLC
Publication of WO2008016951A2 publication Critical patent/WO2008016951A2/fr
Publication of WO2008016951A3 publication Critical patent/WO2008016951A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne des circuits et des procédés qui permettent de décoder des matrices mémoire de cellules de mémoire à éléments passifs programmables et, dans certains modes de réalisation, des matrices mémoire de cellules de mémoire à éléments passifs réinscriptibles, qui sont particulièrement utiles pour des matrices mémoire tridimensionnelles extrêmement denses possédant plus d'un plan mémoire. L'invention concerne en outre des circuits et des procédés qui permettent de sélectionner un ou plusieurs blocs d'une matrice mémoire, de sélectionner une ou plusieurs lignes de mots et lignes de bits dans les blocs de matrice sélectionnés, de transporter des informations de données à destination et en provenance des cellules mémoire sélectionnées dans les blocs de matrice sélectionnés, et de transporter des conditions de polarisation non sélectionnées vers des blocs de matrice non sélectionnés.
PCT/US2007/074904 2006-07-31 2007-07-31 Procédé et appareil pour bus hiérarchique de polarisation de ligne de bits pour matrice mémoire à blocs sélectionnables Ceased WO2008016951A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/461,376 US7596050B2 (en) 2006-07-31 2006-07-31 Method for using a hierarchical bit line bias bus for block selectable memory array
US11/461,376 2006-07-31
US11/461,362 US7633828B2 (en) 2006-07-31 2006-07-31 Hierarchical bit line bias bus for block selectable memory array
US11/461,362 2006-07-31

Publications (2)

Publication Number Publication Date
WO2008016951A2 WO2008016951A2 (fr) 2008-02-07
WO2008016951A3 true WO2008016951A3 (fr) 2008-05-15

Family

ID=38997824

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/074904 Ceased WO2008016951A2 (fr) 2006-07-31 2007-07-31 Procédé et appareil pour bus hiérarchique de polarisation de ligne de bits pour matrice mémoire à blocs sélectionnables

Country Status (2)

Country Link
TW (1) TWI345787B (fr)
WO (1) WO2008016951A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119109723B (zh) * 2023-06-07 2025-08-29 湖南芯力特电子科技有限公司 Can总线驱动电路、can收发器及can总线结构

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245570A (en) * 1990-12-21 1993-09-14 Intel Corporation Floating gate non-volatile memory blocks and select transistors

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245570A (en) * 1990-12-21 1993-09-14 Intel Corporation Floating gate non-volatile memory blocks and select transistors

Also Published As

Publication number Publication date
TWI345787B (en) 2011-07-21
WO2008016951A2 (fr) 2008-02-07
TW200826114A (en) 2008-06-16

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