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WO2008008661A3 - Interleaved hardware multithreading processor architecture and dynamic instruction and data updating architecture - Google Patents

Interleaved hardware multithreading processor architecture and dynamic instruction and data updating architecture Download PDF

Info

Publication number
WO2008008661A3
WO2008008661A3 PCT/US2007/072668 US2007072668W WO2008008661A3 WO 2008008661 A3 WO2008008661 A3 WO 2008008661A3 US 2007072668 W US2007072668 W US 2007072668W WO 2008008661 A3 WO2008008661 A3 WO 2008008661A3
Authority
WO
WIPO (PCT)
Prior art keywords
architecture
processor
data
instruction
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/072668
Other languages
French (fr)
Other versions
WO2008008661A2 (en
Inventor
James D Pennock
Ronald Baker
Brian R Parker
Christopher Belcher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harman International Industries Inc
Original Assignee
Harman International Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/599,967 external-priority patent/US8074053B2/en
Priority claimed from US11/599,732 external-priority patent/US8429384B2/en
Application filed by Harman International Industries Inc filed Critical Harman International Industries Inc
Publication of WO2008008661A2 publication Critical patent/WO2008008661A2/en
Publication of WO2008008661A3 publication Critical patent/WO2008008661A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)

Abstract

An architecture for a digital signal processor alleviates the difficulties and complexities normally associated with writing and optimizing programs to avoid stalls during which one instruction awaits the result of a prior instruction. The architecture coordinates the processing of data for multiple instructions through a multiple stage data pipeline. As a result, the architecture not only supports simultaneous execution of multiple programs, but also permits each program to execute without delays caused by inter-relationships between instructions within the program. A memory update engine provides flexible modification of data in memory. A processor may employ the update engine to update filter coefficients, special effects parameters, signal sample processing instructions, or any other instruction or data during processing. The update engine supports dynamic updating without requiring processor shutdown, thereby allowing the processor to seamlessly continue operation during a live performance.
PCT/US2007/072668 2006-07-11 2007-07-02 Interleaved hardware multithreading processor architecture and dynamic instruction and data updating architecture Ceased WO2008008661A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US83016606P 2006-07-11 2006-07-11
US60/830,166 2006-07-11
US11/599,732 2006-11-15
US11/599,967 US8074053B2 (en) 2006-07-11 2006-11-15 Dynamic instruction and data updating architecture
US11/599,732 US8429384B2 (en) 2006-07-11 2006-11-15 Interleaved hardware multithreading processor architecture
US11/599,967 2006-11-15

Publications (2)

Publication Number Publication Date
WO2008008661A2 WO2008008661A2 (en) 2008-01-17
WO2008008661A3 true WO2008008661A3 (en) 2008-07-31

Family

ID=38819707

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/072668 Ceased WO2008008661A2 (en) 2006-07-11 2007-07-02 Interleaved hardware multithreading processor architecture and dynamic instruction and data updating architecture

Country Status (1)

Country Link
WO (1) WO2008008661A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020056034A1 (en) * 1999-10-01 2002-05-09 Margaret Gearty Mechanism and method for pipeline control in a processor
US6462743B1 (en) * 1999-12-21 2002-10-08 Ati International Srl Pipeline processing system and method
WO2003003237A2 (en) * 2001-06-29 2003-01-09 Eleven Engineering Incorporated System on chip architecture
WO2005069121A1 (en) * 2004-01-13 2005-07-28 Koninklijke Philips Electronics N.V. Electronic circuit with a fifo pipeline

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020056034A1 (en) * 1999-10-01 2002-05-09 Margaret Gearty Mechanism and method for pipeline control in a processor
US6462743B1 (en) * 1999-12-21 2002-10-08 Ati International Srl Pipeline processing system and method
WO2003003237A2 (en) * 2001-06-29 2003-01-09 Eleven Engineering Incorporated System on chip architecture
WO2005069121A1 (en) * 2004-01-13 2005-07-28 Koninklijke Philips Electronics N.V. Electronic circuit with a fifo pipeline

Also Published As

Publication number Publication date
WO2008008661A2 (en) 2008-01-17

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