WO2008001363A3 - Monolithic flash memory having integrated code and data memory portions - Google Patents
Monolithic flash memory having integrated code and data memory portions Download PDFInfo
- Publication number
- WO2008001363A3 WO2008001363A3 PCT/IL2007/000778 IL2007000778W WO2008001363A3 WO 2008001363 A3 WO2008001363 A3 WO 2008001363A3 IL 2007000778 W IL2007000778 W IL 2007000778W WO 2008001363 A3 WO2008001363 A3 WO 2008001363A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory portion
- memory
- data
- fabricated
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
Abstract
A memory chip (10) includes a first memory portion (11) fabricated using charge trapping technology and configured using NAND memory cell array architecture and a second memory portion (12) fabricated using charge trapping technology and having mutually distinct first and second sets of addresses, respectively. A buffer memory portion (14) is coupled to the first memory portion for temporary storage of blocks of data that are written to or read from the first memory portion. Registers (18) store an instruction for controlling the first memory portion. A first interface (19) has a address bus for receiving an address within the first or second set of addresses and has a data bus for conveying data to and from the first memory portion or the second memory portion according to the address. All components are fabricated on a single die.
Applications Claiming Priority (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US81659606P | 2006-06-27 | 2006-06-27 | |
| US60/816,596 | 2006-06-27 | ||
| US84340606P | 2006-09-11 | 2006-09-11 | |
| US60/843,406 | 2006-09-11 | ||
| US86205406P | 2006-10-19 | 2006-10-19 | |
| US60/862,054 | 2006-10-19 | ||
| US88716207P | 2007-01-30 | 2007-01-30 | |
| US60/887,162 | 2007-01-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2008001363A2 WO2008001363A2 (en) | 2008-01-03 |
| WO2008001363A3 true WO2008001363A3 (en) | 2008-04-24 |
Family
ID=38561212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IL2007/000778 Ceased WO2008001363A2 (en) | 2006-06-27 | 2007-06-26 | Monolithic flash memory having integrated code and data memory portions |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO2008001363A2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9690650B2 (en) * | 2013-03-11 | 2017-06-27 | Macronix International Co., Ltd. | Storage scheme for built-in ECC operations |
| US11640308B2 (en) * | 2021-02-19 | 2023-05-02 | Macronix International Co., Ltd. | Serial NAND flash with XiP capability |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001084556A1 (en) * | 2000-05-03 | 2001-11-08 | Advanced Technology Materials, Inc. | Electrically-eraseable programmable read-only memory having reduced-page-size program and erase |
| US20040027856A1 (en) * | 2002-07-05 | 2004-02-12 | Aplus Flash Technology, Inc. | Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations |
| US20040071030A1 (en) * | 2002-07-03 | 2004-04-15 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuits, fabrication method for the same and semiconductor integrated circuit systems |
-
2007
- 2007-06-26 WO PCT/IL2007/000778 patent/WO2008001363A2/en not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001084556A1 (en) * | 2000-05-03 | 2001-11-08 | Advanced Technology Materials, Inc. | Electrically-eraseable programmable read-only memory having reduced-page-size program and erase |
| US20040071030A1 (en) * | 2002-07-03 | 2004-04-15 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuits, fabrication method for the same and semiconductor integrated circuit systems |
| US20040027856A1 (en) * | 2002-07-05 | 2004-02-12 | Aplus Flash Technology, Inc. | Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2008001363A2 (en) | 2008-01-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7791952B2 (en) | Memory device architectures and operation | |
| US8320200B2 (en) | Semiconductor storage device and method of reading data therefrom | |
| US6751129B1 (en) | Efficient read, write methods for multi-state memory | |
| US20080195800A1 (en) | Flash Memory Device and Flash Memory System Including a Buffer Memory | |
| US20060294295A1 (en) | DRAM chip device well-communicated with flash memory chip and multi-chip package comprising such a device | |
| EP2306460A2 (en) | Concurrent flash memory access | |
| US20130286737A1 (en) | Nand flash memory having c/a pin and flash memory system including the same | |
| US20030210569A1 (en) | Semiconductor memory device and memory system | |
| US8359423B2 (en) | Using LPDDR1 bus as transport layer to communicate to flash | |
| WO2002017330A3 (en) | Novel method and structure for reliable data copy operation for non-volatile memories | |
| CN1322441C (en) | Multi-chip package type memory system | |
| GB2401460A (en) | Partial page programming of multi level flash semiconductor memory | |
| CN102096647A (en) | Multi-chip memory system and related data transfer method | |
| JP2008527586A (en) | Group and align on-chip data | |
| EP1932158A1 (en) | Memory with output control | |
| US20070088867A1 (en) | Memory controller and data processing system with the same | |
| US20100077130A1 (en) | Multiprocessor system with booting function using memory link architecture | |
| US8886915B2 (en) | Multiprocessor system having direct transfer function for program status information in multilink architecture | |
| US20070033336A1 (en) | Shared interface semiconductor memories | |
| US20160093379A1 (en) | Nand memory addressing | |
| KR100758301B1 (en) | Memory card and its data storage method | |
| WO2006081057A3 (en) | Simultaneous pipelined read with dual level cache for improved system performance using flash technology | |
| WO2008001363A3 (en) | Monolithic flash memory having integrated code and data memory portions | |
| US20110122713A1 (en) | Read strobe feedback in a memory system | |
| US7490193B2 (en) | Flash memory devices with MMC interfaces and methods of operating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 07766809 Country of ref document: EP Kind code of ref document: A2 |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| NENP | Non-entry into the national phase |
Ref country code: RU |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 07766809 Country of ref document: EP Kind code of ref document: A2 |