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WO2008000667A1 - ProcÉdÉ pour l'adressage de membres d'un agencement de circuits mis en cascade de par le matériel - Google Patents

ProcÉdÉ pour l'adressage de membres d'un agencement de circuits mis en cascade de par le matériel Download PDF

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Publication number
WO2008000667A1
WO2008000667A1 PCT/EP2007/056118 EP2007056118W WO2008000667A1 WO 2008000667 A1 WO2008000667 A1 WO 2008000667A1 EP 2007056118 W EP2007056118 W EP 2007056118W WO 2008000667 A1 WO2008000667 A1 WO 2008000667A1
Authority
WO
WIPO (PCT)
Prior art keywords
subscriber
circuit arrangement
addressing
addressed
enable signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2007/056118
Other languages
German (de)
English (en)
Inventor
Jan Kaluza
Dieter Sonnleitner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of WO2008000667A1 publication Critical patent/WO2008000667A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/50—Address allocation
    • H04L61/5038—Address allocation for local use, e.g. in LAN or USB networks, or in a controller area network [CAN]

Definitions

  • the invention relates to a method for addressing hardware-dependent cascaded subscribers of a circuit arrangement, a circuit arrangement, a computer program and a computer program product
  • Integrated electronic circuits (ICs) in circuitry typically used in control devices have at least one serial peripheral interface (SPI) as connections to at least one other module.
  • SPI serial peripheral interface
  • this address space splitting is already established during a manufacturing process of the circuits.
  • the number of chip or slave select signals provided by integrated circuits e.g. B. are designed as microcontroller, often not sufficient.
  • the document DE 100 36 367 A1 describes a method for controlling peripheral elements.
  • a processor module has a predetermined number of selection interfaces. It is envisaged that a coprocessor with input interfaces and output interfaces will depend on the peripheral elements an assignment of signals at its input interfaces to signals at its output interfaces controls.
  • peripheral elements are selected by a processor module having a predetermined number of selection interfaces by selection signals which are output via these selection interfaces.
  • instructions are transmitted via at least one information interface of the processor module. These instructions are assigned selection identifiers. The instructions are transmitted with the associated selection identifiers, wherein the selection of a peripheral element is performed by a selection signal and a selection identifier.
  • the invention relates to a method for addressing hardware-dependent cascaded participants of a circuit arrangement. It is envisaged that in the circuit arrangement each subscriber is connected to two sections of an additional line and two adjacent stations are connected to each other via a respective section of the supplementary line. During addressing, all subscribers are addressed one after the other by means of a cascadable enable signal, which is transmitted via the additional line.
  • the cascadable enable signal is transmitted along the additional line after the addressing of the preceding subscriber and before the addressing of the subsequent subscriber between a respective section of the additional line connecting the preceding subscriber and the subsequent subscriber.
  • a state of the preceding subscriber is influenced by the cascadable enable signal when the enable signal enters the subsequent subscriber as an input signal. This can mean that the preceding subscriber is enabled or activated or reset or deactivated by the input signal.
  • a state of the subsequent participant is likewise determined by the cascadable release. Besignal influenced when the enable signal leaves the previous participant as an output signal or exits from this. As a result, the following subscriber is enabled or activated or disabled or deactivated.
  • a subscriber currently to be addressed in each case is released before being addressed by the cascadable enable signal. After addressing this participant must be locked. Such a locking of the currently addressed subscriber makes it possible to effect a release of a subsequent subscriber.
  • the one cascadable enable signal it must be ensured that only one subscriber is activated along the cascade and thus released for addressing, all other subscribers are then respectively deactivated and thus not addressable.
  • a first interface can be designed as an input interface for an incoming section of the additional line and a second interface as an output interface for an outgoing section of the additional line.
  • the input interface is activated and the output interface is deactivated in each case before addressing one subscriber. After addressing, the output interface is activated. In this case, by activating the output interface of the currently addressed subscriber, a subscriber subsequently to be addressed to this subscriber can be released for addressing.
  • the method can be carried out, for example, after a reset or restart of the circuit arrangement.
  • each subscriber is first assigned the same initialization address, which, for example, has the value zero.
  • the circuit arrangement according to the invention has a plurality of hardware-dependent cascaded subscribers, each subscriber being connected to two sections of an additional line. Two adjacent participants are connected to each other via a section of the additional line.
  • the subscribers of the circuit arrangement are to be addressed in that they are to be addressed by means of a cascadable enable signal, which is to be transmitted via the additional line, successively via a serial interface (eg SPI bus).
  • a serial interface eg SPI bus
  • each subscriber has a serial peripheral input interface for an incoming portion of the additional line and a serial peripheral output interface for an outgoing portion of the additional line.
  • the computer program with program code means according to the invention is intended to carry out all the steps of a method according to the invention when the computer program is executed on a computer or a corresponding computing unit, in particular in a circuit arrangement according to the invention.
  • the invention also relates to a computer program product with program code means which are stored on a computer-readable data carrier in order to carry out all the steps of a method according to the invention when the computer program is executed on a computer or a corresponding arithmetic unit, in particular in a circuit arrangement according to the invention.
  • the invention allows a flexible design of circuitry with respect to a number of subscribers and a number of functions that can be performed by the subscribers.
  • This circuit arrangement can be designed as an SPI bus and thus as a data connection with serial peripheral interfaces for the subscribers.
  • serial peripheral interfaces for the subscribers.
  • the enable signal can be defined as an input signal ("chain-in signal") when it enters one of the subscribers (input).
  • the enable signal causes a switch, in particular either a release or a reset, of the previous participant within the cascade.
  • the enable signal can also be defined as an output signal ("chain-out signal”) when it exits a subscriber (output). This output signal causes a switching of the subsequent subscriber in the cascade, for example, either its release or blocking.
  • a "POWER ON RESET" and thus a reset are carried out, wherein all SPI bus users have the address 0000b.
  • a new address is assigned for the first participant. The prerequisite for this is that its input interface or a CHIN input is permanently activated and thus set to high and the output interface or a CHOUT output is deactivated and thus set to low.
  • the new address must be different from 0000b, which can be realized when the addressing is carried out.
  • the acceptance of the address is confirmed in a data field of the respective participant. After accepting the new address, the participant or a corresponding block is locked and the CHOUT output is activated and thus set to high.
  • the addressing of the subsequent subscriber ie a successor of the subscriber just addressed, is released.
  • the addressing of this successor is identical.
  • the subscribers can be assigned different addresses or address data in a range from 0001b to 1110b.
  • the address 1111b may be used as needed for special purposes such as an emergency shutdown, reinitialization, etc. According to this principle, up to 14 subscribers can be addressed in the distribution of addresses. After addressing the Subscribers are usually added to the normal operation of the circuit arrangement.
  • an address present at the currently addressed subscriber is checked with its own address, thus multiple addressing during address assignment is to be avoided. If the same address data occur at least twice, the cascade of the already addressed subscriber by removing the CHOUT signal, d. H. by switching from high to low, interrupted and thus prevents multiple addressing. The following subscribers are reset and must be addressed or initialized again. A respective data field is notified of such a collision by the bit sequence 11110000.
  • the topology for subscribers of an SPI bus described for the present circuit arrangement can be used, for example, in the development of new integrated circuits, which results in new possibilities for the design of control units. By cascading it is possible to flexibly offer different specific hardware variants.
  • Table 1 below shows an example of an Integrated Circuit (IC) protocol where MOSI is an abbreviation for “Master-Out-Slave-In” and MISO is an abbreviation for "Master-In-Slave-Out”.
  • IC Integrated Circuit
  • Figure 1 shows a schematic representation of an embodiment of the circuit arrangement according to the invention.
  • FIG. 2 shows a schematic representation of a diagram for an example of an addressing protocol.
  • the embodiment of a circuit formed as an SPI bus schematically illustrated in Figure 1 has a first participant 104, a second participant 106 and an n-th participant 108, which are formed here as integrated circuits (ICs).
  • Each subscriber 104, 106, 108 has an input interface 110 (CHIN) and an output interface 112 (CHOUT), via which the subscribers 104, 106, 108 are each connected to a section of an additional line 114, so that each subscriber 104, 106, 108 with two sections, namely an incoming and an outgoing section, the additional line 114 is connected.
  • two adjacent subscribers 104, 106, 108 each have a section of the supplementary line. tion 114 interconnected.
  • the additional line 114 is applied to a voltage source 116 (Vcc) and has an electrical resistance 118.
  • Vcc voltage source
  • the resistor 118 can also be applied directly an enable signal, which is output directly from a microcontroller.
  • each subscriber 104, 106, 108 is connected to lines 120, 122, 124, 126 of an SPI bus connection 120 and thus connected to a master 130 of the circuit arrangement 102. Accordingly, the subscribers 104, 106, 108 are to be classified as SIaves of the circuit arrangement 102.
  • An addressing of the subscribers 104, 106, 108 takes place with an address allocation command on the SPI bus under the condition that a cascadable enable signal, which is transmitted between the subscribers 104, 106, 108 via the sections of the additional line 114, is active. Thus, all users 104, 106, 108 are addressed one after the other.
  • the cascadable enable signal connects the input interfaces 110 and the output interfaces 112 of the subscribers 104, 106, 108 during a transfer via the sections of the additional line 114 between adjacent subscribers 104, 106, 108 along the cascade, and activates or deactivates these subscribers 104, 106, 108 here. It is also provided that the subscribers 104, 106, 108 are each addressed via an address-specific transmission protocol. During the addressing of a respective subscriber 104, 106, 108, the master 130 sends a "chip-select" signal (/ CS) via a first line 122, and a "master-out-slave-in" via a second line 124.
  • a "chip-select" signal (/ CS)
  • Such functional interfaces 136 which are shown as arrows which point into the subscribers 104, 106, 108, are designed as input function interfaces 136, which are shown as arrows pointing out of the participants 104, 106, 108, are formed as output function interfaces.
  • the subscribers 104, 106, 108 are respectively successively enabled or reset along the additional line by the cascadable enable signal, so that in each case only one subscriber 104, 106, 108 is activated and thus ready for addressing.
  • the first user 104 is assigned a first address
  • the second user 106 is assigned a second address
  • the nth user 108 is assigned an nth address.
  • FIG. 2 shows in an addressing protocol along a time axis 202 from top to bottom in each case a course of a "chip select" signal 204 (/ CS), a synchronization signal 206 (SCLK), a "master-out-slave-in” Signal 208 (MOSI) and a "Master-In-Slave-Out” signal 210 (MISO).
  • CS chip select
  • SCLK synchronization signal
  • MOSI master-out-slave-in
  • MISO Master-In-Slave-Out
  • the selectable "chip select" signal 204 is set to high 212 or high before and after completion of the data transfer, while it is set to low 214 or low during addressing.
  • the synchronization signal 206 With the synchronization signal 206, a signal of one clock of the SPI bus 120 is transmitted, it is alternately switched between high 212 and low 214, thereby successively counting from 7 to 0.
  • the "master-out-slave-in” signal 208 is subdivided into three temporally successive sections 216, 218, 220.
  • a first section 216 the individual subscribers 104, 106, 108 of the SPI bus are addressed via bits A3, A2, A1, A0.
  • functions of the subscribers 104, 106, 108 in this case so-called block functions, are coded via bits F3, F2, F1, FO.
  • F3, F2, F1, FO For example, "READ_DIAGNOSE”, "WRITE_OUTPUTS”, and so on.
  • data of "WRITE" functions are transmitted via bits D7, D6, D5, D4, D3, D2, D1, DO whose digits are synchronized with those of the synchronization signal 206.
  • the "master-in-slave-out” signal 210 is also divided into three sections 222, 224, 226.
  • the first four bits during the first section 222 of the "master-in-slave-out” signal 210 remain unused, since an address of at least one subscriber 104, 106, 108 is not yet completely known.
  • the output of each slave for the master-in-slave-out signal 210 is disabled (high impedance) during this first section 222, and the master-in-slave-out signal 210 is thus inactive.
  • An address confirmation of the subscribers 104, 106, 108 regarded here as slaves takes place during the second section 224, in which case the respectively addressed subscribers 104, 106, 108 report on bits A3, A2, A1, A0, each with its own address.
  • a return of the data takes place in the third section 226, whereby data requested via the bits D7, D6, D5, D4, D3, D2, D1, DO are transmitted functionally dependent.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)

Abstract

L'invention concerne un procédé pour l'adressage de membres (104, 106, 108) d'un agencement de circuits (102) mis en cascade de par le matériel. Il est prévu que, dans l'agencement de circuits (102), chaque membre (104, 106, 108) soit branché sur deux tronçons d'une ligne supplémentaire (114) et que deux membres (104, 106, 108) voisins soient reliés ensemble respectivement par un tronçon de la ligne supplémentaire (104, 106, 108). Lors de l'adressage, tous les membres (104, 106, 108) sont adressés les uns après les autres au moyen d'un signal de validation pouvant être émis en cascade, qui est transmis par la ligne supplémentaire (114).
PCT/EP2007/056118 2006-06-29 2007-06-20 ProcÉdÉ pour l'adressage de membres d'un agencement de circuits mis en cascade de par le matériel Ceased WO2008000667A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102006029997.3 2006-06-29
DE102006029997A DE102006029997A1 (de) 2006-06-29 2006-06-29 Verfahren zur Adressierung von hardwareabhängig kaskadierten Teilnehmern einer Schaltungsanordnung

Publications (1)

Publication Number Publication Date
WO2008000667A1 true WO2008000667A1 (fr) 2008-01-03

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PCT/EP2007/056118 Ceased WO2008000667A1 (fr) 2006-06-29 2007-06-20 ProcÉdÉ pour l'adressage de membres d'un agencement de circuits mis en cascade de par le matériel

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DE (1) DE102006029997A1 (fr)
WO (1) WO2008000667A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118885430A (zh) * 2024-08-07 2024-11-01 山东锐易电动科技有限公司 Spi通信硬件电路、配置从机及监测从机在线状态的方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2287689B1 (fr) 2009-07-27 2012-11-14 Ziehl-Abegg AG Dispositif et procédé d'adressage d'une unité esclave

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4428502A1 (de) * 1994-08-11 1996-02-15 Siemens Ag Bussystem
DE19621272A1 (de) * 1996-05-25 1997-11-27 Bosch Gmbh Robert Adressierungsvorrichtung für eine Nebenstation eines seriellen Bussystems und Verfahren zur Adressierung einer Nebenstation
DE10240832A1 (de) * 2002-09-04 2004-03-18 Robert Bosch Gmbh Bus
DE10036643B4 (de) * 2000-07-26 2005-12-22 Robert Bosch Gmbh Verfahren und Vorrichtung zur Auswahl von Peripherieelementen
EP1622039A1 (fr) * 2004-07-30 2006-02-01 SICK MAIHAK GmbH Méthode et dispositif pour l'attribution d'adresses aux utilisateurs d'un système de bus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4428502A1 (de) * 1994-08-11 1996-02-15 Siemens Ag Bussystem
DE19621272A1 (de) * 1996-05-25 1997-11-27 Bosch Gmbh Robert Adressierungsvorrichtung für eine Nebenstation eines seriellen Bussystems und Verfahren zur Adressierung einer Nebenstation
DE10036643B4 (de) * 2000-07-26 2005-12-22 Robert Bosch Gmbh Verfahren und Vorrichtung zur Auswahl von Peripherieelementen
DE10240832A1 (de) * 2002-09-04 2004-03-18 Robert Bosch Gmbh Bus
EP1622039A1 (fr) * 2004-07-30 2006-02-01 SICK MAIHAK GmbH Méthode et dispositif pour l'attribution d'adresses aux utilisateurs d'un système de bus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118885430A (zh) * 2024-08-07 2024-11-01 山东锐易电动科技有限公司 Spi通信硬件电路、配置从机及监测从机在线状态的方法

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