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WO2008090835A1 - Procédé de fabrication de cartes de circuits imprimés multicouches - Google Patents

Procédé de fabrication de cartes de circuits imprimés multicouches Download PDF

Info

Publication number
WO2008090835A1
WO2008090835A1 PCT/JP2008/050680 JP2008050680W WO2008090835A1 WO 2008090835 A1 WO2008090835 A1 WO 2008090835A1 JP 2008050680 W JP2008050680 W JP 2008050680W WO 2008090835 A1 WO2008090835 A1 WO 2008090835A1
Authority
WO
WIPO (PCT)
Prior art keywords
printed wiring
multilayer printed
roughening
composition
production
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/050680
Other languages
English (en)
Japanese (ja)
Inventor
Shigeo Nakamura
Eiichi Hayashi
Genjin Mago
Tadahiko Yokota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ajinomoto Co Inc
Original Assignee
Ajinomoto Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ajinomoto Co Inc filed Critical Ajinomoto Co Inc
Priority to JP2008555044A priority Critical patent/JPWO2008090835A1/ja
Publication of WO2008090835A1 publication Critical patent/WO2008090835A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
    • H05K3/387—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive for electroless plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/066—Transfer laminating of insulating material, e.g. resist as a whole layer, not as a pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

L'invention concerne un procédé pour la fabrication de cartes de circuits imprimés multicouches qui permet de former un film diélectrique intercouche qui présente une rugosité de surface provoquée par une rugosification de surface réduite, pour préparer une surface de substrat appropriée pour un plaquage et qui permet un déglaçage complet dans un traitement de déglaçage effectué simultanément à la rugosification de surface ; et un film adhésif devant être utilisé dans le procédé. L'invention concerne un film adhésif devant être laminé avec un matériau de base pour carte de circuits imprimés et ainsi utilisé en tant que film diélectrique intercouche d'une carte de circuits imprimés multicouches, lequel film est composé d'un support et d'une couche de substrat faite à partir de la première composition de résine durcissable et d'une couche adhésive faite à partir de la seconde composition de résine durcissable qui sont formées sur le support dans cet ordre, la première composition de résine durcissable étant une composition qui présente une perte de masse due à la rugosification de moins de 3% en masse lorsqu'une couche (de 40μm d'épaisseur) de la composition est soumise au même traitement de durcissement et de rugosification que celui employé dans la fabrication d'une carte de circuits imprimés multicouches, et la seconde composition de résine durcissable étant une composition qui présente une perte de masse due à la rugosification de 3 ou 10% en masse lorsqu'une couche (de 40μm d'épaisseur) de la composition est soumise au même traitement de durcissement et de rugosification que celui employé dans la fabrication d'une carte de circuits imprimés multicouches, à la condition que toute les exigences suivantes soient satisfaites : 10μm ≤ X+Y ≤ 100μm, 1μm < X, et 1μm < Y (où X est l'épaisseur (μm) de la couche de substrat et Y est l'épaisseur (μm) de la couche adhésive).
PCT/JP2008/050680 2007-01-23 2008-01-21 Procédé de fabrication de cartes de circuits imprimés multicouches Ceased WO2008090835A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008555044A JPWO2008090835A1 (ja) 2007-01-23 2008-01-21 多層プリント配線板の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007012208 2007-01-23
JP2007-012208 2007-01-23

Publications (1)

Publication Number Publication Date
WO2008090835A1 true WO2008090835A1 (fr) 2008-07-31

Family

ID=39644412

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/050680 Ceased WO2008090835A1 (fr) 2007-01-23 2008-01-21 Procédé de fabrication de cartes de circuits imprimés multicouches

Country Status (3)

Country Link
JP (1) JPWO2008090835A1 (fr)
TW (1) TWI441853B (fr)
WO (1) WO2008090835A1 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010153839A (ja) * 2008-11-26 2010-07-08 Kyocer Slc Technologies Corp 配線基板の製造方法
JP2010267712A (ja) * 2009-05-13 2010-11-25 Sekisui Chem Co Ltd 多層回路基板の製造方法
JP2012094799A (ja) * 2010-09-27 2012-05-17 Sekisui Chem Co Ltd エポキシ樹脂材料及び多層基板
KR20140005783A (ko) * 2012-07-06 2014-01-15 아지노모토 가부시키가이샤 절연 수지 시트
JP2014013854A (ja) * 2012-07-05 2014-01-23 Ajinomoto Co Inc 支持体付き樹脂シート
JP2014187091A (ja) * 2013-03-22 2014-10-02 Ajinomoto Co Inc 絶縁樹脂シート
CN104685979A (zh) * 2012-09-27 2015-06-03 积水化学工业株式会社 多层基板的制造方法、多层绝缘膜及多层基板
JP2017050561A (ja) * 2016-11-16 2017-03-09 味の素株式会社 絶縁樹脂シート
JP2018027703A (ja) * 2017-11-13 2018-02-22 味の素株式会社 絶縁樹脂シート

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101682886B1 (ko) * 2009-07-14 2016-12-06 아지노모토 가부시키가이샤 동박이 부착된 접착 필름

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11172457A (ja) * 1997-12-05 1999-06-29 Ibiden Co Ltd 無電解めっき用接着剤および多層プリント配線板
JP2003304068A (ja) * 2002-04-05 2003-10-24 Mitsui Mining & Smelting Co Ltd プリント配線板用樹脂付金属箔及びこれを用いた多層プリント配線板
JP2004356238A (ja) * 2003-05-27 2004-12-16 Matsushita Electric Works Ltd 金属箔付き絶縁シート、多層配線板、及び多層配線板の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11172457A (ja) * 1997-12-05 1999-06-29 Ibiden Co Ltd 無電解めっき用接着剤および多層プリント配線板
JP2003304068A (ja) * 2002-04-05 2003-10-24 Mitsui Mining & Smelting Co Ltd プリント配線板用樹脂付金属箔及びこれを用いた多層プリント配線板
JP2004356238A (ja) * 2003-05-27 2004-12-16 Matsushita Electric Works Ltd 金属箔付き絶縁シート、多層配線板、及び多層配線板の製造方法

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010153839A (ja) * 2008-11-26 2010-07-08 Kyocer Slc Technologies Corp 配線基板の製造方法
JP2010267712A (ja) * 2009-05-13 2010-11-25 Sekisui Chem Co Ltd 多層回路基板の製造方法
JP2012094799A (ja) * 2010-09-27 2012-05-17 Sekisui Chem Co Ltd エポキシ樹脂材料及び多層基板
JP2014013854A (ja) * 2012-07-05 2014-01-23 Ajinomoto Co Inc 支持体付き樹脂シート
KR20140005783A (ko) * 2012-07-06 2014-01-15 아지노모토 가부시키가이샤 절연 수지 시트
JP2014017301A (ja) * 2012-07-06 2014-01-30 Ajinomoto Co Inc 絶縁樹脂シート
KR102000921B1 (ko) 2012-07-06 2019-07-17 아지노모토 가부시키가이샤 절연 수지 시트
CN104685979B (zh) * 2012-09-27 2018-11-16 积水化学工业株式会社 多层基板的制造方法、多层绝缘膜及多层基板
CN104685979A (zh) * 2012-09-27 2015-06-03 积水化学工业株式会社 多层基板的制造方法、多层绝缘膜及多层基板
JPWO2014050871A1 (ja) * 2012-09-27 2016-08-22 積水化学工業株式会社 多層基板の製造方法、多層絶縁フィルム及び多層基板
US9888580B2 (en) 2012-09-27 2018-02-06 Sekisui Chemical Co., Ltd. Method for manufacturing multilayer substrate, multilayer insulation film, and multilayer substrate
JP2014187091A (ja) * 2013-03-22 2014-10-02 Ajinomoto Co Inc 絶縁樹脂シート
JP2017050561A (ja) * 2016-11-16 2017-03-09 味の素株式会社 絶縁樹脂シート
JP2018027703A (ja) * 2017-11-13 2018-02-22 味の素株式会社 絶縁樹脂シート

Also Published As

Publication number Publication date
TW200840839A (en) 2008-10-16
JPWO2008090835A1 (ja) 2010-05-20
TWI441853B (zh) 2014-06-21

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