WO2008078229A1

WO2008078229A1 - Bist integrated circuit testing

Info

Publication number: WO2008078229A1
Application number: PCT/IB2007/055087
Authority: WO
Inventors: Friedrich Hapke; Juergen Schloeffel; Andreas Glowatz
Original assignee: NXP BV
Current assignee: NXP BV
Priority date: 2006-12-20
Filing date: 2007-12-13
Publication date: 2008-07-03
Anticipated expiration: 2009-06-20

Abstract

An integrated circuit comprises a BIST architecture having a linear feedback shift register, a BIST controller for controlling a seed value supplied to the linear feedback shift register and a circuit under test which comprises a plurality of flip flop scan chains, wherein the outputs from the linear feedback shift register are provided to the scan chains. A first memory device stores flip flop deterministic state values for flip flops in each scan chain, and a multiplexer arrangement routes the flip flop deterministic state values to the scan chains in preference to the linear feedback shift register output. This structure enables flip flop deterministic state values to be supplied to the scan chains, bypassing the LFSR. This means that these flip flop values can assumed to have the required outputs when calculating the LFSR seed value for a particular test pattern, and this simplifies the equations used to generate the initial seed value for the LSFR.

Description

DESCRIPTION

BIST INTEGRATED CIRCUIT TESTING

This invention relates to BIST (Built-in-self-test) circuit testing, namely the testing of Integrated Circuits (ICs), their "Design for Testability" (DfT), and their computer-aided design/test (CAD/CAT). The invention is of particular interest for ICs with a very high integration density and the use of logic-built-in self-test (LBIST) to identify production faults in the logic part of the circuit.

During the production of ICs with a very high integration density, very high clocking rates, and a very high number of test vectors, there are many problems and costs related to production testing. The high test costs are caused by the required very complex VLSI test systems with a large amount of tester vector memory.

To solve these problems a built-in self-test is used more and more. Logic built-in self-test (LBIST) implies that self-test hardware is added during digital logic circuit design. The LBIST hardware provides on-chip generation of test stimuli that are applied to the circuit-under-test (CUT) and on-chip evaluation of the corresponding test responses of the CUT, as shown in Figure 1.

The CUT typically contains scan chains, which requires that the flip- flops in the CUT can be configured into serial shift registers ('scan chains') in test mode. The self-test is performed by repeatedly generating test stimuli that are shifted into the scan chains, operating the circuit for a number of clock cycles in its functional application mode, and shifting out and evaluating the test responses.

Theoretically, a chip can be tested by inputting, to the various logic devices on the chip, every possible input combination. Every output created by these inputs would then be viewed to determine if the correct output was captured. This would be perfect fault coverage. However, an exhaustive test involves such an extensive number of test patterns that it is expensive to apply. One way to implement LBIST testing is therefore to use a pseudorandom pattern generator, resulting in a "random LBIST" procedure. Early in the test process, when there are many faults that are untested, random LBIST is relatively productive. However, as fault coverage climbs and fewer untested faults remain, random LBIST begins generating a high ratio of unproductive tests.

An improvement to random LBIST is to simulate a representative model of possible faults in the device and determine which inputs or care bits are required to test each of these faults. Tests are generated that provide these required inputs, and the corresponding faults may then be marked as being covered. Historically, deterministic stored pattern testing has avoided the problems of random LBIST by determining these required inputs and using the inputs to test the device under test. Deterministic stored pattern testing entails analyzing the logic devices on the device under test and determining the inputs that would test particular faults.

To perform deterministic stored pattern testing, pre-calculated, stored deterministic patterns are downloaded from the tester into the chip. These deterministic patterns contain the important care bits to test particular faults, and they contain these important bits in the correct positions. The LBIST test is initiated by a stimulus in the form of a seed, and the value of this seed determines the test pattern to be generated. Stimuli generation for built-in self-test application can be implemented with a bit- flipping function, to improve the random testability of a circuit, or by using ROM-based stimuli generation. When the test stimulus generation is based on a ROM where initial values are stored, these values are used as an input to a Linear Feedback Shift Register (LFSR) typically coupled with a Phase Shifter (PS). The LFSR is used to generate either a random pattern or a deterministic pattern. The PS is used to reduce the correlation between neighbouring LFSR outputs. This is the general state of the art.

Through symbolic simulation of the LFSR, PS and the scan chains, the dependencies between the LFSR inputs and the Flip Flop states in the scan chains are determined. As a result, a set of linear equations is received. This set of linear equations expresses the relationship between the starting data supplied to the LFSR (the seed) and the desired output sequence. Typically, the scan chains of the device under test function as a simple shift register, so that the flip flop values do not alter as they are shifted along the scan chains of the device under test. By solving this set of equations, the required seed value to be input to the LFSR can be determined which will give rise to a desired test pattern.

An Automated Test Pattern Generation (ATPG) tool is used to determine the initial states of the Linear Feedback Shift Register (LFSR) for all of the desired test patterns by solving this set of linear equations. Typically, a test process can involve thousands (for example 1 to 10 thousand) test patterns applied to the scan chains. The storing of a seed value for each test pattern reduces significantly the amount of memory requires, as each seed value has a size corresponding to the size of the LSFR, for example between 64 and 256 bits, whereas the test vector to be applied to the device under test corresponds in size to the length of the scan chain of the device under test, for example thousands, tens of thousands or even hundreds of thousands of bits.

The seed values are stored in a ROM. For a built-in self-test of the logic it is important to have a very limited size/number of ROM words, otherwise the ROM would have an unacceptable size. Typically there is one seed word per test pattern (although it is possible to use a seed for more than one pattern).

For current integrated circuits, the number of flip flops in the scan chains is very high as mentioned above. This leads to a huge number of linear equations with cross dependencies. Often it is not possible to solve the set of equations in order to get the right states at the flip flops. This means test coverage loss. In order to solving the linear equations, it may be required to increase the size of the LSFR, which is directly related to the ROM size.

According to the invention, there is provided an integrated circuit comprising a BIST architecture, wherein the BIST architecture comprises: a linear feedback shift register; a BIST controller for controlling a seed value supplied to the linear feedback shift register; a circuit under test which comprises a plurality of flip flop scan chains, wherein the outputs from the linear feedback shift register are provided to the scan chains; a first memory device storing commonly occurring flip flop deterministic state values; and a multiplexer arrangement for routing the flip flop deterministic state values to the scan chains in preference to the linear feedback shift register output.

This structure enables flip flop deterministic state values to be supplied to the scan chains, bypassing the LFSR. This means that these flip flop values can assumed to have the required outputs when calculating the LFSR seed value for a particular test pattern, and this simplifies the equations used to generate the initial seed value for the LSFR. Thus, the deterministic patterns are calculated assuming the flip flop deterministic state values. In other words, the output values for the LSFR can become don't care states for the purpose of simplifying the linear equations, because the deterministic flip flop values will override the LSFR values generated. The first memory device stores the seed patterns, typically with one seed value per test pattern.

The LSFR outputs may be supplied to the scan chains via a phase shifter.

A second memory device can be provided for storing deterministic patterns, namely the calculated seed values. A third memory device can be provided for storing timing information relating to the timing at which the flip flop deterministic state values are to be supplied to the scan chains. In order to control the timing at which the flip flop deterministic state values are supplied to the scan chains (so that they reach the required scan chain position at the correct time) a down counter can be provided, and the down counter output can be provided to a logic array, such that the flip flop deterministic state values are provided from the first memory device to the scan chains only when the down counter reaches zero. The rest of the time, flip flop values are loaded from the LFSR (and optional phase shifter).

The deterministic state flip flop value preferably comprises a flip flop value which occurs more than a predetermined fraction of the time during an automatic test pattern generation process, for example above a threshold, for example a threshold somewhere between 80% and 100%.

The invention also provides a method for implementing built in self testing of a circuit under test which comprises a plurality of flip flop scan chains, in which a linear feedback shift register provides outputs to the scan chains, the method comprising: selecting commonly occurring flip flop deterministic state values for the flip flops in the scan chains during a pre-test ATPG process; during an ATPG process, calculating a deterministic seed pattern for the linear feedback shift register by solving a set of linear equations which ignores the effect of the deterministic seed pattern on the flip flops which have had deterministic state values selected; providing the seed value to the linear feedback shift register; and routing the selected flip flop deterministic state values to the scan chains in preference to the linear feedback shift register output.

Embodiments of the invention will now be described, purely by way of example, with reference to the accompanying drawings, in which:

Figure 1 shows the known basic BIST architecture; Figure 2 shows an example of BIST architecture of the invention;

Figure 3 shows how flip flop deterministic state values can be obtained; Figure 4 is used to explain how deterministic state values can be derived for each flip flop in each scan chain;

Figure 5 shows how the deterministic state values can be stored in a first memory;

Figure 6 shows how timing information relating to the deterministic state values can be stored in a second memory.

The invention provides a test architecture in which already known values for the flip flops in the scan chains are stored in an additional memory device before the set of linear equations has to be solved by the ATPG. This reduces the need to calculate all of the initial values. Only those which are not pre-defined have to be calculated in the equation system. This leads to a higher probability for a successful solution of the linear equations system and consequently to higher fault coverage, and it reduces the overall size of the ROM significantly and saves area and test costs.

Figure 2 shows the integrated circuit elements for the BIST architecture of the invention. The circuit comprises a conventional linear feedback shift register which can be combined with a phase shifter as shown as 10. A BIST controller 12 controls the application of a seed value to the linear feedback shift register 10.

The circuit under test 14 comprises a plurality of flip flop scan chains, shown as scan chain 1 with flip flops FF11 , FF12, ... , FF1 m, scan chain 2 with flip flops FF21 , FF22, ... FF2m, and so on.

There will typically be thousands of flips flops in each scan chain, for example tens or hundreds of thousands, and a large number of scan chains, for example hundreds or thousands. The outputs from the linear feedback shift register 10 are provided to the scan chains through multiplexers 16.

The invention provides a first memory device 18 storing flip flop deterministic state values for each flip flop in each scan chain. This means flip flop values rather than LSFR seed values, and these values are selected based on the test vector to be applied to the device under test, i.e. they are deterministic values. These flip flop deterministic state values can be routed to the scan chains in preference to the linear feedback shift register output.

This first memory device is named a "pre-defined combination ROM" in the following, as it stores predefined combinations of flip flop deterministic state values, on a per-pattern basis.

This structure enables flip flop deterministic state values to be supplied to the scan chains, bypassing the LFSR. This means that these flip flop values can be assumed to have the required outputs when calculating the LFSR seed value for a particular test pattern, and this simplifies the equations used to generate the initial seed value for the LSFR. Thus, the deterministic patterns are calculated assuming the flip flop deterministic state values.

A second memory device 20 stores the deterministic patterns, namely the calculated seed values. This is named a "deterministic pattern ROM" in the following. A third memory device 22 stores timing information relating to the timing at which the flip flop deterministic state values are to be supplied to the scan chains. This is named a "restriction ROM" in the following, as it stores the information which enables the restricted set of linear equations to be solved. A "restrict" is one set of flip flop deterministic state values which can be used to simplify the linear equations to be solved.

The third memory device is used to provide control data for controlling the timing of insertion of the flip flop deterministic state values into the scan chains. This timing data 24 is provided to a down counter 26 which has an output 28 which counts down to zero. This output is used to control a logic array 30, shown as a bank of NAND gates, and these control the multiplexers 16, so that only when the counter is at zero can the deterministic state flop values 32 bypass the LSFR output. The rest of the time, flip flop values are loaded from the LFSR. The down counter 26 thus implements wait cycles.

An address counter 34 is used to select the correct timing information from the third memory device 22.

The memory devices 18 and 22 do not need to be of large capacity. The circuit thus provides a MicroROM based extension to feed pre-defined values to the scan chains.

In operation, the BIST Controller 12 starts both the address counter 34 and the down counter 26 with the signal 36. In parallel, the BIST Controller selects a certain restrict for a pattern from the Deterministic pattern ROM 20, as shown by control signal 38.

The address counter 34 is provided with the restrict number as shown by signal line 40 and points to the corresponding data in the Restriction ROM 22, as shown by signal line 42.

The down counter 26 is loaded with the first number of wait cycles (signal line 24) from that restrict in the Restriction ROM 22. As long as the value of this counter is not 0 no values from the Pre-defined combination ROM 18 are used for the chains. The down counter 26 counts down. When the count reaches 0, the flip flop deterministic state values from the Pre-defined combination ROM 18 are used to feed the scan chains. Only the pre-defined deterministic state values are fed. The address of the pattern of deterministic state values is delivered by the Restriction ROM 22 as shown by signal line 44. With the ready-signal 28, the address counter 34 is incremented and points to the next word in the Restriction ROM 22, and the new wait cycles are loaded to the down counter. A sequence is thus followed, in which the restriction ROM provides the timing to the next required insertion of flip flop deterministic state values, and controls the memory device 18 to select the required deterministic state values, for a given seed value being used from the Deterministic Pattern ROM 20. The way in which the deterministic state values are derived will now be explained.

In a pre-test pattern generation run, those flip flops are identified which have well defined values like 0 or 1 most of the time. This pre-test pattern generation run involves determining the test patterns which are desired, but does not involve calculating the seed values.

To determine the specific flip flops where pre-defined values can be used, a threshold value has to be set.

Figure 3 shows how many times each flip flop has a defined value

(either 1 or 0)during the pre-test pattern generation ATPG run. As shown, some flip flops have a very high occurrence of a defined value of 0 or 1.

When either value arises more than a given fraction of the time (e.g. 90%), the value can be taken to be a deterministic state value.

In the given example, FF11 , FF31 , FF41 , FF51 , FF61 , FF22, FF32 and FF42 are often set to the defined values shown. This information is used by the Test Pattern Generator for the first run.

The deterministic state flip flop pattern is used to simplify the set of linear equations to be solved to enable the seed value to be generated, and the deterministic state flip flop pattern is stored. Assuming the set of linear equations can be solved, the ATPG progresses to the test pattern for the second fault.

For the second fault, the ATPG uses the already existing test pattern {0-1100-110--} to search for a solution of the linear equation system.

If no solution can be found, new values can be set for the flip flops above the threshold. As an example for the generation of the second pattern the values of those flip flops could be {0-1101 -101 --}. This set of deterministic values could be based on a reduced set of stuck-at faults to be covered by the test pattern. The ATPG will choose the new pattern.

This new pattern then will be stored in the Pre-defined Combination ROM 18 as well. For the third fault the ATPG already has two patterns available to start with and to solve the equations and so on.

Thus, the end result is that for each pattern, there is a predetermined set of flip flop values which can be used, and which have enabled a solution to the simultaneous equations to be obtained, so that the calculated seed value, in combination with the deterministic state values, will result in the required test pattern being provided to the scan chains.

This process will end up with a set of pre-defined and stored test patterns for the flip flops above the limit given by the threshold value, and which is much smaller than applying all possible combinations. Figure 4 is used to show how the deterministic state values can be obtained. For the scan chains as shown in Figure 2, a set of flip flop values above the given threshold can been found, and Figure 4 is an example.

Figure 4 shows data that can be obtained for each flip flop position in the scan chains, and shows the deterministic state values for those flip flops for each different test pattern.

The cycle number along the x-axis corresponds to the depth of a flip flop with the scan chain. For example, the data for cycle 10 indicates that the 10^th flip flop in chains 1 , 3 and 6 have the shown values appearing with a frequency above the threshold. The deterministic values are allocated "combination values", to reduce the amount of data stored. Thus, in the example shown there are four combination values C1 to C4 to encode the six columns of data. The x-axis will extend to a cycle number corresponding to the number of flip flops in the scan chains, for example 1000. Nine cycles later, at cycle 19, two flip flops in the chains 2 and 4 were found and so on.

Based on this information, these pre-defined values are be stored in the Pre-defined Combination ROM 18 for example in the format shown in Figure 5. The content of the Restriction ROM 22 is shown in Figure 6. For each restrict (i.e. set of deterministic values to enable a simplified solution to the set of linear equations), the information about the cycle time and the corresponding combination is stored. This ROM 22 thus stores the timings at which deterministic state values can be supplied to the scan chains, and indicates the combinations of deterministic values to be applied to the multiple scan chains.

The number of stored values in the Pre-defined Combination ROM 18 is likely to be small compared to the number of all possible combinations, for example 2⁸=256 combinations for 8 scan chains.

The more pre-defined values are known, the easier it is to solve the linear equation system successfully and therefore to higher fault coverage.

This will result in a much smaller ROM size and therefore decrease the area requirements to store deterministic test pattern on chip significantly. The circuit blocks used to implement the circuit are all standard and the circuits have accordingly not been described in detail. Furthermore, only one example of deterministic pattern generation circuit has been given. Other designs will be possible.

The term "deterministic state" is used to indicate flip flop values that are pre-selected based on the determined test vector, rather than generated by the LFSR. Thus, they may be considered to be "override" flip flop values. The term should be understood in this context, and it will be clear form the above, that the deterministic state values can change between different linear equation calculations. Various other modifications will be apparent to those skilled in the art.

Claims

1. An integrated circuit comprising a BIST architecture, wherein the BIST architecture comprises: a linear feedback shift register (10); a BIST controller (12) for controlling a seed value supplied to the linear feedback shift register; a circuit under test (14) which comprises a plurality of flip flop scan chains, wherein the outputs from the linear feedback shift register (10) are provided to the scan chains; a first memory device (18) storing commonly occurring flip flop deterministic state values; and a multiplexer arrangement (16) for routing the flip flop deterministic state values to the scan chains in preference to the linear feedback shift register output.

2. A circuit as claimed in claim 1 , further comprising a second memory device (20) for storing deterministic patterns.

3. A circuit as claimed in claim 2, wherein the deterministic patterns are calculated ignoring the effect on the flip flops having deterministic state values.

4. A circuit as claimed in any preceding claim, further comprising a third memory device (22) for storing timing information relating to the timing at which the flip flop deterministic state values are to be supplied to the scan chains.

5. A circuit as claimed in claim 4, wherein the third memory device (55) is for storing timing information for a plurality of test patterns.

6. A circuit as claimed in claim 4 or 5, further comprising a down counter (26) for controlling the timing at which the flip flop deterministic state values are supplied to the scan chains.

7. A circuit as claimed in claim 6, wherein the down counter output is provided to a logic array (30), such that the flip flop deterministic state values are provided from the first memory device (18) to the scan chains only when the down counter (26) reaches zero.

8. A circuit as claimed in any preceding claim, wherein the first memory device (18) stores flip flop deterministic state values for a plurality of test patterns.

9. A circuit as claimed in any preceding claim, wherein a deterministic state flip flop value comprises a flip flop value which occurs more than a predetermined fraction of the time during an automatic test pattern generation process.

10. A circuit as claimed in claim 9, wherein the predetermined fraction is between 80% and 100%.

11. A method for implementing built in self testing of a circuit under test which comprises a plurality of flip flop scan chains, in which a linear feedback shift register (10) provides outputs to the scan chains, the method comprising: selecting commonly occurring flip flop deterministic state values for the flip flops in the scan chains during a pre-test ATPG process; during an ATPG process, calculating a deterministic seed pattern for the linear feedback shift register by solving a set of linear equations which ignores the effect of the deterministic seed pattern on the flip flops which have had deterministic state values selected; providing the seed value to the linear feedback shift register; and routing the selected flip flop deterministic state values to the scan chains in preference to the linear feedback shift register output.

12. A method as claimed in claim 11 , wherein the flip flop deterministic state values are routed using timing information stored in a timing information memory device (22).

13. A method as claimed in claim 12, further comprising controlling a down counter (26) for controlling the timing at which the flip flop deterministic state values are supplied to the scan chains.

14. A method as claimed in claim 12, wherein the down counter output is provided to a logic array (30), such that the flip flop deterministic state values are provided from the first memory device to the scan chains only when the down counter reaches zero.

15. A method as claimed in any preceding claim, further comprising storing the flip flop deterministic state values for a plurality of test patterns.

16. A method as claimed in any one of claims 11 to 15, wherein the selecting comprises identifying flip flops having a flip flop value which occurs more than a predetermined fraction of the time.

17. A method as claimed in claim 16, wherein the predetermined fraction is between 80% and 100%.