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Alves et al., 2009 - Google Patents

A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns

Alves et al., 2009

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Document ID
18218678813327173131
Author
Alves D
Barros E
Publication year
Publication venue
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

External Links

Snippet

The claim for new functionalities regarding the improvement of dependability of electronic systems and also the need for managing the time spent during test make the Built-in-Self- Test mechanism (BIST) a promising feature to be integrated in current IC flows. There are a …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

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    • G01R31/317—Testing of digital circuits
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    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits

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