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WO2007038297A2 - Systemes et procedes permettant de fabriquer des dispositifs photovoltaiques - Google Patents

Systemes et procedes permettant de fabriquer des dispositifs photovoltaiques Download PDF

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Publication number
WO2007038297A2
WO2007038297A2 PCT/US2006/037029 US2006037029W WO2007038297A2 WO 2007038297 A2 WO2007038297 A2 WO 2007038297A2 US 2006037029 W US2006037029 W US 2006037029W WO 2007038297 A2 WO2007038297 A2 WO 2007038297A2
Authority
WO
WIPO (PCT)
Prior art keywords
cells
contacts
die
wafer
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/037029
Other languages
English (en)
Other versions
WO2007038297A3 (fr
Inventor
Tom Rust
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to EP06815202A priority Critical patent/EP1938388A2/fr
Priority to CA002623382A priority patent/CA2623382A1/fr
Priority to JP2008532426A priority patent/JP2009510724A/ja
Publication of WO2007038297A2 publication Critical patent/WO2007038297A2/fr
Publication of WO2007038297A3 publication Critical patent/WO2007038297A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H10F10/144—Photovoltaic cells having only PN homojunction potential barriers comprising only Group III-V materials, e.g. GaAs,AlGaAs, or InP photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/127—The active layers comprising only Group III-V materials, e.g. GaAs or InP
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H10F77/147—Shapes of bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings
    • H10F77/306—Coatings for devices having potential barriers
    • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
    • H10F77/315—Coatings for devices having potential barriers for photovoltaic cells the coatings being antireflective or having enhancing optical properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • FIG. 1 illustrates a photovoltaic cell assembly in accordance with one embodiment of the present invention
  • FIG. 2 illustrates an array of photovoltaic cells in accordance with one embodiment of the present invention
  • FIG. 11 illustrates a front/rear view of the cell of FIG. 7 in one possible orientation, with a set of interconnect lines overlaid and with potentials for each line in accordance with one embodiment of the present invention
  • a silicon nitride mask layer about 2,OO ⁇ A thick in one embodiment is deposited on all sides of the wafer.
  • the wafer then can be prepared for photoresist deposition, such as by applying a Hexamethyldisilazane (HMDS) primer to serve as an adhesion promoter for photoresist.
  • HMDS Hexamethyldisilazane
  • the resist then can be spun on the front and back side of the device, applying the resist to the front and back simultaneously or at different times.
  • a jig is used that has a large plate with three pins.
  • cells 502 can be loaded onto the substrate using a dry vibratory process.
  • the die can be packaged randomly, or in strips or lots, and can be dry flowed over the assembly fixture grid 500, such as is shown to fill in a small section of the grid in FIG. 5, although it should be understood that the cells can be flowed to fill in the entire grid or selected sections of the grid.
  • the die can be flowed with a small amount of vibration, and flowed into the target receptacles in the assembly fixture grid. There can be a slight inclination to the surface of the assembly fixture grid in order to allow gravity to assist the flow of cells.
  • Such a process can be used to assemble large panels of these cells in a quick and relatively inexpensive manner.
  • a similar via pattern is exposed and etched on the oac ⁇ si ⁇ e oi me water, but tne via slots 702 are made to align in between the slots made on the top of the wafer as shown in the side view 700 of FIG. 7.
  • the nitride etch is only extended part way through the wafer as the nitride layer is still needed.
  • an oxide layer may be deposited over the nitride layer to allow a wet etch process to transfer the resist pattern to the nitride layer.
  • the top of the device then can be patterned for a deep etch procedure, with the patterned resist being baked by an appropriate baking procedure.
  • the exposed top nitride layer can be etched down to the silicon, and the resist subsequently removed.
  • a similar procedure can be used for the bottom of the wafer, with the wafer being prepared for the resist deposition using a solvent based priming procedure, such as an HMDS priming procedure, with the resist then being spun on the front side of the device and the bottom of the device being patterned for deep etch.
  • the resist can be baked and the bottom nitride layer etched down to the silicon. The resist then can be removed.
  • a nitride layer can be deposited on each side of the device.
  • the wafer then can be prepared for photoresist deposition, such as by applying a Hexamethyldisilazane (HMDS) primer to serve as an adhesion promoter for photoresist.
  • HMDS Hexamethyldisilazane
  • the resist then can be spun on the front side of the device.
  • the top of the device can be patterned for a deep etch procedure, with the patterned resist then being baked by an appropriate baking procedure.
  • the exposed top nitride layer can be etched down to the silicon, and the resist subsequently removed.
  • the POCL diffusion can form a glass or glaze on the device that can be removed from the top and bottom of the device where the contacts are to be placed, as the POCL can regrow some oxide on the top and bottom surfaces.
  • at least one redrive step can be used as known in the art.
  • a redrive step can be performed by soaking in a furnace, or can be combined with a dry or wet thermal oxidization step to passivate the exposed areas of the wafer. This can help to minimize crystal defects. At this point, more measurements of the diode properties can be made to measure properties of device.
  • a combination of fluidic and vibratory processes can be used to load the cells onto the substrate.
  • the fluid can be removed and the cells/substrate dried as known in the art.
  • the fluid can be a simple liquid, such as de- ionized water, or can have any of a number of other desirable properties.
  • the liquid can have surfactant properties that improve the flow of the fluid and cells, and that improve the flow of the die over each other.
  • the indentations in the substrate also can be patterned with a material that would give the die a particular attraction to that location, such that when a dies gets into that position the die tends to stay in that position.
  • the process of loading may be discrete, wherein the substrates are individual panels, or roll fed, wherein the substrate is a continuous ribbon of material fed through the processing regions which supply the cells.
  • the cells then can have a pattern of interconnect 1100 formed as shown, for example, in FIG. 11.
  • the interconnect can be silk screened, inkjet printed, or otherwise deposited to flow over and into the contact vias, such as using some form of conductive paste such as silver epoxy.
  • Other techniques for depositing the interconnect such as using a patterned roller, can be used as known in the art.
  • Another advantage of such a process is that the above described process steps, although similar in complexity to the processing needed for conventional cells, need only be performed on one wafer, whereas a similar processing must be performed on five wafers to obtain the same device. This results in additional savings in the processing costs.

Landscapes

  • Photovoltaic Devices (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

L'invention concerne un dé pour des cellules photovoltaïques qui peut être fabriqué au moyen d'une région de motifs qui couvre sensiblement la surface utilisable d'une pièce cristalline. Des barres peuvent être gravées sur la pièce de façon qu'elles s'étendant sensiblement sur toute la longueur de la pièce. Ces barres peuvent ensuite être coupées en petits morceaux afin de former un dé ayant une largeur sensiblement égale à l'épaisseur de la pièce et un ratio de bord d'environ 20:1 ou moins. Ce procédé permet de maximiser la zone de conversion, ce qui permet d'extraire davantage d'énergie d'un volume donné de matériau de conversion photovoltaïque. Des contacts peuvent être placés sur des bords opposés du dé afin de former des cellules photovoltaïques, qui, dans certains modes de réalisation, fonctionnent quelle que soit l'orientation dans un panneau solaire.
PCT/US2006/037029 2005-09-23 2006-09-21 Systemes et procedes permettant de fabriquer des dispositifs photovoltaiques Ceased WO2007038297A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP06815202A EP1938388A2 (fr) 2005-09-23 2006-09-21 Systemes et procedes permettant de fabriquer des dispositifs photovoltaiques
CA002623382A CA2623382A1 (fr) 2005-09-23 2006-09-21 Systemes et procedes permettant de fabriquer des dispositifs photovoltaiques
JP2008532426A JP2009510724A (ja) 2005-09-23 2006-09-21 光起電力装置製造のシステムおよび方法

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US72008405P 2005-09-23 2005-09-23
US60/720,084 2005-09-23
US72652005P 2005-10-13 2005-10-13
US60/726,520 2005-10-13
US52556206A 2006-09-21 2006-09-21
US11/525,562 2006-09-21

Publications (2)

Publication Number Publication Date
WO2007038297A2 true WO2007038297A2 (fr) 2007-04-05
WO2007038297A3 WO2007038297A3 (fr) 2007-12-21

Family

ID=37900315

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/037029 Ceased WO2007038297A2 (fr) 2005-09-23 2006-09-21 Systemes et procedes permettant de fabriquer des dispositifs photovoltaiques

Country Status (4)

Country Link
EP (1) EP1938388A2 (fr)
JP (1) JP2009510724A (fr)
CA (1) CA2623382A1 (fr)
WO (1) WO2007038297A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2409313A1 (fr) * 2009-03-17 2012-01-25 Roth & Rau AG Installation de traitement de substrat et procédé de traitement de substrat
WO2011050889A3 (fr) * 2009-10-30 2012-05-03 Merck Patent Gmbh Procédé de fabrication de cellules solaires à émetteur sélectif

Family Cites Families (13)

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Publication number Priority date Publication date Assignee Title
US3556075A (en) * 1968-02-26 1971-01-19 Lockheed Aircraft Corp Photocell scoring tool
JPS61292340A (ja) * 1985-06-19 1986-12-23 Sharp Corp ウエハチツプ形成方法
US4735909A (en) * 1986-10-14 1988-04-05 Photon Energy, Inc. Method for forming a polycrystalline monolayer
US6084175A (en) * 1993-05-20 2000-07-04 Amoco/Enron Solar Front contact trenches for polycrystalline photovoltaic devices and semi-conductor devices with buried contacts
WO1999048136A2 (fr) * 1998-03-13 1999-09-23 Steffen Keller Configuration de cellule solaire
US6156967A (en) * 1998-06-04 2000-12-05 Tecstar Power Systems, Inc. Modular glass covered solar cell array
JP2002134782A (ja) * 2000-10-30 2002-05-10 Canon Inc 単結晶基体、それを用いた光電変換装置、放射線撮像装置、画像表示装置、太陽電池モジュール及び単結晶基体の製造方法
AUPR174800A0 (en) * 2000-11-29 2000-12-21 Australian National University, The Semiconductor processing
JP4036692B2 (ja) * 2002-06-27 2008-01-23 三洋電機株式会社 太陽電池モジュールの製造方法及び太陽電池セルの分離方法
JP2004221423A (ja) * 2003-01-16 2004-08-05 Renesas Technology Corp 半導体装置の製造方法
AU2003902270A0 (en) * 2003-05-09 2003-05-29 Origin Energy Solar Pty Ltd Separating and assembling semiconductor strips
KR101257786B1 (ko) * 2004-08-09 2013-04-30 트랜스폼 솔라 피티와이 리미티드 태양전지(슬라이버) 서브모듈 형성
EP1900038A4 (fr) * 2005-06-17 2012-01-04 Transform Solar Pty Ltd Procédé d interconnexion de piles solaires

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2409313A1 (fr) * 2009-03-17 2012-01-25 Roth & Rau AG Installation de traitement de substrat et procédé de traitement de substrat
WO2011050889A3 (fr) * 2009-10-30 2012-05-03 Merck Patent Gmbh Procédé de fabrication de cellules solaires à émetteur sélectif
US8723340B2 (en) 2009-10-30 2014-05-13 Merck Patent Gmbh Process for the production of solar cells comprising a selective emitter

Also Published As

Publication number Publication date
WO2007038297A3 (fr) 2007-12-21
CA2623382A1 (fr) 2007-04-05
EP1938388A2 (fr) 2008-07-02
JP2009510724A (ja) 2009-03-12

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