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WO2007032067A1 - Dispositif semi-conducteur et procédé de fabrication idoine - Google Patents

Dispositif semi-conducteur et procédé de fabrication idoine Download PDF

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Publication number
WO2007032067A1
WO2007032067A1 PCT/JP2005/016943 JP2005016943W WO2007032067A1 WO 2007032067 A1 WO2007032067 A1 WO 2007032067A1 JP 2005016943 W JP2005016943 W JP 2005016943W WO 2007032067 A1 WO2007032067 A1 WO 2007032067A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
region
semiconductor device
trench
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2005/016943
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English (en)
Japanese (ja)
Inventor
Sergey Pidin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2005/016943 priority Critical patent/WO2007032067A1/fr
Publication of WO2007032067A1 publication Critical patent/WO2007032067A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a logic embedded memory and a manufacturing method thereof.
  • a logic-embedded memory including a logic (logic) circuit and a memory (memory) circuit has characteristics of a high transfer rate and low power consumption, and is indispensable for realizing a high-function, high-value-added system.
  • Dynamic random access memory consists of one transistor / capacitor and one memory cell. Although it is a volatile memory that loses its memory when the power is turned off, it can be driven without the need for a high voltage like a flash memory.
  • Many capacitors dedicated to DRAMs are known to form a three-dimensional structure to improve the degree of integration. The three-dimensional structure manufacturing process is a special process that, when mixed with a logic circuit, reduces the reliability of the logic circuit.
  • STI shallow trench isolation
  • LOCOS silicon local oxidation
  • CMP chemical mechanical polishing
  • the memory capacitor of the logic embedded memory preferably has a planar structure in order to ensure reliability.
  • a planar structure capacitor is formed, the occupied area becomes large.
  • FIG. 1A and 1B show a DRAM cell structure proposed in Patent Document 1.
  • FIG. 1A is a plan view
  • FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. 1A.
  • the active region AR surrounded by the shallow trench isolation STI is equivalent to two transistors on the left and right, and the central wide portion is a contact region connected to the bit line. Intersects with narrow areas on both sides
  • the portion below the gate electrode G to be formed constitutes a channel.
  • a partial force sandwiched between both gate electrodes G for example, constitutes a common source region.
  • a region outside both the gate electrodes G forms a drain region and a part of the capacitor.
  • the main part of the capacitor is the area where the widths at both ends are widened.
  • an n-type wall NW is formed on a p-type substrate SUB.
  • the shallow trench isolation STI is formed to an intermediate depth of n-rule NW and defines the active area AR (Fig. 1A).
  • a recess is formed in the STI, and the active region side wall shown in bold in FIG. 1A is exposed.
  • a capacitor dielectric film 58 is formed.
  • a polycrystalline silicon film 60 is deposited and etched using a resist mask to form a gate electrode 60g and a capacitor counter electrode 60c.
  • a low concentration p-type impurity is ion-implanted to form the source LDD region 61 and simultaneously form the drain region 62.
  • the sidewall spacer 64 is formed, ion implantation of high-concentration p-type impurities is performed to form a high-concentration source region 66, and the polycrystalline silicon films 60g and 60c are also doped into high-concentration p-type.
  • a silicide process is performed, and a silicide layer 69 is formed on the source region 66 and the gate electrode 60g.
  • a capacitor is formed with the upper and side surfaces of the active region as one electrode, so that the electrode area of the capacitor is increased. It is said that the capacity can be increased.
  • the process described as DRAM is the same as the MO transistor formation process except for STI etching and capacitor storage electrode formation ion implantation, and it is easy to mix with logic circuits.
  • Non-Patent Document 1 explains that it is important for planar-type DRAM-powered system-on-chip (SoC) applications that are suitable for mixed logic circuits.
  • SoC system-on-chip
  • An example of creating the DRAM cell shown in Fig. 1C is reported.
  • Access transistor force It is formed in the form having equivalent source / drain regions 66 and 62 Other than the above, it corresponds to the configuration shown in Fig. 1A and IB. Equivalent parts are indicated by the same reference numerals.
  • the capacitance was 8 fFZ ⁇ m2, but with a sample that etched 0.15 ⁇ m deep recess into 0.35 zm deep STI, The desired capacity of 10 fFZ x m2 was obtained and the cell capacity was reported to have increased by 25%.
  • Patent Document 1 US Patent Publication No. 6,573,548
  • Non-Patent Document 1 Journal of The Electrochemical Society, 152 (1) G107-G109 (2005)
  • An object of the present invention is to provide a semiconductor device in which a logic circuit and a DRAM circuit are mixedly mounted, including a DRAM that can be manufactured without much change in a logic process and has a large capacitance per unit area. is there.
  • Another object of the present invention is to provide a highly reliable semiconductor device in which a logic circuit and a DRAM circuit are mounted, using an element isolation region by STI.
  • Another object of the present invention is to increase the capacitance of a capacitor in a form in which a capacitor is formed by digging a part of STI.
  • a semiconductor substrate having a logic region and a memory region
  • a capacitor storage electrode formed on the inner surface of the capacitor trench and extending to the upper surface of the adjacent active region
  • An access transistor having one source Z drain region formed in an active region in which the capacitor storage electrode extends, enters under the capacitor storage electrode, and forms an electrical connection;
  • a logic transistor formed in an active region of the logic region
  • the gate electrode of the access transistor and the logic transistor is formed using the same layer as the capacitor counter electrode.
  • the storage electrode formed on the recess formed in the STI can have almost the entire area of the inner surface of the recess as the electrode area. Can be formed without using a special process, ensuring high reliability.
  • FIG. 1A-1C are a plan view and a cross-sectional view showing a conventional STI-use capacitor.
  • FIGS. 2A to 2C are cross-sectional views illustrating a method of manufacturing a logic embedded memory semiconductor device having an STI-use capacitor according to an embodiment of the present invention.
  • FIGS. 2D-2E are a plan view and a cross-sectional view showing a method of manufacturing a logic-embedded memory semiconductor device having an STI-use capacitor according to an embodiment of the present invention.
  • FIGS. 2F-2H are cross-sectional views illustrating a method of manufacturing a logic embedded memory semiconductor device having an STI-use capacitor according to an embodiment of the present invention.
  • FIGS. 21-2J are cross-sectional views illustrating a method of manufacturing a logic embedded memory semiconductor device having an STI-use capacitor according to an embodiment of the present invention.
  • FIGS. 2K to 2L are cross-sectional views illustrating a method of manufacturing a logic embedded memory semiconductor device having STI-use capacitors according to an embodiment of the present invention.
  • FIGS. 2M-2N are cross-sectional views showing a method of manufacturing a logic embedded memory semiconductor device having STI-use capacitors according to an embodiment of the present invention.
  • FIGS. 2O-2P are cross-sectional views illustrating a method of manufacturing a logic-embedded memory semiconductor device having STI-use capacitors according to an embodiment of the present invention.
  • FIGS. 3A-3C are a plan view and a cross-sectional view showing a method of manufacturing an STI-use capacitor according to another embodiment of the present invention.
  • an element isolation region 12 is formed in a p-type silicon semiconductor substrate 11 by shallow trench isolation (STI).
  • STI shallow trench isolation
  • the surface of the silicon substrate is thermally oxidized to grow a buffer oxide film, and a silicon nitride film is formed thereon.
  • a resist pattern having the shape of the active region AR is formed, and the silicon nitride film and the silicon oxide film are etched.
  • the silicon substrate 11 is reactively etched to form a trench.
  • the upper end opening width of the trench is 200 nm and the trench depth is 300 nm. It is preferable to etch the trench side wall under an inclined condition.
  • a silicon nitride film liner 12 ⁇ is formed by chemical vapor deposition (CVD). Silicon oxide film (undoped silicate glass USG) 12f is deposited by high-density plasma (HDP) CVD, and the trench is backfilled. Chemical mechanical polishing (CMP) is performed using the patterned silicon nitride film as a stopper to remove the deposition curtain on the silicon nitride film and planarize the surface. The silicon nitride film is removed by etching with hot phosphoric acid, and the nona oxide film is removed by etching with dilute hydrofluoric acid.
  • CVD chemical vapor deposition
  • Si oxide film (undoped silicate glass USG) 12f is deposited by high-density plasma (HDP) CVD, and the trench is backfilled.
  • CMP Chemical mechanical polishing
  • n-well NW is formed by ion implantation using a resist mask. In the logic area, n-well and p-well are formed.
  • the surface of the active region AR is thermally oxidized to form a buffer oxide film 13.
  • This buffer oxide film protects the surface of the substrate silicon when the polycrystalline silicon film formed thereon is etched.
  • a photoresist film having a thickness of about 200 nm is applied, exposed and developed, and then subjected to STI.
  • a photoresist pattern PR1 for etching is formed. If the width of the STI is 200 nm, for example, a stripe with a width of lOOnm is left in the center, and an aperture AP is formed that opens part of the active region beyond the edge of the STI region to be etched.
  • FIG. 2D shows an example of a planar shape of the opening pattern AP.
  • the active region AR has a shape with a wide end, and the opening pattern AP is formed so as to surround the wide active region end.
  • the STI insulating film exposed in the opening pattern AP is the etching target. Etch back the STI about 200nm deep by reactive etching.
  • reactive etching for example, C4F8 / Ar / 02 is used as an etchant gas for silicon oxide, and CHF3 / Ar / 02 is used as an etchant gas for silicon nitride.
  • isolated capacitor trenches CT1 and CT2 are formed.
  • the sidewall of the capacitor trench CT consists of an exposed silicon substrate (n-type wall NW) and a STI-carrying insulating film 12c remaining at the center and bottom. It is preferable to etch the side wall of the buried insulating film 12c under the condition of tilting.
  • the region between the outer periphery of the active region AR and the outer periphery of the aperture AP is etched back to form a capacitor trench.
  • a polycrystalline silicon film 15 is deposited to a thickness of about 20 nm by CVD using SiH 4 and H 2 gas at a substrate temperature of about 600 ° C. Add p-type impurity B at the same time as deposition, or perform ion implantation of B after deposition to impart conductivity.
  • This polycrystalline silicon film 15 constitutes the storage electrode of the capacitor.
  • the bottom surface of the capacitor trench CT, which is just the active region side surface, and the STI side surface can also be used as the capacitor area. However, in this state, the polycrystalline silicon film 15 in the capacitor trench CT1 and the polycrystalline silicon film 15 in another capacitor trench CT2 are electrically continuous.
  • a photoresist covering the capacitor region is formed on the polycrystalline silicon film 15.
  • An opening is formed on the STI buried insulating film 12c remaining in the center, and also opens outside the capacitor region.
  • the polycrystalline silicon film 15 is reactively etched using the photoresist pattern PR2 as a mask.
  • Etchant gas for polycrystalline silicon having selectivity for silicon oxide film is, for example,
  • the surface of the active region not covered with the photoresist pattern PR2 is protected by the buffer oxide film 13 for etching power. After the etching of the polycrystalline silicon film 15, the photoresist mask PR2 is removed, and the buffer oxide film 13 is removed with, for example, dilute hydrofluoric acid.
  • FIG. 2H shows a state where the buffer oxide film 13 is also removed and a clean silicon surface is exposed.
  • the polycrystalline silicon films 15x and 15y formed in the capacitor trench CT cover both sides and the bottom of the trench and are separated from each other. In the logic circuit region, the surface of the active region defined by STI is exposed.
  • dry thermal oxidation is performed in, for example, 900 ° C. dry 02 to consume about 4 / m of the silicon surface and grow a thermal oxide film 16.
  • the active area of the logic circuit area is also shown on the left side of the figure.
  • a gate oxide film 16g is formed on the surface of the active region, and the exposed surface of the polycrystalline silicon film 15 is also thermally oxidized to form a silicon oxide film 16c constituting a capacitor dielectric film.
  • a polycrystalline silicon film 17 is deposited on the silicon oxide film 16 to a thickness of about 120 nm by CVD using SiH 4 and H 2 gas at a substrate temperature of about 600 ° C. This polycrystalline silicon film forms the gate electrode of the transistor and the counter electrode of the capacitor.
  • a photoresist pattern PR3 for the gate electrode of the transistor and the counter electrode of the capacitor is formed on the polycrystalline silicon film 17.
  • the width (gate length) of the gate electrode is 50 nm, for example.
  • the polycrystalline silicon film 17 is reactively etched using the photoresist pattern PR3 as a mask.
  • C12 / HBr / ⁇ 2 is used as the etching gas.
  • the etching is performed so as to stop at the gate oxide film 16g.
  • both sides of the gate electrode 17g (and the counter electrode 17c) of the polycrystalline silicon film The extension region 21 is formed by ion-implanting a low concentration of p-type impurity B into the n-type wall NW at an acceleration energy of 3 keV and a dose of 5 X 1014 cm_2 (hereinafter expressed as 5E14).
  • the gate electrode 17g and the counter electrode 17c are also doped with p-type impurities.
  • a silicon oxide film is deposited on the semiconductor substrate to a thickness of about 10 nm CV D, and etched back by reactive etching to form the gate electrode 17g and the capacitor C on the sidewalls. Form side wall spacer SW.
  • p-type impurity B is ion-implanted at an acceleration energy of 10 keV and a dose of 3E15 to form a high concentration source / drain region 22.
  • the gate electrode 17g and the counter electrode 17c are also heavily doped with p-type impurities.
  • a silicon oxide film 23 is formed on the substrate by CVD with a thickness of about 20 nm. This oxide film serves as a mask for the silicide process.
  • a photoresist pattern PR4 having a shape covering the region for preventing the silicidation reaction is formed. Photoresist pattern PR4 covers the access transistor. Reactive etching of the silicon oxide film 23 is performed using C4F8 / Ar / ⁇ 2 as an etching gas and the photoresist pattern PR4 as a mask.
  • the silicon oxide film is removed from the counter electrode in the logic transistor region and the memory region. Thereafter, the photoresist pattern PR4 is removed.
  • Logic transistor source Z drain region, gate electrode and capacitor counter electrode form a silicide layer to reduce resistance. Capacitor storage region can degrade retention characteristics due to silicide reaction. This is because it is preferable not to form silicide.
  • the sidewall spacers SW on both sides of the counter electrode 17g of the capacitor are covered with a mask and are not etched, so that they remain protruding from the counter electrode 17g of polycrystalline silicon.
  • a Co film on the substrate surface by sputtering and performing a primary silicidation reaction at a low temperature, wash out the unreacted Co film with sulfuric acid / hydrogen peroxide solution and perform a secondary silicide reaction at 850 ° C.
  • a low resistance silicide film is formed.
  • a CoSi layer 26 having a thickness of 50 nm is formed on the source Z drain region of the logic transistor, the gate electrode, and the counter electrode of the capacitor.
  • the figure also shows the n-channel transistor in the p-well PW in the logic circuit area at the left end.
  • the conductivity type of the channel (well), the gate electrode 16g, the extension 23, and the source Z drain region 24 is opposite to that of the corresponding part of the p-channel transistor.
  • ions are separated by a photoresist mask and implanted in a separate process.
  • a DRAM cell is formed simultaneously with the formation of the logic transistor.
  • the steps added to form the DRAM cell include buffer oxide film formation in FIG. 2B, STI partial etching in FIGS. 2C and 2E, polycrystalline silicon deposition in FIG. 2F, and polycrystalline silicon films in FIGS. 2G and 2H ( And buffer oxide film). These processes use similar processes in the production of logic transistors and can be performed with high reliability. Since the capacitor is formed using almost all the inner surface of the recess formed in STI, the area of the capacitor can be increased.
  • a silicon oxide film is used as the gate insulating film and the capacitor dielectric film has been described
  • a silicon oxynitride film, a silicon nitride film, a high dielectric constant insulating film, a high dielectric constant insulating film into which nitrogen is introduced A stacked layer of a silicon oxide film or the like can also be used.
  • the source region of the two access transistors can be shared, and memory capacitors can be formed on both sides.
  • Various known MOS transistor configurations can be used.
  • partial etching of STI was performed using an etching mask having an opening including a part of the active region from STI.
  • the capacitor's storage electrode is also in contact with the side of the active region and forms a pn junction capacitance.
  • the impurity concentration in the active region is low and the pn junction capacitance is small. A pn junction can cause leakage.
  • FIGS. 3A and 3B show another embodiment in which a recess is formed only in the internal space of the STI to form a capacitor.
  • FIG. 3A is a plan view showing an active region AR and an opening AP of an STI etching mask
  • FIG. 3B is a cross-sectional view showing a state in which a storage electrode is formed after partial etching of STI corresponding to FIG. 2H.
  • the shape of the active region AR is a simple rectangle.
  • the mask opening AR is separated for each capacitor on the STI, and it is necessary to increase the area of the recess side surface.
  • a lattice shape may be used.
  • the active area AR is separated from the outer periphery of the aperture AP.
  • FIG. 3B is a cross-sectional view of one capacitor.
  • a recess on the loop is formed in the STI region, and a polycrystalline silicon film 15x is formed on the inner surface.
  • the polycrystalline silicon film 15x between the recesses shows a removed form, but may be continuously removed as long as it is in a single capacitor. As shown in Figure 2G, the capacitors need to be separated.
  • the polycrystalline silicon film 15 extends from the recess to the adjacent active region. It is preferable that the extension 21 enters the lower portion of the polycrystalline silicon film 15x and reaches the STI.
  • Polycrystalline silicon film 15x is not in direct contact with n-well NW. This is advantageous when the polycrystalline silicon film 15 is doped at a high concentration.
  • the STI etching can be performed by etching only silicon oxide.
  • the silicon nitride film liner 12 ⁇ shown in FIG. 2A can also be used as an etch stopper. It may be possible to prevent the mobility from being lowered by the tensile stress of the silicon nitride film.
  • the planar shape of the recess constituting the capacitor can be variously selected.
  • FIG. 3C is a modification of the planar shape of the recess.
  • Recess R1 and Recess R2 are interdigitated. Although a shape with two comb teeth is shown, the number of comb teeth can be changed arbitrarily.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)

Abstract

Dispositif semi-conducteur à mémoire intégrée logique comprenant une STI définissant une pluralité de régions actives dans un substrat semi-conducteur, un évidement constitué en enlevant une partie de la profondeur de la STI dans une zone mémoire, une électrode de stockage de condensateur constituée sur la surface interne de l’évidement et s'étendant le long de la surface supérieure d’une région active adjacente, un film diélectrique à condensateur formé sur l’électrode de stockage de condensateur, une électrode opposée à condensateur formé sur le film diélectrique à condensateur, un transistor d’accès formé dans la région active le long de laquelle s’étend l’électrode de stockage de condensateur, et ayant une source et un drain dont l’un s’étend sous l’électrode de stockage de condensateur pour constituer une connexion électrique, et un transistor logique formé dans une zone logique. L'électrode opposée, l’électrode diélectrique à condensateur, et l’électrode de stockage de condensateur constituent un condensateur à mémoire, et les électrodes de grille du transistor d’accès et du transistor logique sont formées en utilisant la même couche que l’électrode opposée à condensateur.
PCT/JP2005/016943 2005-09-14 2005-09-14 Dispositif semi-conducteur et procédé de fabrication idoine Ceased WO2007032067A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011503841A (ja) * 2007-11-02 2011-01-27 アイピーディーアイエイ 多層構造及びその製造方法
CN112635467A (zh) * 2020-12-18 2021-04-09 上海微阱电子科技有限公司 存储单元结构及形成方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH022672A (ja) * 1988-06-17 1990-01-08 Nec Corp 半導体メモリセルとその製造方法
JP2004527901A (ja) * 2001-01-29 2004-09-09 モノリシック・システム・テクノロジー・インコーポレイテッド キャビティ内に部分的に製造されたコンデンサ構造を備えたｄｒａｍセル及びその作動方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH022672A (ja) * 1988-06-17 1990-01-08 Nec Corp 半導体メモリセルとその製造方法
JP2004527901A (ja) * 2001-01-29 2004-09-09 モノリシック・システム・テクノロジー・インコーポレイテッド キャビティ内に部分的に製造されたコンデンサ構造を備えたｄｒａｍセル及びその作動方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011503841A (ja) * 2007-11-02 2011-01-27 アイピーディーアイエイ 多層構造及びその製造方法
CN112635467A (zh) * 2020-12-18 2021-04-09 上海微阱电子科技有限公司 存储单元结构及形成方法

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