[go: up one dir, main page]

WO2006000189A1 - Ensemble de couches, transistor a effet de champ et procede de fabrication d'un ensemble de couches - Google Patents

Ensemble de couches, transistor a effet de champ et procede de fabrication d'un ensemble de couches Download PDF

Info

Publication number
WO2006000189A1
WO2006000189A1 PCT/DE2005/001095 DE2005001095W WO2006000189A1 WO 2006000189 A1 WO2006000189 A1 WO 2006000189A1 DE 2005001095 W DE2005001095 W DE 2005001095W WO 2006000189 A1 WO2006000189 A1 WO 2006000189A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
carbon
trench
semiconductor layer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2005/001095
Other languages
German (de)
English (en)
Inventor
Lars Dreeskornfeld
Jessica Hartwich
Rainer Schröter
Gernot Steinlesberger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of WO2006000189A1 publication Critical patent/WO2006000189A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/018—Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
    • H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations

Definitions

  • the invention relates to a layer arrangement, a field effect transistor and a method for producing a layer arrangement.
  • FD-SOI fully-depleted silicon-on-insulator
  • a fully-depleted silicon-on-insulator device can meet the requirements of the International Technology Roadmap for Semiconductors (ITRS). Due to the extreme scaling of the channel thickness (in particular in the range of 10 nm and less) corresponding to the gate length (for example ratio 1: 4), in particular a required low off-current of an FD-SOI transistor can be achieved.
  • ITRS International Technology Roadmap for Semiconductors
  • an SOI substrate which comprises a silicon substrate, a silicon oxide layer formed on the silicon substrate and a thin top layer formed on the silicon oxide layer is used as the starting wafer. Has silicon layer.
  • SOI MOSFETs are field-effect transistors which are processed on or in the thin monocrystalline silicon layer (top silicon layer) of an SOI substrate. Particularly interesting for future CMOS technologies are SOI MOSFETs in which the layer thickness of the silicon film is smaller than the depth of the depletion zone, which differs from the silicon Silicon oxide interface hineinerstreckt into the silicon layer. If the silicon layer is completely depleted of charge carriers, such SOI MOSFETs are referred to as fully depleted (FD).
  • FD fully depleted
  • the SIMOX Separatation by Implantation of Oxygen
  • the SIMOX method is based on an ion implantation of oxygen into lightly doped n-type or p-type silicon wafers, whereby a buried electrically insulating layer of silicon oxide is produced below the wafer surface.
  • An alternative method for forming an SOI substrate is the so-called ELTRAN method, with which a low-defect, thin, monocrystalline silicon layer can be arranged on a buried silicon oxide layer.
  • the ELTRAN method is described in [1].
  • One of the challenges in fabricating a planar SOI-MOS transistor is reducing the parasitic resistances at the source and drain regions.
  • a partial circumvention of the problem is often achieved by epitaxially growing silicon material on top of a thin channel layer so that sufficient material is available for silicidation and subsequent via processes.
  • Another challenge in fabricating SOI-MOS devices is the often required introduction of novel materials such as metal gate materials, high-k gate dielectrics, silicon germanium alloys, etc., for better performance and scalability Device to reach.
  • novel materials such as metal gate materials, high-k gate dielectrics, silicon germanium alloys, etc.
  • problems with the FD-SOI technology are to form a channel region of very small thickness, to contact the source / drain regions with sufficiently low terminal resistance, and to use a charge-depleted transistor by selecting the gate material (and not to adjust as in conventional transistors by adjusting the channel doping).
  • [2] discloses a method for processing a dummy depleted SOI transistor based on forming a recess in a channel region ("recessed channel"). Technology). After a channel region has been formed as a thinned region of a silicon layer, a gate region made of polycrystalline silicon is formed above it.
  • [2] discloses a method of manufacturing an SOI field effect transistor in which a hard mask is formed on a patterned silicon layer of an SOI substrate. Subsequently, a window is formed in the hard mask to expose the silicon layer in a window area. The silicon layer is removed in the window area. Thereafter, a gate insulating layer is formed in the window, and a gate electrode is formed thereon. The unetched portions of the silicon layer are used as the source / drain regions, and the re-etched portion of the silicon layer is used as the channel region. A gate region of polycrystalline silicon material is formed.
  • [3] discloses that the work function of carbon material is about 4.85eV.
  • thermally conductive structures of diamond or diamond-like material, wherein formed to form the thermally conductive structures in a silicon layer trenches and then filled with diamond or Diamant ⁇ similar material.
  • the invention is based in particular on the problem of providing a layer arrangement which is improved compared to [2] and which can be used in particular as a field-effect transistor.
  • the problem is solved by a layer arrangement, by a field effect transistor and by a method for producing a layer arrangement having the features according to the independent patent claims.
  • the layer arrangement according to the invention comprises a substrate, a semiconductor layer on the substrate, a trench in the semiconductor layer, electrically insulating material on the sidewalls and at the bottom of the trench and carbon-containing material on the electrically insulating material in the trench.
  • a field effect transistor is provided with a layer arrangement having the features described above.
  • a method of fabricating a layered structure in which a semiconductor layer is provided on a substrate, a trench is formed in the semiconductor layer, electrically insulating material is formed on the sidewalls and bottom of the trench, and carbon material is formed on the electrically insulating material in the trench.
  • a basic idea of the invention is to provide a field effect transistor einrichtbare layer arrangement in which a thinned portion of a semiconductor layer is provided as a channel region in "recessed channel” technology with an extremely small thickness and a due of the thinned semiconductor layer region-generated trench is filled with carbon-containing material as the gate region.
  • the use of carbon material as a gate region is very advantageous for a FD-SOI field effect transistor.
  • the transistor characteristics can be adjusted by selecting the gate material rather than by channel doping, as is conventional.
  • Carbon material is a so-called "midgap material", ie the threshold voltage of a field effect transistor based on the layer arrangement according to the invention is due to the implementation of a carbon gate region for both an n-MOS field effect transistor and a p-MOS Field effect transistor possible.
  • the layer arrangement according to the invention is outstandingly suitable for CMOS applications.
  • the midgap material property of carbon is due to the fact that the work function for carbon is in the range of about 5eV (according to [3] at about 4.85 eV), ie closer to silicon midgap than to n + doped or p + doped polysilicon.
  • Carbon as the trench-filling material of the layer arrangement is well compatible with other process materials that can be used for the layer arrangement, in particular in the context of silicon microtechnology (eg, silicon, silicon oxide, silicon nitride), and thus can also be incorporated into existing processes with reasonable effort ,
  • carbon material has a good deposition property on electrically insulating material on the inner wall of the trench, which preferably contains silicon oxide as electrically insulating material and can serve as a field-effect transistor as a gate-insulating layer in one embodiment of the layer arrangement.
  • carbon material is typical Process conditions (temperature, chemical environment) of the silicon micro-technology in particular for the manufacture of field effect transistors compatible. This compatibility includes the property of good temperature resistance and the ability to easily etch back a carbon layer by dry etching (eg, H 2 , O 2 , air or plasma etching).
  • An important aspect of the invention may be seen as combining recessed channel processing to form the layer assembly with the use of carbon, particularly polycrystalline carbon, as a novel trench filling material.
  • carbon particularly polycrystalline carbon
  • the carbon material can advantageously be used both for p-MOS devices and for n-MOS devices.
  • the layer arrangement according to the invention serves according to a preferred embodiment as a fully depleted field effect transistor with very good performance.
  • SOI technology an FD-SOI transistor with ultrathin channel region and carbon as gate material is provided according to the invention.
  • An electrically insulating layer may be provided between the substrate and the semiconductor layer of the layer arrangement.
  • the substrate, the electrically insulating layer and the semiconductor layer may be formed as a silicon on insulator substrate (SOI substrate).
  • SOI substrate silicon on insulator substrate
  • the substrate forms a bulk silicon wafer
  • the electrically insulating layer forms a buried silicon oxide layer
  • the semiconductor layer forms a top silicon layer of a very small thickness.
  • processing can already be started with a very thin top silicon layer as the semiconductor layer, so that an extremely thin channel region can be formed by thinning a central section of the semiconductor layer.
  • the semiconductor layer (in particular the thinned central region of the semiconductor layer, which can be used as channel region) of the layer arrangement can be partially depleted on charge carriers, and is preferably fully depleted on charge carriers.
  • the semiconductor layer may have a thickness of at most 30 nm, preferably at most 10 nm, in the region of the trench exhibit.
  • the thinned portion of the semiconductor layer may have a thickness of at most 30 nm, preferably at most 10nr ⁇ .
  • a particularly good adjustability of the electrical conductivity of the channel region can be achieved by applying an electrical signal to the gate region using the field effect.
  • the carbon-containing material may be carbon. According to this embodiment, the carbon-containing material is formed solely of carbon and does not have other components at most or at most in trace amounts (i.e., in insignificant amounts).
  • the carbon-containing material may include or consist of polycrystalline carbon.
  • Polycrystalline carbon is ideal as a midgap material for p-MOS devices and n-MOS devices.
  • the resistivity for undoped materials is for graphite at a few m ⁇ cm, ie about 5 m ⁇ cm, for diamond it is much greater than 1 m ⁇ cm, ie, in the range of 100 m ⁇ cm to 1000 m ⁇ cm, and for the invention preferred material of polycrystalline carbon at about 1 m ⁇ cm (undoped carbon of order of magnitude doped silicon).
  • the inventively preferred material made of carbon has orders of magnitude lower resistivity than diamond.
  • the specific resistance for doped materials for graphite is a few ⁇ cm, ie about 5 ⁇ cm, for highly doped diamond (10 20 to 10 21 per cm 3 ) at some 1 m ⁇ cm, ie in the range of 5 m ⁇ cm and for the preferred material according to the invention of polycrystalline carbon at about 10 ⁇ cm to 1 ⁇ cm, preferably at about 1 ⁇ cm.
  • the carbon material preferred according to the invention also has a specific order of magnitude lower resistivity than diamond in the doped state.
  • the carbon material preferred according to the invention it is even possible for the carbon material preferred according to the invention to have a lower specific resistance than silver, which has a specific resistance of 1.6 ⁇ cm.
  • the roughness of Higly Oriented Pyrolitic Graphite is less than 1 nm, that of diamond is highly dependent on the microstructure, i. grain size and orientation, stress, impurities and dislocations within the diamond.
  • the roughness is between 1 nm and 3 nm, in particular about 2 nm + 0.3 nm.
  • the roughness of the material of carbon preferred according to the invention lies between HOPG and diamond.
  • the grain size of HOPG is about 10 microns and in polycrystalline CVD diamond, ie diamond, which is produced by chemical vapor deposition, at some to, ie about 5 microns.
  • the grain size of the invention preferred Polycrystalline carbon material is between 0.5 nm and 3 ⁇ m, in particular 1 ⁇ m to 2 mm.
  • the hardness of graphite is about 0.2 GPa and that for diamond is 10 GPa to several 100 GPa, i. up to about 500 GPa.
  • the hardness of the inventively preferred material of polycrystalline carbon is between 2 GPa and 9 GPa, in particular about 6 GPa to 7 GPa.
  • the elasticity of graphite is about 8 GPa and for diamond about 400 GPa to 500 GPa.
  • the elasticity of the inventively preferred material of polycrystalline carbon is between 50 GPa and 150 GPa, in particular about 80 GPa and thus lies between the elasticity of graphite and diamond.
  • the layer arrangement can be set up as a field-effect transistor.
  • the (thinned) portion of the semiconductor layer below the trench may be configured as a channel region
  • regions of the semiconductor layer adjacent to the trench may be the first source / drain region and the second source / drain region be arranged (ie, a first unthinned portion of the semiconductor layer may be configured as a first source / drain region and a second unthinned portion of the semiconductor layer may be configured as a second source / drain region)
  • at least a part of electrically insulating material may be configured as a gate insulating layer and the carbon-containing material may be configured as a gate region.
  • the layer arrangement can optionally as p-MOS field effect transistor or used as an n-MOS field effect transistor.
  • a CMOS arrangement is formed, with a first layer arrangement according to the invention, which is set up as a p-MOS field-effect transistor, and with a second layer arrangement according to the invention, which is set up as an n-MOS field-effect transistor.
  • These two layer arrangements can be integrated in a common substrate. Since carbon material is a midgap material, the carbon material may be provided as a gate region both in a p-MOS field effect transistor and in an n-MOS field effect transistor, so that a high-performance CMOS device is formed with little effort is.
  • a gas flow of a carbonaceous gas such as methane (CH 4 ) can be adjusted, whereby the pressure is set to, for example, 600 hectopascals.
  • the thickness of the deposited carbon layer can be adjusted over the processing time.
  • a polycrystalline carbon layer is understood in particular to mean a layer which consists essentially of carbon and which in partial regions has a graphite structure, i. a hexagonal lattice structure which can be considered crystalline.
  • the individual "crystalline" subregions with hexagonal structures are separated by regions which have no hexagonal lattice structures, or at least separated by hexagonal lattice structures which have a different orientation to the adjacent "crystalline" subregions.
  • a hydrogen atmosphere is generated at a pressure of 1 hectopascal.
  • a carbon-containing gas for example, methane (CH 4 ) or acetylene (C 2 H 4 )
  • CH 4 methane
  • C 2 H 4 acetylene
  • a polycrystalline carbon layer separates out.
  • the carbonaceous gas is constantly introduced during the deposition process, so that the total pressure remains substantially constant.
  • a hydrogen atmosphere of about 2 Torr to 3 Torr, preferably 2.5 Torr, which is about 3.3 hectopascals corresponds, generated.
  • a so-called photon furnace is used, ie a light source which additionally provides energy.
  • a carbon-containing gas for example methane (CH 4 ), acetylene (C 2 H 4 ) or alcohol vapor, preferably ethanol vapor (C 2 H 5 OH), is then in turn introduced into the hydrogen atmosphere until a total pressure between 6.5 Torr and 8, 5 Torr, preferably 7.5 Torr, which corresponds to about 10 hectopascals, is reached. Even under these conditions, a polycrystalline carbon layer separates out. Also in this process, the carbonaceous gas is preferably continuously introduced while the conformal deposition is performed.
  • the carbon-containing material can be formed by supplying a carbon-containing gas in a hydrogen atmosphere having a total pressure of between 1 hectopascal and 4 hectopascal and at a temperature between 600 ° C and 1000 ° C.
  • the carbonaceous gas may be methane, ethane, acetylene or alcohol vapor.
  • the temperature can be set between 900 ° Celsius and 970 ° Celsius, the total pressure of the hydrogen atmosphere can be 1 hectopascal, and in forming the carbonaceous layer enough carbonaceous gas can be supplied to set a total pressure between 500 hectopascals and 700 hectopascals , Alternatively, the temperature may be set between 750 ° C and 850 ° C, the total hydrogen atmosphere pressure may be 1.5 Hectopascals, and carbon-forming layer may be carbonated enough to produce a total pressure of between 9 and Hectopascals 11 hectopascal sets.
  • the temperature may be maintained at least in part by means of photon heating and / or by using a plasma.
  • the trench may be formed in the semiconductor layer by removing material of the semiconductor layer, i. by thinning the semiconductor layer (for example, in a central portion of the semiconductor layer).
  • FIGS. 1 to 12 layer sequences at different times during a method for producing a field-effect transistor according to a preferred exemplary embodiment of the invention
  • FIG. 13 according to the method according to FIGS. 1 to 12. produced field effect transistor according to a preferred embodiment of the invention.
  • the silicon-on-insulator substrate 100 shown in FIG. 1 contains a bulk silicon substrate 101, a buried oxide 102 (BOX) formed thereon, and a thin top layer formed on the silicon oxide layer 102.
  • an active region (“mesen") is defined using a lithography process and an etching process based on the top silicon layer 103.
  • first sidewall spacers 301 are formed on the sidewalls of the laterally limited silicon layer 201.
  • the first sidewall spacers 301 may be formed of silicon oxide material or silicon nitride material. This ensures a lateral isolation of the mesen.
  • a silicon nitride hard mask 401 is deposited on the layer sequence 300.
  • photoresist material (lacquer) is first deposited on the layer sequence 400 and patterned using a lithography process and an etching process in such a way that photoresist material is removed in a central section , whereby a window 502 is formed and a Surface area of the silicon nitride hardmask 401 is exposed.
  • the silicon nitride hard mask 401 is etched into the exposed area using a dry etching method, thereby forming a patterned silicon nitride hard mask 401 and exposing a surface area of the laterally confined silicon layer 201 becomes. Subsequently, for example, by means of a stripping method, the photoresist 501 is removed from the surface of the layer sequence thus obtained.
  • the laterally limited silicon layer 201 is thinned using a dry etching method.
  • a thinned silicon region 703 is formed in a central section of the laterally delimited silicon layer 201, to which a first, unthinned silicon region 701 adjoins on the left side according to FIG. 7 and a second, unthinned silicon region 702 on the right side according to FIG Due to the removal of silicon material during thinning of the laterally confined silicon layer 201, a trench 704 remains in a central portion of the laterally confined silicon layer 201.
  • a protective silicon oxide layer 801 is initially formed (for example by means of thermal oxidation or using a deposition method) in a horizontal bottom region of the trench 704 according to FIG.
  • second sidewall spacers 802 of silicon nitride material are formed on vertical walls of the trench 704, as shown in FIG.
  • the layer sequence 800 is subjected to a wet etching process for smoothing, whereby the protective silicon oxide layer 801 is removed.
  • a gate insulating layer 1001 of silicon oxide material is formed on the exposed portion of the laterally-patterned silicon layer 201, i. formed predominantly on the thinned silicon region 703 in the trench 704.
  • polycrystalline carbon material 1101 is deposited over the entire surface of the layer sequence 1000, whereby the trench 704 is completely filled with carbon material and also other regions of the layer sequence are covered with carbon material.
  • a gas flow of the carbon-containing gas methane (CH 4 ) is then set at a temperature of 950 ° Celsius and a pressure of 1 hectopascal in H2 atmosphere, whereby the pressure is set to 600 hectopascal, for example.
  • the deposited polycrystalline carbon material 1101 is etched back so that carbon material remains only in the trench 704, thus forming a carbon gate region 1201 of polycrystalline carbon material.
  • the silicon nitride hardmask 401 is removed using an etching process.
  • the field effect transistor 1300 In the field effect transistor 1300, the first un-thinned silicon region 701 is established as the first source / drain region 1301, the second undiluted silicon region 702 is established as the second source / drain region 1302, and the thinned silicon region 703 is ultra-thin channel region 1303 formed.
  • the field effect transistor 1300 of Fig. 13 is an FD-SOI MOSFET having excellent transistor characteristics.
  • silicon-on-insulator substrate 101 semiconductor silicon substrate 102 silicon oxide layer 103 top silicon layer 200 layer sequence 201 laterally delimited silicon layer 300 layer sequence 301 first sidewall spacer 400 layer sequence 401 silicon nitride hard mask 500 layer sequence 501 photoresist 502 window 600 Layer sequence 601 window 700 layer sequence 701 first undiluted silicon region 702 second undiluted silicon region 703 thinned silicon region 704 trench 800 layer sequence 801 protective silicon oxide layer 802 second sidewall spacer 900 layer sequence 1000 layer sequence 1001 gate-insulating layer 1100 layer sequence 1101 polycrystalline carbon Material 1200 layer sequence 1201 carbon gate region 1300 field effect transistor 1301 first source / drain region 1302 second source / drain region 1303 ultra-thin channel area

Landscapes

  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un ensemble de couches comprenant un substrat, une couche semiconductrice placée sur ce substrat, une tranchée formée dans la couche semiconductrice, un matériau électriquement isolant placé contre les parois latérales et au fond de la tranchée ainsi qu'un matériau carboné placé sur le matériau électriquement isolant dans la tranchée.
PCT/DE2005/001095 2004-06-24 2005-06-20 Ensemble de couches, transistor a effet de champ et procede de fabrication d'un ensemble de couches Ceased WO2006000189A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004030552.8 2004-06-24
DE102004030552A DE102004030552B4 (de) 2004-06-24 2004-06-24 Schicht-Anordnung, Feldeffekttransistor und Verfahren zum Herstellen einer Schicht-Anordnung

Publications (1)

Publication Number Publication Date
WO2006000189A1 true WO2006000189A1 (fr) 2006-01-05

Family

ID=35058200

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2005/001095 Ceased WO2006000189A1 (fr) 2004-06-24 2005-06-20 Ensemble de couches, transistor a effet de champ et procede de fabrication d'un ensemble de couches

Country Status (2)

Country Link
DE (1) DE102004030552B4 (fr)
WO (1) WO2006000189A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7978504B2 (en) * 2008-06-03 2011-07-12 Infineon Technologies Ag Floating gate device with graphite floating gate

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04142079A (ja) * 1990-10-02 1992-05-15 Nippon Telegr & Teleph Corp <Ntt> 半導体装置およびその製造方法
JP2001352058A (ja) * 2000-06-09 2001-12-21 Toshiba Corp 半導体装置の製造方法
US20020142551A1 (en) * 2001-03-29 2002-10-03 International Business Machines Corporation CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture
US20030189231A1 (en) * 1999-07-28 2003-10-09 Clevenger Lawrence A. Method and structure for providing improved thermal conduction for silicon semiconductor devices
DE10233663A1 (de) * 2002-07-24 2004-02-19 Infineon Technologies Ag Methode zur Prozessierung eines Fully-Depleted SOI Transistors
WO2005062752A2 (fr) * 2003-11-28 2005-07-14 International Business Machines Corporation Structure de grille de carbure metallique et procede de fabrication

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04142079A (ja) * 1990-10-02 1992-05-15 Nippon Telegr & Teleph Corp <Ntt> 半導体装置およびその製造方法
US20030189231A1 (en) * 1999-07-28 2003-10-09 Clevenger Lawrence A. Method and structure for providing improved thermal conduction for silicon semiconductor devices
JP2001352058A (ja) * 2000-06-09 2001-12-21 Toshiba Corp 半導体装置の製造方法
US20020142551A1 (en) * 2001-03-29 2002-10-03 International Business Machines Corporation CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture
DE10233663A1 (de) * 2002-07-24 2004-02-19 Infineon Technologies Ag Methode zur Prozessierung eines Fully-Depleted SOI Transistors
WO2005062752A2 (fr) * 2003-11-28 2005-07-14 International Business Machines Corporation Structure de grille de carbure metallique et procede de fabrication

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
BUCHANAN D A ET AL: "Fabrication of midgap metal gates compatible with ultrathin dielectrics", APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, US, vol. 73, no. 12, 21 September 1998 (1998-09-21), pages 1676 - 1678, XP012020986, ISSN: 0003-6951 *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 417 (E - 1258) 3 September 1992 (1992-09-03) *
PATENT ABSTRACTS OF JAPAN vol. 2002, no. 04 4 August 2002 (2002-08-04) *
RAGHAVAN G ET AL: "POLYCRYSTALLINE CARBON: A NOVEL MATERIAL FOR GATE ELECTRODES IN MOSTECHNOLOGY", JAPANESE JOURNAL OF APPLIED PHYSICS, PUBLICATION OFFICE JAPANESE JOURNAL OF APPLIED PHYSICS. TOKYO, JP, vol. 32, no. 1B, PART 1, January 1993 (1993-01-01), pages 380 - 383, XP000418034, ISSN: 0021-4922 *

Also Published As

Publication number Publication date
DE102004030552A1 (de) 2006-02-02
DE102004030552B4 (de) 2008-12-24

Similar Documents

Publication Publication Date Title
DE112011106092B3 (de) Halbleiter, der durch elastische Kantenrelaxation eines Stressors in Kombination mit einer vergrabenen Isolierschicht verspannt wird
DE102009055392B4 (de) Halbleiterbauelement und Verfahren zur Herstellung des Halbleiterbauelements
DE112012001742B4 (de) Halbleiterstruktur mit einem graphennanoband und verfahren zu dessen herstellung
TWI306632B (en) Methods for forming a semiconductor device
DE112012000689B4 (de) Halbleiterstruktur mit Gate-Dielektrikum aus Nitrid und Verfahren zum Bilden der Halbleiterstruktur
DE112006001705B4 (de) Verfahren zur Herstellung eines Integrierten Komplementär-Metalloxid-Halbleiter-Schaltkreises unter Verwendung eines erhöhten Source-Drains und eines Ersatz-Metall-Gates
DE102005052054B4 (de) Halbleiterbauteil mit Transistoren mit verformten Kanalgebieten und Verfahren zu seiner Herstellung
DE112011101378B4 (de) Epitaxie von Delta-Monoschicht-Dotierstoffen für eingebettetes Source/Drain-Silicid
DE102012206478B4 (de) Extrem-dünner-Halbleiter-auf-Isolator(ETSOI)-FET mit einem Rück-Gate und verringerter Parasitärkapazität sowie Verfahren zu dessen Herstellung
DE112012004932B4 (de) Verfahren zur Herstellung eines SOI-FinFET mit vertieften verschmolzenen Rippen und Schicht zur verbesserten Spannungskopplung
KR102637107B1 (ko) 전자 소자 및 그 제조방법
DE112011105925B4 (de) Mikroelektronischer Transistor und Verfahren zum Herstellen desselben
DE112007003116B4 (de) Verfahren zur Herstellung eines verspannten Transistors und Transistor
DE102009055435B4 (de) Verstärkter Einschluss von Metallgateelektrodenstrukturen mit großem ε durch Verringern der Materialerosion einer dielektrischen Deckschicht beim Erzeugen einer verformungsinduzierenden Halbleiterlegierung
DE102012222116B4 (de) Halbleiterstruktur mit Doppelschicht-Gate-Dielektrikum mit geringer äquivalenter Oxiddicke, Graphen-Halbleiterbauelemente und ein Verfahren
TW201034084A (en) Optimized compressive SiGe channel PMOS transistor with engineered Ge profile and optimized silicon cap layer
TW200929541A (en) Transistor and method of fabricating the same
CN1897232A (zh) 三栅极器件及其加工方法
DE102008010110B4 (de) Verfahren zum Herstellen eines Halbleiterelements mit vergrabener Oxidschicht und einer Feldeffekttransistor-Anordnung mit vergrabener Oxidschicht
WO2008054967A2 (fr) Procédé de mise en place d&#39;un transistor à haute mobilité électronique (hemt) de dimension nanométrique sur un isolant
US7033869B1 (en) Strained silicon semiconductor on insulator MOSFET
DE102009023237B4 (de) Verfahren zum Herstellen von Transistorelementen mit unterschiedlicher Verformung und Halbleiterbauelement
DE102011004320A1 (de) Komplementäre Transistoren mit Metallgateelektrodenstrukturen mit großem ε und epitaktisch hergestellten Halbleitermaterialien in den Drain- und Sourcebereichen
CN104425599A (zh) 鳍式场效应晶体管及其形成方法
DE102008044983B4 (de) Verfahren zum Herstellen eines strukturierten verformten Substrats, insbesondere zur Herstellung verformter Transistoren mit geringerer Dicke der aktiven Schicht

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase