WO2006000189A1 - Layer assembly, field effect transistor, and method for producing a layer assembly - Google Patents

Abstract

The invention relates to a layer assembly which comprises a substrate, a semiconductor layer on said substrate, a trench in the semiconductor layer, electrically insulating material on the side walls and on the base of the trench and carbon-containing material on the electrically insulating material in the trench.

Description

Besehreibung

Layer arrangement, field effect transistor and method for producing a layer arrangement

The invention relates to a layer arrangement, a field effect transistor and a method for producing a layer arrangement.

So-called fully-depleted silicon-on-insulator (FD-SOI) devices with. ultrathin channel regions are considered a promising alternative for conventional bulk substrate transistors in future CMOS generations. A fully-depleted silicon-on-insulator device can meet the requirements of the International Technology Roadmap for Semiconductors (ITRS). Due to the extreme scaling of the channel thickness (in particular in the range of 10 nm and less) corresponding to the gate length (for example ratio 1: 4), in particular a required low off-current of an FD-SOI transistor can be achieved.

In SOI technology ("silicon-on-insulator"), an SOI substrate which comprises a silicon substrate, a silicon oxide layer formed on the silicon substrate and a thin top layer formed on the silicon oxide layer is used as the starting wafer. Has silicon layer.

SOI MOSFETs are field-effect transistors which are processed on or in the thin monocrystalline silicon layer (top silicon layer) of an SOI substrate. Particularly interesting for future CMOS technologies are SOI MOSFETs in which the layer thickness of the silicon film is smaller than the depth of the depletion zone, which differs from the silicon Silicon oxide interface hineinerstreckt into the silicon layer. If the silicon layer is completely depleted of charge carriers, such SOI MOSFETs are referred to as fully depleted (FD).

By scaling down the layer thickness of the monocrystalline silicon layer of the SOI substrate, which corresponds to the body or channel thickness of the transistor in known SOI MOSFETs, disturbing short channel effects can be effectively suppressed.

For example, to form an SOI substrate, the SIMOX (Separation by Implantation of Oxygen) method is used. The SIMOX method is based on an ion implantation of oxygen into lightly doped n-type or p-type silicon wafers, whereby a buried electrically insulating layer of silicon oxide is produced below the wafer surface.

An alternative method for forming an SOI substrate is the so-called ELTRAN method, with which a low-defect, thin, monocrystalline silicon layer can be arranged on a buried silicon oxide layer. The ELTRAN method is described in [1].

One of the challenges in fabricating a planar SOI-MOS transistor is reducing the parasitic resistances at the source and drain regions. A partial circumvention of the problem is often achieved by epitaxially growing silicon material on top of a thin channel layer so that sufficient material is available for silicidation and subsequent via processes. Another challenge in fabricating SOI-MOS devices is the often required introduction of novel materials such as metal gate materials, high-k gate dielectrics, silicon germanium alloys, etc., for better performance and scalability Device to reach. However, such new materials have the disadvantage that when forming other semiconductor technology components (for example, the gate insulating layer of a field effect transistor) occurring temperatures are so high that these novel materials can be adversely affected or even destroyed at such high process temperatures. As the dimensions become smaller, the handling of existing dopants also becomes difficult for similar reasons.

In particular, problems with the FD-SOI technology are to form a channel region of very small thickness, to contact the source / drain regions with sufficiently low terminal resistance, and to use a charge-depleted transistor by selecting the gate material (and not to adjust as in conventional transistors by adjusting the channel doping).

One way to create a very thin channel region is the recessed channel technology described in [2].

[2] discloses a method for processing a dummy depleted SOI transistor based on forming a recess in a channel region ("recessed channel"). Technology). After a channel region has been formed as a thinned region of a silicon layer, a gate region made of polycrystalline silicon is formed above it.

In particular, [2] discloses a method of manufacturing an SOI field effect transistor in which a hard mask is formed on a patterned silicon layer of an SOI substrate. Subsequently, a window is formed in the hard mask to expose the silicon layer in a window area. The silicon layer is removed in the window area. Thereafter, a gate insulating layer is formed in the window, and a gate electrode is formed thereon. The unetched portions of the silicon layer are used as the source / drain regions, and the re-etched portion of the silicon layer is used as the channel region. A gate region of polycrystalline silicon material is formed.

[3] discloses that the work function of carbon material is about 4.85eV.

In [4], structures are disclosed which serve to dissipate heat from semiconductor devices. The heat dissipation is achieved by thermally conductive structures of diamond or diamond-like material, wherein formed to form the thermally conductive structures in a silicon layer trenches and then filled with diamond or Diamant¬ similar material.

The invention is based in particular on the problem of providing a layer arrangement which is improved compared to [2] and which can be used in particular as a field-effect transistor. The problem is solved by a layer arrangement, by a field effect transistor and by a method for producing a layer arrangement having the features according to the independent patent claims.

The layer arrangement according to the invention comprises a substrate, a semiconductor layer on the substrate, a trench in the semiconductor layer, electrically insulating material on the sidewalls and at the bottom of the trench and carbon-containing material on the electrically insulating material in the trench.

In addition, according to the invention, a field effect transistor is provided with a layer arrangement having the features described above.

Further, according to the present invention, there is provided a method of fabricating a layered structure in which a semiconductor layer is provided on a substrate, a trench is formed in the semiconductor layer, electrically insulating material is formed on the sidewalls and bottom of the trench, and carbon material is formed on the electrically insulating material in the trench.

A basic idea of the invention is to provide a field effect transistor einrichtbare layer arrangement in which a thinned portion of a semiconductor layer is provided as a channel region in "recessed channel" technology with an extremely small thickness and a due of the thinned semiconductor layer region-generated trench is filled with carbon-containing material as the gate region. The use of carbon material as a gate region is very advantageous for a FD-SOI field effect transistor. In such an ultrathin channel FD-SOI field effect transistor, the transistor characteristics (particularly the threshold voltage) can be adjusted by selecting the gate material rather than by channel doping, as is conventional. Carbon material is a so-called "midgap material", ie the threshold voltage of a field effect transistor based on the layer arrangement according to the invention is due to the implementation of a carbon gate region for both an n-MOS field effect transistor and a p-MOS Field effect transistor possible. Thus, the layer arrangement according to the invention is outstandingly suitable for CMOS applications. The midgap material property of carbon is due to the fact that the work function for carbon is in the range of about 5eV (according to [3] at about 4.85 eV), ie closer to silicon midgap than to n ⁺ doped or p ⁺ doped polysilicon.

Carbon as the trench-filling material of the layer arrangement is well compatible with other process materials that can be used for the layer arrangement, in particular in the context of silicon microtechnology (eg, silicon, silicon oxide, silicon nitride), and thus can also be incorporated into existing processes with reasonable effort , In particular, carbon material has a good deposition property on electrically insulating material on the inner wall of the trench, which preferably contains silicon oxide as electrically insulating material and can serve as a field-effect transistor as a gate-insulating layer in one embodiment of the layer arrangement. Also, carbon material is typical Process conditions (temperature, chemical environment) of the silicon micro-technology in particular for the manufacture of field effect transistors compatible. This compatibility includes the property of good temperature resistance and the ability to easily etch back a carbon layer by dry etching (eg, H ₂ , O ₂ , air or plasma etching).

An important aspect of the invention may be seen as combining recessed channel processing to form the layer assembly with the use of carbon, particularly polycrystalline carbon, as a novel trench filling material. In this case, due to its "midgap workfunction", the carbon material can advantageously be used both for p-MOS devices and for n-MOS devices.

The layer arrangement according to the invention serves according to a preferred embodiment as a fully depleted field effect transistor with very good performance. Using the SOI technology, an FD-SOI transistor with ultrathin channel region and carbon as gate material is provided according to the invention.

The use of carbon material for filling in the trench or as a gate material of a layer arrangement arranged as a field effect transistor has the additional advantage that such a carbon layer has a very good electrical conductivity, so that a low-loss signal supply to the gate Range is possible and above all a fast device is realized because the signal delay is kept low due to the low ohmic resistance of the carbon material. Preferred developments of the invention will become apparent from the dependent claims.

In the following, embodiments of the layer arrangement according to the invention will first be described.

An electrically insulating layer may be provided between the substrate and the semiconductor layer of the layer arrangement.

In the layer arrangement, the substrate, the electrically insulating layer and the semiconductor layer may be formed as a silicon on insulator substrate (SOI substrate). In other words, according to this embodiment, the substrate forms a bulk silicon wafer, the electrically insulating layer forms a buried silicon oxide layer, and the semiconductor layer forms a top silicon layer of a very small thickness. Starting from an SOI substrate, processing can already be started with a very thin top silicon layer as the semiconductor layer, so that an extremely thin channel region can be formed by thinning a central section of the semiconductor layer.

The semiconductor layer (in particular the thinned central region of the semiconductor layer, which can be used as channel region) of the layer arrangement can be partially depleted on charge carriers, and is preferably fully depleted on charge carriers. ,

The semiconductor layer may have a thickness of at most 30 nm, preferably at most 10 nm, in the region of the trench exhibit. In other words, the thinned portion of the semiconductor layer may have a thickness of at most 30 nm, preferably at most 10nrα. In a channel region of this thickness, a particularly good adjustability of the electrical conductivity of the channel region can be achieved by applying an electrical signal to the gate region using the field effect.

The carbon-containing material may be carbon. According to this embodiment, the carbon-containing material is formed solely of carbon and does not have other components at most or at most in trace amounts (i.e., in insignificant amounts).

The carbon-containing material may include or consist of polycrystalline carbon. Polycrystalline carbon is ideal as a midgap material for p-MOS devices and n-MOS devices.

For brevity, the properties of different carbonaceous materials (e.g., polycrystalline carbon, graphite, diamond, etc.) useful in the layer assembly of the present invention will be briefly contrasted. Due to their high electrical conductivity, polycrystalline carbon and graphite are particularly suitable.

The resistivity for undoped materials is for graphite at a few mΩcm, ie about 5 mΩcm, for diamond it is much greater than 1 mΩcm, ie, in the range of 100 mΩcm to 1000 mΩcm, and for the invention preferred material of polycrystalline carbon at about 1 mΩcm (undoped carbon of order of magnitude doped silicon). Thus, the inventively preferred material made of carbon has orders of magnitude lower resistivity than diamond.

The specific resistance for doped materials for graphite is a few μΩcm, ie about 5 μΩcm, for highly doped diamond (10 ²⁰ to 10 ²¹ per cm ³ ) at some 1 mΩcm, ie in the range of 5 mΩcm and for the preferred material according to the invention of polycrystalline carbon at about 10 μΩcm to 1 μΩcm, preferably at about 1 μΩcm. Thus, the carbon material preferred according to the invention also has a specific order of magnitude lower resistivity than diamond in the doped state. Depending on the doping or implantation or intercalation, it is even possible for the carbon material preferred according to the invention to have a lower specific resistance than silver, which has a specific resistance of 1.6 μΩcm.

The roughness of Higly Oriented Pyrolitic Graphite (HOPG) is less than 1 nm, that of diamond is highly dependent on the microstructure, i. grain size and orientation, stress, impurities and dislocations within the diamond. For the material of polycrystalline carbon preferred according to the invention, the roughness is between 1 nm and 3 nm, in particular about 2 nm + 0.3 nm. The roughness of the material of carbon preferred according to the invention lies between HOPG and diamond.

The grain size of HOPG is about 10 microns and in polycrystalline CVD diamond, ie diamond, which is produced by chemical vapor deposition, at some to, ie about 5 microns. The grain size of the invention preferred Polycrystalline carbon material is between 0.5 nm and 3 μm, in particular 1 μm to 2 mm.

The hardness of graphite is about 0.2 GPa and that for diamond is 10 GPa to several 100 GPa, i. up to about 500 GPa. The hardness of the inventively preferred material of polycrystalline carbon is between 2 GPa and 9 GPa, in particular about 6 GPa to 7 GPa.

The elasticity of graphite is about 8 GPa and for diamond about 400 GPa to 500 GPa. The elasticity of the inventively preferred material of polycrystalline carbon is between 50 GPa and 150 GPa, in particular about 80 GPa and thus lies between the elasticity of graphite and diamond.

The layer arrangement can be set up as a field-effect transistor.

According to this embodiment, the (thinned) portion of the semiconductor layer below the trench may be configured as a channel region, regions of the semiconductor layer adjacent to the trench may be the first source / drain region and the second source / drain region be arranged (ie, a first unthinned portion of the semiconductor layer may be configured as a first source / drain region and a second unthinned portion of the semiconductor layer may be configured as a second source / drain region), at least a part of electrically insulating material may be configured as a gate insulating layer and the carbon-containing material may be configured as a gate region. The layer arrangement can optionally as p-MOS field effect transistor or used as an n-MOS field effect transistor.

Furthermore, according to the invention, a CMOS arrangement is formed, with a first layer arrangement according to the invention, which is set up as a p-MOS field-effect transistor, and with a second layer arrangement according to the invention, which is set up as an n-MOS field-effect transistor. These two layer arrangements can be integrated in a common substrate. Since carbon material is a midgap material, the carbon material may be provided as a gate region both in a p-MOS field effect transistor and in an n-MOS field effect transistor, so that a high-performance CMOS device is formed with little effort is.

In the following, the method according to the invention for producing a layer arrangement will be described in more detail. Embodiments of the layer arrangement also apply to the method for producing the layer arrangement and vice versa.

In particular, two different processes are possible for depositing the carbon layer.

According to a first process, at a temperature of preferably 950 ° Celsius and a pressure of 1 hectopascal in H2 atmosphere then a gas flow of a carbonaceous gas such as methane (CH ₄ ) can be adjusted, whereby the pressure is set to, for example, 600 hectopascals. The thickness of the deposited carbon layer can be adjusted over the processing time.

According to a second method, at 800 ° C in a photon furnace at a pressure of 2.5 Torr (about 3.3 Hectopascal) of hydrogen and 7.5 torr (about 10 hectopascal) of methane carbon layer are formed.

In particular, the deposition of polycrystalline carbon can be carried out, as described below. A polycrystalline carbon layer is understood in particular to mean a layer which consists essentially of carbon and which in partial regions has a graphite structure, i. a hexagonal lattice structure which can be considered crystalline. However, the individual "crystalline" subregions with hexagonal structures are separated by regions which have no hexagonal lattice structures, or at least separated by hexagonal lattice structures which have a different orientation to the adjacent "crystalline" subregions.

In a first process, at a temperature between 900 ° Celsius and 970 ° Celsius, preferably 950 ° Celsius, a hydrogen atmosphere is generated at a pressure of 1 hectopascal. Subsequently, a carbon-containing gas, for example, methane (CH ₄ ) or acetylene (C ₂ H ₄ ), is introduced until a total pressure of about 600 hectopascals sets. Under these conditions, a polycrystalline carbon layer separates out. Preferably, the carbonaceous gas is constantly introduced during the deposition process, so that the total pressure remains substantially constant.

In a second process for producing a polycrystalline carbon layer, at a temperature of about 800 ° C, a hydrogen atmosphere of about 2 Torr to 3 Torr, preferably 2.5 Torr, which is about 3.3 hectopascals corresponds, generated. Simultaneously with heating by means of a normal oven, a so-called photon furnace is used, ie a light source which additionally provides energy. As a result, the temperature can be reduced compared to the method described above, which can be advantageous depending on the field of application. A carbon-containing gas, for example methane (CH ₄ ), acetylene (C ₂ H ₄ ) or alcohol vapor, preferably ethanol vapor (C ₂ H ₅ OH), is then in turn introduced into the hydrogen atmosphere until a total pressure between 6.5 Torr and 8, 5 Torr, preferably 7.5 Torr, which corresponds to about 10 hectopascals, is reached. Even under these conditions, a polycrystalline carbon layer separates out. Also in this process, the carbonaceous gas is preferably continuously introduced while the conformal deposition is performed.

In summary, the carbon-containing material can be formed by supplying a carbon-containing gas in a hydrogen atmosphere having a total pressure of between 1 hectopascal and 4 hectopascal and at a temperature between 600 ° C and 1000 ° C.

The carbonaceous gas may be methane, ethane, acetylene or alcohol vapor.

The temperature can be set between 900 ° Celsius and 970 ° Celsius, the total pressure of the hydrogen atmosphere can be 1 hectopascal, and in forming the carbonaceous layer enough carbonaceous gas can be supplied to set a total pressure between 500 hectopascals and 700 hectopascals , Alternatively, the temperature may be set between 750 ° C and 850 ° C, the total hydrogen atmosphere pressure may be 1.5 Hectopascals, and carbon-forming layer may be carbonated enough to produce a total pressure of between 9 and Hectopascals 11 hectopascal sets.

The temperature may be maintained at least in part by means of photon heating and / or by using a plasma.

The trench may be formed in the semiconductor layer by removing material of the semiconductor layer, i. by thinning the semiconductor layer (for example, in a central portion of the semiconductor layer).

Embodiments of the invention are illustrated in the figures and are explained in more detail below.

Show it:

FIGS. 1 to 12 layer sequences at different times during a method for producing a field-effect transistor according to a preferred exemplary embodiment of the invention,

FIG. 13 according to the method according to FIGS. 1 to 12. produced field effect transistor according to a preferred embodiment of the invention.

The same or similar components in different figures are provided with the same reference numerals. The illustrations in the figures are schematic and not to scale.

The silicon-on-insulator substrate 100 shown in FIG. 1 contains a bulk silicon substrate 101, a buried oxide 102 (BOX) formed thereon, and a thin top layer formed on the silicon oxide layer 102. Silicon layer 103 of crystalline silicon material (c-Si).

In order to obtain the laterally limited silicon layer 201 shown in FIG. 2, an active region ("mesen") is defined using a lithography process and an etching process based on the top silicon layer 103.

In order to obtain the layer sequence 300 shown in FIG. 3, first sidewall spacers 301 are formed on the sidewalls of the laterally limited silicon layer 201. The first sidewall spacers 301 may be formed of silicon oxide material or silicon nitride material. This ensures a lateral isolation of the mesen.

In order to obtain the layer sequence 400 shown in FIG. 4, a silicon nitride hard mask 401 is deposited on the layer sequence 300.

In order to obtain the layer sequence 500 shown in FIG. 5, photoresist material (lacquer) is first deposited on the layer sequence 400 and patterned using a lithography process and an etching process in such a way that photoresist material is removed in a central section , whereby a window 502 is formed and a Surface area of the silicon nitride hardmask 401 is exposed.

In order to obtain the layer sequence 600 shown in FIG. 6, the silicon nitride hard mask 401 is etched into the exposed area using a dry etching method, thereby forming a patterned silicon nitride hard mask 401 and exposing a surface area of the laterally confined silicon layer 201 becomes. Subsequently, for example, by means of a stripping method, the photoresist 501 is removed from the surface of the layer sequence thus obtained.

In order to obtain the layer sequence 700 shown in FIG. 7, the laterally limited silicon layer 201 is thinned using a dry etching method. As a result, a thinned silicon region 703 is formed in a central section of the laterally delimited silicon layer 201, to which a first, unthinned silicon region 701 adjoins on the left side according to FIG. 7 and a second, unthinned silicon region 702 on the right side according to FIG Due to the removal of silicon material during thinning of the laterally confined silicon layer 201, a trench 704 remains in a central portion of the laterally confined silicon layer 201.

In order to obtain the layer sequence 800 shown in FIG. 8, a protective silicon oxide layer 801 is initially formed (for example by means of thermal oxidation or using a deposition method) in a horizontal bottom region of the trench 704 according to FIG. Next, second sidewall spacers 802 of silicon nitride material are formed on vertical walls of the trench 704, as shown in FIG. In order to obtain the layer sequence 900 shown in FIG. 9, the layer sequence 800 is subjected to a wet etching process for smoothing, whereby the protective silicon oxide layer 801 is removed.

To obtain the layer sequence 1000 shown in Fig. 10, a gate insulating layer 1001 of silicon oxide material is formed on the exposed portion of the laterally-patterned silicon layer 201, i. formed predominantly on the thinned silicon region 703 in the trench 704.

In order to obtain the layer sequence 1100 shown in FIG. 11, polycrystalline carbon material 1101 is deposited over the entire surface of the layer sequence 1000, whereby the trench 704 is completely filled with carbon material and also other regions of the layer sequence are covered with carbon material. In this carbon deposition method, a gas flow of the carbon-containing gas methane (CH ₄ ) is then set at a temperature of 950 ° Celsius and a pressure of 1 hectopascal in H2 atmosphere, whereby the pressure is set to 600 hectopascal, for example.

In order to obtain the layer sequence 1200 shown in FIG. 12, the deposited polycrystalline carbon material 1101 is etched back so that carbon material remains only in the trench 704, thus forming a carbon gate region 1201 of polycrystalline carbon material.

To the field effect transistor shown in Figure 13 1300 according to the preferred embodiment of the invention to obtained, the silicon nitride hardmask 401 is removed using an etching process.

In the field effect transistor 1300, the first un-thinned silicon region 701 is established as the first source / drain region 1301, the second undiluted silicon region 702 is established as the second source / drain region 1302, and the thinned silicon region 703 is ultra-thin channel region 1303 formed. Thus, the field effect transistor 1300 of Fig. 13 is an FD-SOI MOSFET having excellent transistor characteristics. The following publications are cited in this document

[1] T. Yonehara and K. Sakaguchi, "ELTRAN ^®; Novel SOI wafer technology", JSAP International No.4 (JuIy 2001), pp. 10-16

DE 102 33 663 A1

[3] G. Raghavan, J.L. Hoyt and J.F. Gibbons, Jpn. J. Appl. Phys., Vol.32 (1993), pp. 380-383

[4] US 2003/0189231 Al LIST OF REFERENCE NUMBERS

100 silicon-on-insulator substrate 101 semiconductor silicon substrate 102 silicon oxide layer 103 top silicon layer 200 layer sequence 201 laterally delimited silicon layer 300 layer sequence 301 first sidewall spacer 400 layer sequence 401 silicon nitride hard mask 500 layer sequence 501 photoresist 502 window 600 Layer sequence 601 window 700 layer sequence 701 first undiluted silicon region 702 second undiluted silicon region 703 thinned silicon region 704 trench 800 layer sequence 801 protective silicon oxide layer 802 second sidewall spacer 900 layer sequence 1000 layer sequence 1001 gate-insulating layer 1100 layer sequence 1101 polycrystalline carbon Material 1200 layer sequence 1201 carbon gate region 1300 field effect transistor 1301 first source / drain region 1302 second source / drain region 1303 ultra-thin channel area

Claims

claims: 1st layer arrangement, ^■ • with a substrate; • with a semiconductor layer on the substrate; • with a trench in the semiconductor layer; • with electrically insulating material on the sidewalls and at the bottom of the trench; • Carbon-containing electrically conductive material on the electrically insulating material in the trench. 2. Layer arrangement according to claim 1, with an electrically insulating layer between the substrate and the semiconductor layer. 3. The layer arrangement according to claim 2, wherein the substrate, the electrically insulating layer and the semiconductor layer are formed as a silicon on insulator substrate. 4. Layer arrangement according to one of claims 1 to 3, wherein the semiconductor layer is completely depleted of charge carriers. 5. A layer arrangement according to any one of claims 1 to 4, wherein the semiconductor layer in the region of the trench has a thickness of at most ten nanometers. 6. Layer arrangement according to one of claims 1 to 5, wherein the carbon-containing material consists of carbon. 7. A layer assembly according to any one of claims 1 to 6, wherein the carbon-containing material comprises polycrystalline carbon. 8. Field effect transistor, with a layer arrangement according to one of claims 1 to 7. 9. Field effect transistor according to claim 8, wherein • the area of the semiconductor layer below the trench is set up as a channel area; • regions of the semiconductor layer adjacent to the trench are arranged as a first source / drain region and as a second source / drain region; • at least a part of the electrically insulating material is designed as a gate-insulating layer; • The carbon-containing material is set up as a gate area. 10. A method for producing a layer arrangement, in which • a semiconductor layer is provided on a substrate; • a trench is formed in the semiconductor layer; • electrically insulating material is formed on the side walls and ■ at the bottom of the trench; Carbon-containing material is formed on the electrically insulating material in the trench. 11. The method of claim 10, wherein the carbon-containing material is formed by, in a hydrogen atmosphere with a total pressure between 1 hectopascal and 4 hectopascal and at a temperature between 600 ° Celsius and 1000 ° Celsius, a carbon-containing gas is supplied. 12. The method of claim 11, wherein the carbonaceous gas is methane, ethane, acetylene or alcohol vapor. 13. The method of claim 11 or 12, wherein the temperature between 900 ° Celsius and 970 ° Celsius, the total pressure of the hydrogen atmosphere is 1 hectopascal and in the formation of the carbon-containing layer so much carbon-containing gas is supplied that a total pressure between 500 Hektopascal and 700 hectopascal. 14. The method of claim 11 or 12, wherein the temperature between 750 ° C and 850 ° C, the total pressure of the hydrogen atmosphere is 1.5 hectopascal and in the formation of the carbon-containing layer so much carbon-containing gas is supplied that a total pressure between 9 hectopascal and 11 hectopascal sets. 15. The method according to any one of claims 11 to 14, wherein the temperature is maintained at least partially by means of a photon heater and / or by using a plasma. 16. The method of claim 10, wherein the trench is formed in the semiconductor layer by removing material of the semiconductor layer.