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WO2005008170A2 - Traitement de normale de contour - Google Patents

Traitement de normale de contour Download PDF

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Publication number
WO2005008170A2
WO2005008170A2 PCT/US2004/022401 US2004022401W WO2005008170A2 WO 2005008170 A2 WO2005008170 A2 WO 2005008170A2 US 2004022401 W US2004022401 W US 2004022401W WO 2005008170 A2 WO2005008170 A2 WO 2005008170A2
Authority
WO
WIPO (PCT)
Prior art keywords
edge
wafer
images
normal
defects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2004/022401
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English (en)
Other versions
WO2005008170A3 (fr
Inventor
Cory Watkins
Mark Harless
Francy Abraham
Hak Chuah Sim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
August Technology Corp
Original Assignee
August Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by August Technology Corp filed Critical August Technology Corp
Priority to KR1020067000874A priority Critical patent/KR101060428B1/ko
Priority to JP2006520266A priority patent/JP4949024B2/ja
Priority claimed from US10/890,762 external-priority patent/US7340087B2/en
Priority claimed from US10/890,692 external-priority patent/US6947588B2/en
Publication of WO2005008170A2 publication Critical patent/WO2005008170A2/fr
Publication of WO2005008170A3 publication Critical patent/WO2005008170A3/fr
Priority to US11/331,619 priority patent/US7366344B2/en
Anticipated expiration legal-status Critical
Priority to US12/036,679 priority patent/US7706599B2/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/10—Image acquisition
    • G06V10/12—Details of acquisition arrangements; Constructional details thereof
    • G06V10/14—Optical characteristics of the device performing the acquisition or on the illumination arrangements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/9501—Semiconductor wafers
    • G01N21/9503—Wafer edge inspection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F18/00—Pattern recognition
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/10—Segmentation; Edge detection
    • G06T7/12—Edge-based segmentation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer

Definitions

  • the present invention relates to an inspection system that inspects the edge of a semiconductor wafer or like substrate such as a microelectronics substrate.
  • edge inspection is important for detecting delamination of thin films, chipping and cracking of the wafer, resist removal metrology, and particle detection that all cause yield issues in a modern fab.
  • edge of the wafer is a leading indicator of process status, and by monitoring the edge of the wafer for changes in appearance, tighter process control can be implemented.
  • One proposed solution laser/analog detector technology that looks directly at the edge normal of the wafer. This solution provides limited benefits in detecting particles and chip-outs, and is limited in classifying defects since the solution does not perform image processing. There is a need for continued improvement in edge inspection.
  • An edge inspection method for detecting defects on a wafer surface includes acquiring a set of digital images which captures a circumference of the wafer. An edge of the wafer about the circumference is determined. Each digital image is segmented into a plurality of horizontal bands. Adjacent edge clusters about the circumference of the wafer are combined into edge pixel bins. The edge pixel bins are analyzed via edge clusters analysis to identify defects. The edge pixel bins are also analyzed via blob analysis to determine defects.
  • Figure 1 is a schematic diagram illustrating one embodiment of an edge inspection system
  • Figure 2 is a schematic diagram illustrating the indicated portion of the edge inspection system illustrated in Figure 1 in more detail
  • Figure 3 is a schematic diagram illustrating another embodiment of an edge inspection system
  • Figure 4 is a top view illustrating one embodiment of the edge inspection system
  • Figure 5 is an angled perspective view illustrating one embodiment of the edge inspecting system
  • Figure 6 is a front perspective view illustrating one embodiment of the edge inspection system
  • Figure 7 is a side view illustrating one embodiment of an edge top sensor
  • Figure 8 is a perspective view illustrating one embodiment of an edge normal sensor
  • Figure 9 is a flow diagram illustrating one embodiment of a method for inspecting the edges of semiconductor wafers
  • Figure 10 is a flow diagram illustrating one embodiment of a method for inspecting
  • Figure 11 is a partial side view illustrating wafer edge normal detection.
  • Figures 12A and 12B are partial side views illustrating a normal edge of a wafer.
  • Figure 13 is a diagram illustrating the intensity of various wafer normal edge bands.
  • Figures 14A-14C are graphs illustrating intensities of various lateral bands of a normal edge of a wafer. Similar numerals refer to similar parts throughout the drawings.
  • the edge normal inspection method of the present invention may be used on any of a number of edge inspection systems.
  • the present invention is a method of detecting defects along the wafer edge normal surface.
  • the method of finding defects on the wafer edge normal of the present invention involves the following steps: (1) detection of the wafer edge, (2) image normalization, (3) horizontal band segmentation, (4) lateral illumination correction, (5) creation of a dynamic reference image, (6) image edge analysis, (7) edge pixels bin clustering, (8) edge cluster analysis, (9) blob analysis on difference image, and (10) statistical manipulation.
  • Figure 1 is a schematic diagram illustrating one embodiment of an edge inspection system 100.
  • Edge inspection system 100 includes an edge top sensor 102, an edge normal sensor 104, a controller 106, a base 108, and a stage 110.
  • Top edge sensor 102 includes a camera 112
  • normal edge sensor 104 includes a camera 114.
  • Stage 110 includes a motor 116, an encoder 118, and a support plate 120.
  • Motor 116 is coupled to encoder 118 and support plate 120 to rotate support plate 120;- Encoder 118 provides counts for controlling the position of motor 116.
  • Support plate 120 supports a wafer 122 for inspecting an edge 124 of wafer 122.
  • Controller 106 is electrically coupled to top edge sensor 102 through communication link 126, normal edge sensor 104 through communication link 128, and staging 130 through communication link 132.
  • Controller 106 controls edge top sensor 102, edge normal sensor 104, and staging 130 for inspecting edge 124 of wafer 122.
  • Figure 2 is a schematic diagram illustrating the indicated portion of edge inspection system 100 illustrated in Figure 1 in more detail.
  • Figure 2 illustrates edge top sensor 102, normal edge sensor 104, and edge 124 of wafer 122 .
  • Edge 124 of wafer 122 includes resist layer 140 having an edge bead removal (EBR) line 142, edge exclusion region 144, wafer edge bevel 146, and wafer bottom 148.
  • Wafer edge bevel 146 includes top bevel 150, wafer edge normal 152, and bottom bevel 154.
  • Edge top sensor 102 has a field of view as indicated at 156.
  • Edge normal sensor 104 has a field of view as indicated at 158.
  • Edge inspection system 100 inspects and/or measures along edge 124 of wafer 122 including resist layer 140, edge exclusion region 144, top bevel 150, wafer edge normal 152, and bottom bevel 154.
  • Figure 3 is a schematic diagram illustrating an alternative embodiment of an edge inspection system 1 0.
  • Edge inspection system 160 in addition to edge top sensor 102, edge normal sensor 104, controller 106, staging 130, and base 108, includes edge bottom sensor 162, camera 163, and communication link 164. In this embodiment, both the top and bottom edge of wafer 122 are inspected.
  • Edge inspection system 160 performs edge inspection in substantially the same manner as edge inspection system 100 (Fig.
  • edge inspection system 160 inspects both the top of edge 124 (Fig. 2) and the bottom of edge 124 of wafer 106 via edge bottom sensor 162, camera 163, and communication link 164.
  • Figures 4 - 6 illustrate varying views of one embodiment of edge inspection system 100.
  • Figure 4 illustrates a top view
  • Figure 5 illustrates an angled perspective view
  • Figure 6 illustrates a front perspective view of edge inspection system 100.
  • Figure 7 illustrates a side view of one embodiment of edge top sensor 102
  • Figure 8 illustrates a perspective view of one embodiment of edge normal sensor 104.
  • Edge top sensor 102 is an inspection sensor and, as illustrated in Figure 7, includes edge top camera 112, a beamsplitter 166, optics 168, a brightfield light or strobe 170, a darkfield light or strobe 172, a backlight 174, and a servo motor and focus stage (not shown for clarity purposes).
  • Edge top camera 112 in one embodiment, is a color camera with the following specifications, although other parameters may be used: 10 x 5 mm field of view (FOV), 5 ⁇ m resolution, and 360° continuous coverage of the wafer edge in both brightfield and darkfield modes.
  • Edge normal sensor 104 is an inspection sensor and, as illustrated in Figure 8, includes edge normal camera 114 and one or more strobes, such as strobes 176 A and 176B, and mirrors 177 A and 177B.
  • Edge normal camera 114 in one embodiment, is positioned so as to look at the thin profile of wafer 122.
  • Camera 114 in one embodiment, is a single chip color camera with the following specifications, although other parameters may be used: 4 x 2 mm FOV, 4 ⁇ m resolution, and 360° continuous coverage of the wafer edge in mixed mode lighting.
  • the one or more strobes 176A and 176B are incident on wafer edge bevel 146 while simultaneously incident on diffuser 178 to provide mixed mode lighting.
  • Edge inspection system 100 of the present invention is used in one embodiment to inspect the edge of a substrate such as a semiconductor wafer.
  • edge inspection system 100 can inspect edge 124 of wafer 122.
  • Edge inspection system 100 is a unique system that uses multiple cameras, such as cameras 112 and 114, with corresponding strobe lights, such as strobe lights 176A and 176B for edge normal camera 114, and brightfield light 170 and darkfield light 172 (Fig. 7) for edge top camera 112.
  • Edge top camera 112 and edge normal camera 114 are used to acquire image data around the circumference of a substrate or wafer 122 for both the top of edge 124 of wafer 122 and wafer edge bevel 146, respectively.
  • edge normal camera 114 and edge top camera 112 have 4 ⁇ m and 5 ⁇ m image resolution, respectively, and special lighting diffusers to enable the detection of defects.
  • One such diffuser 178 is illustrated attached to edge normal camera 114 in Figure 4.
  • edge inspection system 100 collects or captures image data for 100% of the circumference of wafer 122 for processing and analysis.
  • the images are in color for better defect classification.
  • strobe lights 176A and 176B enable greater depth-of-field for edge normal camera 114, enabling easier review of wafer edge bevel 146 by not having to focus on wafer edge bevel 146. Even more, edge top camera 112 captures two passes of data around the circumference of wafer 122.
  • the first pass is brightfield data, while the second pass is darkfield data. This enables more reliable detection of EBR line 142 for resist removal metrology and the ability to better detect and classify particles and other contaminants as either surface particles or embedded particles.
  • all of the data from a single wafer is collected in less than approximately 10 seconds and processed in less than approximately 30 seconds.
  • wafer 122 is spun by motor 116.
  • wafer 122 is spun two revolutions or most preferably slightly more than two full revolutions such as 2.1 revolutions or the like to provide a bit of overlap to assure that all data is collected.
  • the brightfield strobe 170 and backlight 174 are illuminated and images are gathered around the circumference of wafer 122.
  • the images are passed to controller 106 where algorithms process the images to look for defects, wafer center, wafer edges, EBR lines, and the notch.
  • Edge data of wafer 122 is fed to the motion control system (not shown for clarity purposes) of edge normal camera 114 in order to keep edge normal camera 114 in focus while edge normal camera 114 is inspecting edge 124 of wafer 122.
  • darkfield images are collected at the same positions on wafer 122 as the corresponding brightfield images.
  • the wafer edge data obtained by edge top camera 112 during the first revolution is used to focus edge normal camera 114 by controlling servo motor 180 to move sensor 104 on focus stage 182.
  • dual strobes 176A and 176B with diffuser 178 and a small aperture 184 enable 0.5 mm depth- of-field for edge normal camera 114.
  • the edge normal images are collected from 100% of the circumference of wafer 122.
  • the images are passed to controller 106 where the algorithms process the images to look for defects.
  • edge normal camera 114 is a color camera, thus enabling better defect capture ability such as thin film variation, particles, delamination, residual resist, slurry ring, etc.
  • Edge inspection system 100 includes staging 130 that has support plate
  • staging 130 is a Continuous Rotate Stage including motor 116 and encoder 118.
  • encoder 118 is a 1.3 Million Counts/Rev encoder.
  • stage 130 includes a vacuum to hold afer 122 in place on support plate 120.
  • edge inspection system 100 is packaged in an integrated metrology module of the type contemplated under draft Semiconductor Equipment and Materials (SEMI) standard 3377C for integrated metrology modules (IMM). In this embodiment, edge inspection system 100 attaches to a loadport using an interface such as a 300 mm BOLTS interface.
  • SEMI Semiconductor Equipment and Materials
  • edge inspection system 100 is part of multiple inspection modules clustered about a single robot and controller, thereby reducing handling costs and inspection data flow costs. This novel multiple inspection module approach further allows more than one module of the same type to be attached to the cluster to improve throughput or add reliability.
  • edge inspection system 100 detects defects and variations along the edge 124 of wafer 122, such as particles, chips, cracks, delamination, copper- overflow, resist particles, embedded particles, etc. Detecting these types of defects enables either re-work, discontinuing processing, or process enhancement to achieve better yields.
  • edge inspection system 100 is very fast (in one embodiment over 100 wafers per hour), of a small form factor, low cost, robust, and offline review capable (preferably in color images).
  • edge inspection system 100 performs various processes, including either or both EBR and edge of wafer (EEW) metrology measurement, chip and/or crack inspection, contamination and/or particles inspection, and delamination inspection using image processing techniques.
  • EBR and/or EEW metrology step involves analyzing the images to obtain the measurement from wafer edge normal 152 of wafer 122 to EBR line 142 of resist layer 140.
  • the chip and/or crack inspection involves analyzing the images for chips and cracks evident along wafer edge normal 152, top bevel 150, and bottom bevel 154.
  • the contamination and/or particles inspection involves analyzing the images for anomalies found on wafer edge bevel 146 or in edge exclusion region 144 of wafer 122.
  • edge inspection system 100 has the following EBR and/or EEW metrology performance characteristics: up to and including full 360° continuous measurements (selectable amounts less than this), 1° increments, 50 ⁇ m accuracy, and lO ⁇ m repeatability. As to chips and cracks, lOO ⁇ m or greater accuracy is provided. As to contamination and particles, 5 ⁇ m resolution and full coverage edge top and edge normal is provided.
  • edge inspection system 100 is capable of full color defect images, multiple revolutions per inspection, approximately 20 seconds per complete inspection using both edge top 102 and edge normal 104 sensors, approximately 12 seconds for wafer handling, and approximately 120 or more wafers per hour (WPH).
  • Figure 8 is a flow diagram illustrating one embodiment of a method 200 for detecting defects on edge 107 (Fig. 2) of semiconductor wafer 106.
  • wafer 106 is loaded on stage 110 and held in place by support plate 108 and a vacuum.
  • controller 118 activates brightfield illumination for sensor 102.
  • controller 118 begins rotating wafer 106 on stage 110 using motor 112.
  • top edge sensor 102 obtains images of the top of edge 107 of wafer 106.
  • controller 118 determines if the first rotation of wafer 106 is completed. If the first rotation of wafer 106 is not completed, control returns to block 206 where wafer 106 continues to rotate and images continue to be obtained with edge top camera 102. If the first rotation of wafer 106 is completed, then at 212, the images of the top of edge 107 of wafer 106 are analyzed by controller 118 and used to control the position of edge normal sensor 104 to keep edge normal camera 113 in focus.
  • controller 118 deactivates the brightfield illumination for sensor 102.
  • controller 118 activates the darkfield illumination for sensor 102.
  • controller 228 rotates wafer 106.
  • top edge camera 111 obtains images of the top of edge 107 of wafer 106.
  • normal edge camera 113 also obtains images of wafer edge bevel 129.
  • controller 118 determines if the second rotation of wafer 106 is completed. If the second rotation of wafer 106 is not completed, control returns to block 218 where wafer 106 continues to rotate and images continue to be obtained with normal edge camera 104. If the second rotation of wafer 106 is completed, then at 226, the images of the top of edge 107 and wafer edge bevel 129 of wafer 106 are analyzed to locate any edge defects.
  • FIG. 10 is a flow diagram illustrating one embodiment of a method for inspecting a normal edge of a semi-conductor wafer, such as wafer edge normal 152 of wafer 122.
  • the edge normal inspection method of the present invention maybe used on any of a number of edge inspection systems, such as edge inspection system 100 shown described with reference to Figures 1-8.
  • method 300 shown in Figure 10, inspects wafer edge normal 152 and identifies defects due to delamination of thinfilms, chipping and cracking of the wafer, resist removal metrology, and particle detection that all cause yield issues in a modern fab.
  • Method 300 includes the following steps: detection of the wafer edge (step 302), image normalization (step 304), horizontal band segmentation (step 306), lateral illumination correction (step 308), dynamic reference imaging (step 310), image edge analysis (step 312), edge pixel bin clustering (step 314), edge cluster analysis (step 316), blob analysis on difference image (step 318), and statistical manipulation (step 320).
  • the present method performs all essential image processing steps using- the green channel. Red and blue channels are determined only for all defect areas to achieve color defect classification. In another embodiment, red and blue channel processing may also be included in all essential image processing steps.
  • the detection of wafer edge 124 is accomplished and shown in greater detail in Figure 11.
  • a zero-crossing edge detector can be used to locate the top and bottom sides of the wafer foreground process area and is a three step process: first, top and bottom wafer side coarse detections 404A and 404B are centered at the middle of the image generate coarse detection. Second, fine edge detections 406A and 406B sample projections along the top and bottom wafer sides estimated in the preceding coarse detection. Third, least square fit lines 408A and 408B are used to compute parametric representations for the wafer top and bottom sides using edge sample positions generated during fine detection.
  • a new normalized scene image is generated as shown in Figure 1 IB using least square fit line equations 408 A and 408B for top and bottom sides (from step 302) to correct for wafer tilt.
  • the normalized scene image is aligned such that the image is parallel to the horizontal axis of inspection system 100.
  • the height of the wafer edge is determined by the equation (hi + h 2 )/2.
  • wafer anamoly 410 is unaltered during the normalization process.
  • the normalized scene image can also include predefined bands of background regions adjacent to the wafer foreground region as shown in Figure 12B.
  • the remaining processing steps are applied to the normalized scene image and not the original test image.
  • the normalized scene image is segmented into horizontal bands of uniform (or near uniform) shades as shown in Figure 13. Segmentation is accomplished by detecting fairly large intensity transitions in the vertical projection of mean pixel intensity on each scan line in the scene image.
  • the region inside the foreground region as well as two background bands immediately on top of and below the foreground region are analyzed. In one embodiment, each band should not be thinner than a minimum band thickness.
  • both the top and bottom background bands have similar band thicknesses that are pre-determined.
  • Foreground horizontal bands are segmented by splitting up the region at the Y positions that correspond to local edge maximas (after canny-type edge filtering) in the horizontal projection of each scan line in the foreground local edge maxima above average edge strength.
  • Each horizontal band has a maximum Y position, a light variation correction and a high intensity error threshold.
  • the high intensity error threshold is calculated during creation of the intensity different image for the process area.
  • the threshold is the absolute intensity error value that separates the top predefined percentage (in one embodiment, the top one percent) of the highest intensity error pixels from remaining pixels with lower absolute intensity errors.
  • lateral intensity variations of a local band is determined by combining information from the raw local bands lateral intensity variations ( Figure 14A) and the global lateral intensity variations ( Figure 14B).
  • the local lateral illumination error for a horizontal band is determined in two steps.
  • a local column intensity error vector is determined for each horizontal band.
  • This local error vector contains the mean error for each column in a specific horizontal band.
  • the local error vector comprises the difference between the mean intensity of each column and the overall mean intensity of the entire horizontal band.
  • a global column error vector is also generated by averaging all the local column error vectors.
  • the local column error vector for each horizontal band is corrected to follow the general trend of the global column error vector while retaining most of its local column variation. This step is needed to separate intensity variations caused by real defects from intensity variations caused by illumination error.
  • the vertical projection intensity shown in Figure 13 and the local band lateral intensity variation shown in Figure 14C are combined to create a dynamic reference image or model of a defect-free wafer image. Later in the process or method, this model will be utilized to find defects in wafer edge using blob analysis (step 318). In many wafer-fabrication defect cases, such as defects due to peel-off, the defect is not a distinguishing blob in contrast with adjacent properly fabricated wafer sections. Instead, fabrication defects can have intensities that blend well with the surface intensity except for small regions of sharp intensity variations within the defect area and around the perimeter of defect. At 312, image edge analysis is performed.
  • edge pixels for each horizontal band are enhanced by determining the local intensity variation for each pixel compared to a number of neighboring pixels. Heuristics are deployed to remove relatively small edge pixel clusters and to eradicate inherent intensity variations between horizontal bands in the vertical direction. Edge pixels usually appear as small separated clusters.
  • edge pixel bin clustering includes combining or connecting nearby edge clusters so that the system can associate a group of edge clusters to a single defect area.
  • Each horizontal band is divided into several 50 percent overlapping vertical columns called bins. All edge pixels within a bin are considered as a single entity. Adjacent overlapping bins share edge pixels. Two techniques are used to identify defects on the wafer: edge cluster analysis and blob analysis.
  • edge cluster analysis scans the edge cluster bins for continuous sets of non-empty bins with significantly high edge pixel counts such as greater than 120% of the average edge pixel count. In one embodiment, edge cluster analysis scans the edge cluster bins for continuous sets of non-empty bins with edge pixel counts between 120% and 150% of the average edge pixel count. If found, a single surface variation defect is associated to the bounding rectangular region of a continuous set of prominent non-empty edge pixel bins.
  • blob analysis is applied to the difference image between the normalized scene image and the dynamic model reference image to detect blobs with high pixel errors such as greater than 180% of the average pixel error.
  • blob analysis is applied to the difference image between the normalized scene image and the dynamic model reference image to detect blobs with pixel errors between 180% and 200% of the average pixel error.
  • a simple auto-thresholding technique is used to determine the minimum error threshold that will classify a pixel as defect.
  • the blob analysis also checks for edge pixel counts and perimeter contrast for each error pixel blob. This will help to reduce overkill caused by lighting variation as discussed earlier.
  • image processing techniques applied to each image frame to find potential wafer defects at 320 a statistical model of defect and imaging attributes for horizontal bands along the wafer edge across all image frames captured for the wafer is determined or constructed. For example, the roughness and intensity measurements of fine resolution horizontal band regions in the image are maintained.
  • fine band statistical data are dynamically combined to compare with the defect and image properties of horizontal bands segmented for each image frame. If a particular defect is a result of image properties for horizontal bands that are consistent for all image frames, the defect can be removed as potential overkill.
  • potential overkill includes surface variation defects found within a set of horizontal bands with consistently high roughness measurement for all the image frames. The surface variation defects will be removed because these defects are most likely inherent properties of an unpolished wafer region.
  • the statistical data can be used to identify potential escapes. For example, a set of horizontal bands in an image frame may be much brighter or darker than similar regions in other image frames.
  • Edge inspection system 100 which incorporates edge normal detection method 300 provides inspection of a normal edge of a wafer to identify defects therealong. Quality control during the fabrication process is greatly heightened. Accordingly, the invention as described above and understood by one of skill in the art is simplified, provides an effective, safe, inexpensive, and efficient device, system and process which achieves all the enumerated objectives, provides for eliminating difficulties encountered with prior devices, systems and processes, and solves problems and obtains new results in the art.

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Abstract

La présente invention concerne un procédé de vérification de contour permettant de détecter des défauts à la surface d'une plaquette. Ce procédé consiste à acquérir un ensemble d'images numériques qui capture une circonférence de la plaquette, à déterminer un contour de la plaquette autour de la circonférence, à segmenter chaque image numérique en une pluralité de bandes horizontales, à combiner des groupes de contours adjacents autour de la circonférence de la plaquette en cases de pixels de contour, à analyser les cases de pixels de contour par une analyse de groupes de contours, afin d'identifier des défauts, puis à analyser également les cases de pixels de contour par une analyse de tache, afin de déterminer des défauts.
PCT/US2004/022401 2003-07-14 2004-07-14 Traitement de normale de contour Ceased WO2005008170A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020067000874A KR101060428B1 (ko) 2003-07-14 2004-07-14 반도체와 같은 기판을 위한 에지부 검사 방법
JP2006520266A JP4949024B2 (ja) 2003-07-14 2004-07-14 縁部垂直部分処理
US11/331,619 US7366344B2 (en) 2003-07-14 2006-01-13 Edge normal process
US12/036,679 US7706599B2 (en) 2003-07-14 2008-02-25 Edge normal process

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US48695203P 2003-07-14 2003-07-14
US48695303P 2003-07-14 2003-07-14
US60/486,952 2003-07-14
US60/486,953 2003-07-14
US10/890,762 US7340087B2 (en) 2003-07-14 2004-07-14 Edge inspection
US10/890,692 2004-07-14
US10/890,762 2004-07-14
US10/890,692 US6947588B2 (en) 2003-07-14 2004-07-14 Edge normal process

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WO2005008170A3 WO2005008170A3 (fr) 2005-05-06

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Cited By (11)

* Cited by examiner, † Cited by third party
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JP2006294969A (ja) * 2005-04-13 2006-10-26 Reitetsukusu:Kk ウエハ検査装置及びウエハの検査方法
JP2007256272A (ja) * 2006-02-24 2007-10-04 Hitachi High-Technologies Corp 表面検査装置
WO2007129691A1 (fr) * 2006-05-09 2007-11-15 Nikon Corporation Appareil de contrôle de partie d'extrémité
JP2007303853A (ja) * 2006-05-09 2007-11-22 Nikon Corp 端部検査装置
JP2007303854A (ja) * 2006-05-09 2007-11-22 Nikon Corp 端部検査装置
WO2008113638A3 (fr) * 2007-03-19 2009-02-12 Vistec Semiconductor Sys Gmbh Dispositif et procédé pour l'inspection de défauts en bordure d'une plaquette, et utilisation du dispositif dans un système d'inspection pour plaquettes
WO2009054403A1 (fr) * 2007-10-23 2009-04-30 Shibaura Mechatronics Corporation Dispositif de contrôle pour substrat en forme de disque
WO2010072771A1 (fr) 2008-12-23 2010-07-01 Luvata Espoo Oy Ensemble métallique constituant un précurseur pour un supraconducteur et procédé convenant à la production d'un supraconducteur
JP2013145239A (ja) * 2006-09-29 2013-07-25 Lam Research Corporation 基板を位置決めして検査するためのオフセット補正方法および装置
CN103175469B (zh) * 2011-12-23 2017-09-08 株式会社三丰 增强型边缘聚焦工具及利用该工具的聚焦方法
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JP2006294969A (ja) * 2005-04-13 2006-10-26 Reitetsukusu:Kk ウエハ検査装置及びウエハの検査方法
JP2007256272A (ja) * 2006-02-24 2007-10-04 Hitachi High-Technologies Corp 表面検査装置
WO2007129691A1 (fr) * 2006-05-09 2007-11-15 Nikon Corporation Appareil de contrôle de partie d'extrémité
JP2007303853A (ja) * 2006-05-09 2007-11-22 Nikon Corp 端部検査装置
JP2007303854A (ja) * 2006-05-09 2007-11-22 Nikon Corp 端部検査装置
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WO2008113638A3 (fr) * 2007-03-19 2009-02-12 Vistec Semiconductor Sys Gmbh Dispositif et procédé pour l'inspection de défauts en bordure d'une plaquette, et utilisation du dispositif dans un système d'inspection pour plaquettes
WO2009054403A1 (fr) * 2007-10-23 2009-04-30 Shibaura Mechatronics Corporation Dispositif de contrôle pour substrat en forme de disque
US8488867B2 (en) 2007-10-23 2013-07-16 Shibaura Mechatronics Corporation Inspection device for disk-shaped substrate
WO2010072771A1 (fr) 2008-12-23 2010-07-01 Luvata Espoo Oy Ensemble métallique constituant un précurseur pour un supraconducteur et procédé convenant à la production d'un supraconducteur
CN103175469B (zh) * 2011-12-23 2017-09-08 株式会社三丰 增强型边缘聚焦工具及利用该工具的聚焦方法
WO2022225545A1 (fr) 2021-04-19 2022-10-27 Kla Corporation Inspection de profil de bord à la recherche de défauts de délaminage
EP4285316A4 (fr) * 2021-04-19 2025-01-01 KLA Corporation Inspection de profil de bord à la recherche de défauts de délaminage

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WO2005008170A3 (fr) 2005-05-06
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JP4949024B2 (ja) 2012-06-06
JP2007536723A (ja) 2007-12-13

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