WO2004095578A1 - Semiconductor device and production method therefor - Google Patents

Abstract

An insulation film (24) having a gentle surface inclination is formed by a high-density plasma CVD method or a normal-pressure CVD method after a ferroelectric capacitor (23) is formed. Then, an alumina film (25) is formed on the insulation film (24). Such a method can positively protect the ferroelectric capacitor (23) despite the low coverage of the alumina film (25).

Description

 Specification'

 Semiconductor device and method of manufacturing the same

 The present invention relates to a semiconductor device with improved resistance to the entry of hydrogen and moisture from the outside and a method for manufacturing the same. Background art

 Recently, the wiring rule for ferroelectric memory (FeRAM) is 0.35 m, and the plasma CVD method is mainly used to form the interlayer insulating film.

 Further, in the ferroelectric memory, an alumina film directly covering the ferroelectric capacitor is formed as a hydrogen diffusion preventing film in order to prevent hydrogen diffusion into the ferroelectric capacitor.

 However, there has recently been an increasing demand for miniaturization of ferroelectric memories, and with miniaturization, the specifications of ferroelectric capacitors and wiring have become strict. On the other hand, the coverage of alumina films is relatively low. For these reasons, with the conventional structure, the protection of the ferroelectric capacitor is not sufficient, and deterioration of the ferroelectric capacitor is a problem.

 As for the interlayer insulating film, when a multilayer wiring structure is formed, voids may be formed in the interlayer insulating film between the ferroelectric capacitor and the wiring. This makes it difficult to obtain high reliability.

 Furthermore, high moisture resistance is a property required for most semiconductor devices, not only for ferroelectric memories.

 For this reason, a multilayer wiring structure in which a SiN film is provided between two wiring layers has been proposed. However, such a structure does not have sufficient moisture resistance.

 Patent Document 1

Japanese Patent Application Laid-Open No. 2000-01-36026 Unexamined Japanese Patent Publication No. JP 2001-150703A

 An object of the present invention is to provide a semiconductor device capable of suppressing deterioration of a semiconductor element such as a ferroelectric capacitor and a method for manufacturing the same.

 In a first semiconductor device according to the present invention, a semiconductor substrate, a ferroelectric capacitor formed above the semiconductor substrate, and directly covering the ferroelectric capacitor, and a slope of a surface thereof is the ferroelectric capacitor And an insulating film that is gentler than the slope of the surface. Then, a hydrogen diffusion preventing film for preventing diffusion of hydrogen into the ferroelectric capacitor is formed on the insulating film.

 A second semiconductor device according to the present invention includes a semiconductor substrate, a semiconductor element formed on the semiconductor substrate, and a pad formed above the semiconductor substrate and connected to the semiconductor element. One or more wiring layers formed between the semiconductor element and the pad are provided. A moisture intrusion prevention film is formed between the pad and the uppermost one of the one or two or more wiring layers to prevent moisture from entering the lower layer. .

 In the first method of manufacturing a semiconductor device according to the present invention, after forming a ferroelectric capacitor above a semiconductor substrate, the ferroelectric capacitor is directly covered, and the slope of the surface is changed to the surface of the ferroelectric capacitor. An insulating film is formed which is gentler than the inclination. Then, a hydrogen diffusion preventing film for preventing diffusion of hydrogen into the ferroelectric capacitor is formed on the insulating film.

In the second method for manufacturing a semiconductor device according to the present invention, after forming a semiconductor element on a semiconductor substrate, one or more wiring layers are formed above the semiconductor element. Next, a moisture intrusion prevention film is formed above the uppermost wiring layer located at the uppermost position among the one or more wiring layers to prevent moisture from entering the lower layer side. Then, a pad connected to the semiconductor element is formed above the moisture intrusion prevention film. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a circuit diagram showing a configuration of a memory cell array of a ferroelectric memory manufactured by a method according to an embodiment of the present invention.

 2A to 2G are cross-sectional views illustrating a method of manufacturing the ferroelectric memory according to the first embodiment of the present invention in the order of steps.

 3A to 3E are cross-sectional views illustrating a method of manufacturing a ferroelectric memory according to the second embodiment of the present invention in the order of steps. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a configuration of a memory cell array of a ferroelectric memory (semiconductor device) manufactured by a method according to an embodiment of the present invention.

 This memory cell array is provided with a plurality of bit lines 3 extending in one direction, and a plurality of lead lines 4 and plate lines 5 extending in a direction perpendicular to the direction in which the bit lines 3 extend. ing. In addition, a plurality of memory cells of the ferroelectric memory according to the present embodiment are arranged in an array so as to match the lattice formed by the bit line 3, the word line 4, and the plate line 5. I have. Each memory cell is provided with a ferroelectric capacitor 1 and a MOS transistor 2.

 The gate of the MOS transistor 2 is connected to the word line 4. Further, one of the source and drain of the MOS transistor 2 is connected to the bit line 3, and the other of the source and drain is connected to one electrode of the ferroelectric capacitor 1. Then, the other electrode of the ferroelectric capacitor 1 is connected to the plate line 5. Note that each of the lead lines 4 and the plate lines 5 are shared by a plurality of MOS transistors 2 arranged in the same direction as the direction in which they extend. Similarly, each bit line 3 is shared by a plurality of MOS transistors 2 arranged in the same direction as the direction in which the bit line 3 extends. The direction in which the word line 4 and the plate line 5 extend and the direction in which the bit line 3 extends may be referred to as a row direction and a column direction, respectively.

 In the memory cell array of the ferroelectric memory configured as described above, data is stored according to the polarization state of the ferroelectric film provided in the ferroelectric capacitor 1.

(First Embodiment) Next, a first embodiment of the present invention will be described. However, here, for convenience, the structure of each memory cell will be described together with its manufacturing method. 2A to 2G are cross-sectional views illustrating a method for manufacturing a ferroelectric memory (semiconductor device) according to the first embodiment of the present invention in the order of steps. 2A to 2G show a portion corresponding to two MOS transistors sharing one bit line (corresponding to bit line 3 in FIG. 1).

 In the first embodiment, first, as shown in FIG. 2A, a cell 12 is formed on the surface of a semiconductor substrate 11 such as a silicon substrate. Next, an element isolation region 13 is formed on the surface of the semiconductor substrate 11 by, for example, STI (Shallow Trench Isolation). Subsequently, the gate insulating film 14, the gate electrode 15, the cap film 16, the side wall 17, the source / drain diffusion layer 18 and the silicide layer 19 are formed on the surface of the well 12. A MOS transistor 20 is formed as a switching element. This 20 MOS transistor corresponds to the MOS transistor 2 in FIG. Note that two source / drain diffusion layers 18 are formed for each of the MOS transistors 20 for source and drain, and one of them is shared between the two MOS transistors 20.

Next, a silicon oxynitride film 21 is formed on the entire surface so as to cover the MOS transistor 20, and an SiO ₂ film 22 is formed on the entire surface as an interlayer insulating film. Polishing: The SiO ₂ film 22 is flattened by chemical mechanical polishing or the like. The silicon oxynitride film 21 is formed to prevent moisture deterioration of the gate insulating film 14 and the like when the SiO ₂ film 22 is formed.

Thereafter, as shown in FIG. 2B, a ferroelectric capacitor 23 having a planar structure is formed on the 310 ₂ film 22. The ferroelectric capacitor 23 includes a lower electrode 23a, a ferroelectric film 23b and an upper electrode 23c which are sequentially stacked. This ferroelectric capacitor 23 corresponds to the ferroelectric capacitor 1 in FIG.

Subsequently, as shown in FIG. 2C, an insulating film 24 having a surface whose inclination is gentler than that of the surface of the ferroelectric capacitor 23 is formed. As the insulating film 24, for example, by using T EOS (Tetra-Ethyl Ortho-Silicate) and O ₃ , an SiO ₂ film (N SG (Non-doped Silicate Glass) film), S P is added i 0 ₂ film (PSG (Phospho- Silicate Glass) film), S 0 ₂ film B及Pi P is added (BPSG (Boron Phospho- Silicate Glass (Film)), Fio-added SiO ₂ B (FSG (Fluoro-Silicate Glass) Film), etc. may be formed. Further, as the insulating film 24, for example, an NSG film, a PSG film, a BPSG film, a FSG film, a SiON, or the like may be formed by a high-density plasma (HDP: High Density Plasma) CVD method. Further, as the insulating film 2 4, by a plasma CVD method, S i 0 ₂ film may be formed S i ON film.

However, in the case of forming the insulating film 2 4 by atmospheric C VD method or a plasma C VD method, followed by applying plasma treatment using a plasma of N ₂ or N ₂ 0 in the insulating film 2 4, It is preferable to reduce the moisture in the insulating film 24 and to improve the film quality of the insulating film 24. The processing temperature at this time is preferably 200 to 450 ° C.

When the insulating film 24 is formed by the normal pressure CVD method, an SiO ₂ film or a SiO ON film is formed by plasma CVD at a thickness of about 30 OA to 100 A before the formation. Is preferred. This is to improve the coverage and prevent water from entering the ferroelectric capacitor 23.

 Further, the temperature of the semiconductor substrate 11 at the time of film formation is preferably in the range of 175 ° C to 350 ° C. This is because if the temperature is lower than 175 ° C, the coverage is reduced, and if the temperature is higher than 350 ° C, the already formed ferroelectric capacitor 23 may be broken. Because there is.

 Next, as shown in FIG. 2D, an alumina film (aluminum oxide film) 25 is formed on the insulating film 24 as a hydrogen diffusion preventing film. Since there is a steep portion on the side surface of the ferroelectric capacitor 23, if the alumina film is formed so as to directly cover the ferroelectric capacitor 23, the coverage may be insufficient. Since the insulating film 24 is formed and the surface thereof has a gentle slope, the low coverage of the alumina film 25 does not matter.

Next, as shown in FIG. 2E, an Si oxide film 26 is formed on the entire surface as an interlayer insulating film, and the Si oxide film 26 is planarized by CMP or the like. Thereafter, as shown in FIG. 2 F, a patterning and etching techniques, S i oxide film 2 6, the alumina film 2 5, the insulating film 2 4, S i 0 ₂ film 2 2 and the silicon San窒monolayer 2 1 Then, a contact hole reaching each silicide layer 19 is formed to open a plug contact portion. Then, a barrier metal film (not shown) is formed in each contact hole, and a W film is buried therein by, for example, a CVD method, and the W film is planarized by CMP to form a W plug 2. Form 7 and 28. The W plug 28 is a W plug connected to the silicide layer 19 shared by the two MOS transistors 20, and the W plug 27 is connected to the remaining silicide layer 19 W plug.

 Next, as shown in FIG. 2G, a contact hole reaching the upper electrode 23c is formed in the Si oxide film 26, the alumina film 25, and the insulating film 24 by using patterning and etching techniques. I do. Then, a wiring 29 connecting the upper electrode 23 c and the W plug 27 via a contact hole and a wiring 30 connecting to the W plug 28 are formed on the Si oxide film 26. .

 Prior to forming the wirings 29 and 30, annealing at 400 ° C. to 600 ° C. was applied to the ferroelectric capacitor 23 in an oxygen atmosphere, a nitrogen atmosphere, or an atmosphere of a mixed gas thereof. It is preferable to apply it. By performing such annealing, the deterioration of the characteristics of the ferroelectric capacitor 23 caused in the steps before the recovery is recovered.

Thereafter, formation of an interlayer insulating film, formation of contact plugs, formation of wiring of the second and subsequent layers from the bottom, and the like are further performed. Then, a passivation film composed of, for example, a silicon oxide film and a Si ₃ N ₄ film is formed to complete a ferroelectric memory having a ferroelectric capacitor. When forming the upper layer wiring, the wiring (not shown) connected to the lower electrode 23a is connected to the plate line (corresponding to the plate line 5 in FIG. 1). Is connected to the bit line (corresponding to bit line 3 in FIG. 1). The gate electrode 15 itself may be a word line, or the gate electrode 15 may be connected to a word line in an upper layer wiring.

According to the first embodiment, since coverage of the alumina film 25 does not matter, it is possible to more reliably prevent hydrogen from entering the ferroelectric capacitor 23. Can be. That is, the ferroelectric capacitor 23 can be protected more reliably. '

 In particular, when a silicon oxynitride film is formed as the insulating film 24 by a high-density plasma CVD method, the insulating film 24 also functions as a moisture intrusion preventing film, so that the ferroelectric capacitor 23 is protected. Be more robust.

 It is preferable that the thickness of the hydrogen diffusion preventing film is 10 nm to 100 nm. If the thickness is less than 100 ηιη, diffusion of hydrogen may not be sufficiently prevented, and if the thickness exceeds 100 nm, the etching of the hydrogen diffusion preventing film may occur. Is difficult.

 As the hydrogen diffusion preventing film, an A1 oxynitride film, a Ta oxide film, a Ti oxide film, or the like may be formed in addition to the alumina film.

 (Second embodiment)

 Next, a second embodiment of the present invention will be described. However, here, for the sake of convenience, the structure of the semiconductor device will be described together with its manufacturing method. 3A to 3E are cross-sectional views illustrating a method of manufacturing a ferroelectric memory (semiconductor device) according to the second embodiment of the present invention in the order of steps.

 In the second embodiment, semiconductor elements (not shown) and the like are formed on a semiconductor substrate (not shown) in the same manner as in the first embodiment, and then, as shown in FIG. An interlayer insulating film 31 is formed above.

 Next, on the interlayer insulating film 31, a raw material film for the lower electrode (lower electrode film), a ferroelectric film and a raw material film for the upper electrode (upper electrode film) are sequentially deposited. By patterning the body film, an upper electrode 34 and a ferroelectric capacitor insulating film 33 are formed. Next, a lower electrode 32 is formed by forming an alumina film 35 on the entire surface and patterning the alumina film 35 and the lower electrode film. Then, an alumina film 36 is formed on the entire surface. The thickness of the alumina films 35 and 36 is, for example, about 50 nm and about 20 nm, respectively.

Thereafter, an interlayer insulating film 37 is formed on the entire surface, and a contact hole is formed in the interlayer insulating film 37, the alumina film 36, and the interlayer insulating film 31, and a W plug 38 is embedded in the contact hole. Further, an interlayer insulating film 37, an alumina film 36, and an alumina film In 35, contact holes reaching the upper electrode 34 and the lower electrode 32, respectively, are formed. Then, on the interlayer insulating film 37, an A1 wiring 39 connected to the upper electrode 34, an A1 wiring 40 connected to the lower electrode 32, and an A1 wiring 41 connected to the W plug 38 are formed. . Subsequently, an alumina film 42 having a thickness of about 20 nm is formed on the entire surface, and an interlayer insulating film 43 is formed thereon.

 Next, a contact hole reaching the A1 wiring 41 and the like is formed on the interlayer insulating film 43 and the alumina film 42, and a W plug 44 is buried in the contact hole. A1 wiring 45 is formed on 43.

Thereafter, as shown in FIG. 3B, a SiO ₂ film 46 having a thickness of about 2.2 μπι is formed using TEOS as a raw material by a plasma CVD method. Then, CMP by S: 10 to ₂ film 46 1. polished and planarized to a thickness of about 0 m. Thereafter, by performing a plasma process using N ₂ 0 relative to S i 0 ₂ film 46, to reduce the moisture present in the S i 0 ₂ film 46.

Subsequently, as shown in FIG. 3C, a SiO ₂ film 47 having a thickness of about 10 O nm is formed on the entire surface by plasma CVD using TEOS as a raw material. Then, by subjecting the SiO ₂ film 47 to a plasma treatment using N ₂ 〇, the moisture present in the SiO ₂ film 47 is reduced. Next, S i 0 ₂ film 4 7 as a water intrusion preventing film is formed an alumina film 48 on the, by plasma CVD thereon, S i 0 ₂ film of about 100 nm thick TEOS as a raw material Form 49. Then, by performing plasma treatment had use of N ₂ 0 relative to S i 0 ₂ film 4 9, reduces the water present in the S I_〇 ₂ film 49. Then, a contact hole reaching the AI wiring 45 is formed, and a W plug 50 is buried in the contact hole. The thickness of the alumina film 48 is, for example, about 50 nm.

However, the 3 10 ₂ film 46 ^ [0? Formed by (high density plasma) CVD method, when the board I de in S 10 ₂ film 46 (to) has not occurred, after planarization by CMP, the N ₂ 0 plasma treatment as required Alternatively, the alumina film 48 may be formed directly on the SiO ₂ film 46 without forming the SiO ₂ film 47.

Next, as shown in FIG. 3D, an A1 wiring 51 is formed on the SiO ₂ film 49. At this time, as shown in Fig. 3E, wire bonding is performed on the same layer as A1 wiring 51. A pad 54 is also formed. That is, to form a A 1 film on a S i 0 ₂ film 4 9, which by patterning, to form the A 1 line 5 1 and the pad 5 4 from the same A 1 film.

Thereafter, as shown in FIGS. 3D and 3E, a high-density plasma SiO ₂ film 52 and a Si ₃ N ₄ film 53 are sequentially formed as a passivation film on the entire surface. Then, an opening exposing a part of the pad 54 is formed in the high-density plasma SiO ₂ film 52 and the Si ₃ N ₄ film 53.

 According to the second embodiment, it is possible to more reliably prevent moisture from entering a semiconductor element (such as a ferroelectric capacitor). In other words, when a moisture intrusion prevention film is formed so as to cover the ferroelectric capacitor wiring and the like, moisture enters the moisture intrusion prevention film and concentrates there. However, if a moisture intrusion prevention film (alumina film 48) is formed between the pad 54 and the uppermost wiring layer as in the present embodiment, moisture will It becomes more difficult to reach the element, and entry can be prevented more reliably.

 Further, the alumina film 48 used as the moisture intrusion prevention film in the second embodiment also has an effect of preventing diffusion of hydrogen. For this reason, it is possible to further suppress the hydrogen deterioration of the ferroelectric capacitor. Therefore, it is preferable to use, as the moisture intrusion prevention film, a film that not only prevents the ingress of moisture but also prevents the diffusion of hydrogen.

Here, the results of the moisture resistance test actually performed by the present inventors will be described. In this moisture resistance test, semiconductor devices manufactured under the conditions of the prescribed temperature and humidity were placed, and after 72 hours, 168 hours, and 336 hours, it was investigated whether or not they operated normally. . Tables 1 to 3 show the results. In Example 1, similarly to the second embodiment, an alumina film is formed between the uppermost wiring layer (the uppermost wiring layer) and the pad as a moisture intrusion prevention film. On the other hand, in Example 2, the alumina film as in Example 1 was not formed. The denominator of “impossible number” in Tables 1 to 3 is the total number of samples used for measurement, and the total number of numerators that did not work properly and were judged as failed. As shown in Tables 1 to 3, in Example 1 according to the second embodiment, the long-term moisture resistance was extremely excellent. After forming an insulating film by high-density plasma CVD so as to cover the uppermost wiring layer, a moisture intrusion prevention film may be formed thereon.

 The thickness of the moisture intrusion prevention film is preferably from 10 nm to 100 nm. If the thickness is less than 10 ηιη, it may not be possible to sufficiently prevent water from entering, and if the thickness exceeds 100 nm, it is difficult to etch the moisture intrusion prevention film. This is because

 Further, a silicon nitride film, a silicon oxynitride film, a tantalum oxide film, a titanium oxide film, or the like may be formed as the moisture intrusion prevention film in addition to the alumina film.

 Further, the pad is not limited to the one for wire bonding, and for example, a bump may be formed on the pad.

 In both the first and second embodiments, the method for forming the alumina film is not particularly limited. For example, an alumina film may be formed by physical vapor deposition or MOCVD, or an alumina film may be formed by hydrolysis represented by the following chemical formula.

 (Chemical formula)

2A 1 C 13+ 3H ₂ 0 → A l ₂ 0 ₃ + 6HC 1 †

In forming the passivation film, a silicon oxide film under the Si ₃ N ₄ film is formed by a high-density plasma CVD method, or two silicon oxide films are formed by a high-density plasma CVD method. Preferably, a hydrogen diffusion preventing film is formed between them, and a Si ₃ N ₄ film is formed on the upper silicon oxide film. Incidentally, the T EO S oxide film may be used as the silicon oxide film under the S i ₃ N ₄ film.

 Further, the wiring material is not limited to A1. For example, Cu wiring or A1-Cu alloy wiring may be used. In forming the contact plug, before the W plug is buried, the contact hole is formed with a sequentially formed TIN film and a Pari metal film made of a T i film or a Pari metal film made of only a T I N film. It is preferable to form them.

Further, as the ferroelectric capacitor of the capacitor insulating film (ferroelectric film), for example, PZT (P b (Z r, T i) 0 3) film or _{SBT (S r B i 2 T} a 2 0 9) film Etc. can be used. The method for forming these films is not particularly limited, either. For example, it can be formed by the MOCVD method.

 If the first embodiment and the second embodiment are applied at the same time, both effects can be obtained. Industrial applicability

As described above in detail, according to the present invention, the entry of hydrogen or moisture can be more reliably prevented by the hydrogen diffusion preventing film or the moisture entry preventing film. For this reason, the reliability and the yield and the productivity are improved.

table 1

表 3

Table 3

 3 36 hours later

 Impossible number Impossible ratio (%) Example 1 8/20 40.0 Comparative example 2 0/20 0.0

Claims

1. a semiconductor substrate;  A ferroelectric capacitor formed above the semiconductor substrate;  An insulating film that directly covers the ferroelectric capacitor, the surface of which has a gentler slope than the surface of the ferroelectric capacitor;  A hydrogen diffusion preventing film formed on the insulating film to prevent diffusion of hydrogen into the ferroelectric capacitor;  A semiconductor device comprising: of  2. The semiconductor device according to claim 1, wherein the insulating film is a film formed by a high-density plasma CVD method.  Enclosure 3. The insulating film includes a silicon oxide film to which impurities are not added, a silicon oxynitride film, a silicon oxide film to which fluorine is added, a silicon oxide film to which phosphorus is added, and a silicon oxide film to which boron and phosphorus are added. 2. The semiconductor device according to claim 1, wherein the semiconductor device is one kind of film selected from the group consisting of a silicon oxide film. 4. The hydrogen diffusion preventing film is a film selected from the group consisting of an aluminum oxide film, an aluminum oxynitride film, a tantalum oxide film, and a titanium oxide film. Semiconductor device. 5. The semiconductor device according to claim 1, wherein the thickness of the hydrogen diffusion preventing film is 100 nm to 100 nm. 6. A semiconductor element formed on the semiconductor substrate; A pad formed above the semiconductor substrate and connected to the semiconductor element; one or more wiring layers formed between the semiconductor element and the pad; and one or more wiring layers The uppermost wiring layer located at the top of 2. The semiconductor device according to claim 1, further comprising: a moisture intrusion prevention film formed between the semiconductor device and the semiconductor substrate, the moisture intrusion prevention film configured to prevent moisture from entering into a lower layer side of the semiconductor device. 7. The semiconductor device according to claim 6, wherein the moisture intrusion prevention film is one kind of film selected from the group consisting of an aluminum oxide film, a silicon nitride film, and a silicon oxynitride film. . 8. Semiconductor substrate,  A semiconductor element formed on the semiconductor substrate,  A pad formed above the semiconductor substrate and connected to the semiconductor element; one or more wiring layers formed between the semiconductor element and the pad; and one or more wiring layers And a moisture prevention film formed between the uppermost wiring layer located at the uppermost position and the pad, and for preventing moisture from entering the lower layer side. 9. The semiconductor device according to claim 8, further comprising an insulating film formed by high-density plasma CVD so as to cover the uppermost wiring layer. 10. The semiconductor device according to claim 8, wherein the moisture intrusion prevention film is one kind of film selected from the group consisting of an aluminum oxide film, a silicon nitride film, and a silicon oxynitride film. . 11. The semiconductor device according to claim 8, wherein a thickness of the moisture intrusion prevention film is 10 nm to 100 nm. 12. The semiconductor device according to claim 8, further comprising a ferroelectric capacitor formed in any layer between the semiconductor substrate and the uppermost wiring layer. Forming a ferroelectric capacitor above the semiconductor substrate; A step of directly covering the ferroelectric capacitor, and forming an insulating film whose surface slope is gentler than the surface slope of the ferroelectric capacitor;  Forming a hydrogen diffusion preventing film on the insulating film for preventing diffusion of hydrogen into the ferroelectric capacitor;  A method for manufacturing a semiconductor device, comprising: 14. The method according to claim 13, wherein the insulating film is formed by a high-density plasma CVD method. 15. The method for manufacturing a semiconductor device according to claim 14, wherein the temperature of the semiconductor substrate at the time of forming the insulating film is set to be in a range of 1750 to 350 ° C. 16. As the insulating film, a silicon oxide film to which no impurity is added, a silicon oxynitride film, a silicon oxide film to which fluorine is added, a silicon oxide film to which phosphorus is added, and boron and phosphorus are added. 14. The method for manufacturing a semiconductor device according to claim 13, wherein one kind of film selected from the group consisting of an added silicon oxide film is formed. 17. The hydrogen diffusion preventing film according to claim 13, wherein one kind of film selected from the group consisting of an aluminum oxide film, an aluminum oxynitride film, a tantalum oxide film, and a titanium oxide film is formed. The manufacturing method of the semiconductor device described in the above. 18. The method for manufacturing a semiconductor device according to claim 13, wherein the thickness of the hydrogen diffusion preventing film is set to 10 nm to 100 nm. 19. The method for manufacturing a semiconductor device according to claim 13, wherein the insulating film is formed by a normal pressure CVD method or a plasma CVD method using tetraethylorthosilicate as a raw material. 20. The semiconductor device according to claim 19, further comprising, after the step of forming the insulating film, a step of performing a plasma treatment on the insulating film using N ₂ or N ₂₀ plasma. Manufacturing method. 21. The method for manufacturing a semiconductor device according to claim 20, wherein in the step of performing the plasma processing, the temperature in the processing chamber is set to 200 ° C. to 450 ° C. 22. The method for manufacturing a semiconductor device according to claim 17, wherein the aluminum oxide film is formed by a physical vapor deposition method, a MOC VD method, or a hydrolysis method. 23. The method according to claim 22, wherein a silicon oxide film or a silicon oxynitride film is formed as the insulating film by a high-density plasma CVD method or a plasma CVD method. 24. The step of forming the insulating film includes:  Forming a silicon oxide film or a silicon oxynitride film by a plasma CVD method;  Forming a silicon oxide film to which impurities are not added using tetraethyl orthosilicate as a raw material by a normal pressure CVD method;  14. The method for manufacturing a semiconductor device according to claim 13, comprising: 25. a step of forming a semiconductor element on the semiconductor substrate before the step of forming the ferroelectric capacitor,  After the step of forming the hydrogen diffusion preventing film, Forming one or more wiring layers above the ferroelectric capacitor; and forming a wiring layer above the uppermost wiring layer positioned at the top of the one or more wiring layers, and Forming a moisture intrusion prevention film for preventing ingress of moisture; forming a pad connected to the semiconductor element above the moisture intrusion prevention film; 14. The method for manufacturing a semiconductor device according to claim 13, comprising: 26. The semiconductor according to claim 25, wherein one type of film selected from the group consisting of an aluminum oxide film, a silicon nitride film, and a silicon oxynitride film is formed as the moisture intrusion prevention film. Equipment manufacturing method. 27. After the step of forming the hydrogen diffusion preventing film,  Forming an interlayer insulating film on the hydrogen diffusion preventing film;  Flattening the interlayer insulating film;  Forming a contact hole reaching the part of the ferroelectric capacitor in the interlayer insulating film, the hydrogen diffusion preventing film and the insulating film;  Subjecting the ferroelectric capacitor to annealing at a temperature of 400 ° C. to 600 ° C. in an atmosphere containing at least one kind of gas selected from the group consisting of oxygen and nitrogen; Forming a wiring connected to the ferroelectric capacitor via a through hole;  14. The method for manufacturing a semiconductor device according to claim 13, comprising: 28. A step of forming a semiconductor element on a semiconductor substrate,  Forming one or more wiring layers above the semiconductor element;  Forming a moisture intrusion prevention film above the uppermost wiring layer positioned at the top of the one or more wiring layers to prevent moisture from entering the lower layer side; and Forming a pad connected to the semiconductor element above,  A method for manufacturing a semiconductor device, comprising: 29. The semiconductor device according to claim 28, further comprising a step of forming an insulating film covering the uppermost wiring layer by high-density plasma CVD before the step of forming the moisture intrusion prevention film. Manufacturing method. 30. The semiconductor device according to claim 28, wherein one type of film selected from the group consisting of an aluminum oxide film, a silicon nitride film, and a silicon oxynitride film is formed as the moisture intrusion prevention film. Manufacturing method. 31. The method for manufacturing a semiconductor device according to claim 28, wherein a thickness of the moisture intrusion prevention film is set to 10 nm to 100 nm. 32. The method according to claim 28, further comprising a step of forming an insulating film covering the uppermost wiring layer using tetraethyl orthosilicate as a raw material by a plasma CVD method before the step of forming the moisture intrusion prevention film. The manufacturing method of the semiconductor device described in the above. 3 3. Before the step of forming the moisture intrusion prevention film,  Forming a first insulating film covering the uppermost wiring layer using tetraethylorthosilicate as a raw material by a plasma CVD method;  Flattening the first insulating film; Performing a plasma treatment on the first insulating film using N ₂₀ plasma;  Forming a second insulating film on the first insulating film by plasma CVD using tetraethylorthosilicate as a raw material; Performing a plasma process using N ₂ O plasma on the second insulating film;  Has,  Before the step of forming the pad,  Forming a third insulating film on the moisture intrusion prevention film by plasma CVD using tetraethylorthosilicate as a raw material; Performing a plasma treatment using N ₂ O plasma on the third insulating film; 29. The method for manufacturing a semiconductor device according to claim 28, comprising: 34. A step of forming a ferroelectric capacitor above the semiconductor substrate in parallel with the step of forming one or more wiring layers above the semiconductor element. 13. The method for manufacturing a semiconductor device according to item 5.