KR20070081714A - Ferroelectric memory device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a ferroelectric memory device. The capacitor including the dielectric film formed of the ferroelectric material of the memory element has a form surrounded by the lower and upper diffusion barrier films. Accordingly, it is possible to provide a ferroelectric memory device capable of improving performance by preventing the capacitor from deteriorating.

Description

Ferroelectric random access memory device and method for fabricating the same

1A to 1F are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a ferroelectric memory device and a manufacturing method thereof.

In an integrated circuit (IC) device, data is stored in the form of a charge in a memory cell capacitor. This stored charge is lost through several paths over time. Therefore, there is a need for a refresh operation to periodically refresh information. The interval between such refresh operations is called refresh time. This refresh time can be improved by increasing the capacitance of the capacitor to increase the amount of charge stored by the memory cell capacitor.

One of the widely used methods to increase the capacity of the capacitor is to use a ferroelectric material having a high dielectric constant as the dielectric film of the capacitor. The ferroelectric remains after the externally formed electric field has been removed from the external polarization (P _r : remanant polarization), which is part of spontaneous polarization (P _s ), and the direction of the spontaneous polarization changes the direction of the electric field. It is the material which can be changed by making it.

This property of ferroelectrics coincides with the basic concept of binary memory, which is the basis of widely used digital memory devices. Therefore, PZT (Pb (Zr, Ti) O ₃ ) and SBT (SrBi ₂ Ta Research of memory devices using ferroelectrics, such as ₂ O ₉ ), is being conducted.

The biggest obstacle to the realization of this FRAM (Ferroelectric Random Access Memory) is that the ferroelectric properties of the PZT capacitors degrade during the integration process. That is, the spontaneous polarization decreases in the interlayer insulating film, the intermetallic insulating film, or the passivation process. For example, an interlayer insulating film is formed on all surfaces of a capacitor including a ferroelectric film as a dielectric film for the purpose of insulating the metal wiring and the like formed in a subsequent step. However, when this interlayer insulating film is brought into direct contact with the ferroelectric film, the characteristics of the capacitor deteriorate due to the reaction between the two. In addition, cracks occur in the insulating film in contact with the electrode material. In order to prevent this problem and to prevent volatilization and diffusion of materials forming the ferroelectric film in a subsequent process, or hydrogen (H) to penetrate into the ferroelectric film, a titanium oxide film (TiO), which is a metal oxide film, is formed between the ferroelectric capacitor and the interlayer insulating film. ₂ ) or an encapsulating barrier layer (EBL) such as an aluminum oxide film (Al ₂ O ₃ ) is formed.

The ferroelectric memory device as described above improves the performance of the semiconductor device, and the smaller the size, the greater the influence of hydrogen on the capacitor. Accordingly, a phenomenon in which the capacitor deteriorates even with a small amount of hydrogen occurs. The structure of the ferroelectric memory device having a diffusion barrier covering the capacitor can exert an effect on the hydrogen coming from the top to the bottom, but has a problem of being vulnerable to the hydrogen rising from the bottom to the top through any path.

An object of the present invention is to provide a ferroelectric memory device capable of preventing deterioration of a capacitor including a dielectric film formed of a ferroelectric material and a method of manufacturing the same.

The present invention provides a method of manufacturing a ferroelectric memory device. According to this method, first, a first interlayer insulating film and a lower diffusion barrier film are formed on a semiconductor substrate. The lower diffusion barrier layer and the first interlayer dielectric layer are patterned to form contact holes that expose a predetermined region of the semiconductor substrate, and then fill contact holes to form contact plugs. A capacitor is formed in a predetermined region of the lower diffusion barrier layer including the contact plug. After forming the upper diffusion barrier layer covering the semiconductor substrate including the capacitor, a second interlayer insulating layer is formed on the upper diffusion barrier layer, thereby manufacturing a ferroelectric memory device. The capacitor is characterized by being surrounded by the lower and upper diffusion barriers.

The first and second interlayer insulating films may be formed of silicon oxide.

The lower and upper diffusion barrier layers may be formed of a material including aluminum oxide, silicon oxynitride, or silicon nitride.

The method may further include forming an additional interlayer insulating layer on the lower diffusion barrier. The interlayer insulating film may be formed of silicon oxide.

The dielectric film of the capacitor may be formed of a ferroelectric material. The ferroelectric material may be PZT.

The upper diffusion barrier layer may be formed to overlap the lower diffusion barrier layer in a region where the capacitor is not formed.

The present invention also provides a ferroelectric memory device. The memory device includes a semiconductor substrate, a lower portion including a contact plug and a contact plug connected to a predetermined region of the semiconductor substrate through a first interlayer insulating layer and a lower diffusion barrier, a lower diffusion barrier, and a first interlayer insulation layer formed sequentially on the semiconductor substrate. A capacitor formed in a predetermined region of the diffusion barrier layer, an upper diffusion barrier layer covering the semiconductor substrate including the capacitor, and a second interlayer insulating layer formed on the upper diffusion barrier layer, wherein the capacitor is surrounded by the lower and upper diffusion barrier layers. do.

The first and second interlayer insulating films may be formed of a silicon oxide film.

The lower and upper diffusion barrier layers may be formed of a single layer or multiple layers including an aluminum oxide layer, a silicon oxynitride layer, or a silicon nitride layer.

The interlayer insulating layer formed on the lower diffusion barrier layer may be further included. The interlayer insulating film may be made of a silicon oxide film.

The dielectric film of the capacitor may be made of ferroelectric material. The ferroelectric material may be PZT.

The upper diffusion barrier layer may be in contact with the lower diffusion barrier layer in a region where the capacitor is not formed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art. In the drawings, the thicknesses of films and regions are exaggerated for clarity. Also, if it is mentioned that the film is on another film or substrate, it may be formed directly on the other film or substrate or a third film may be interposed therebetween.

1A to 1F are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present invention.

Referring to FIG. 1A, a device isolation layer 112 is formed on a semiconductor substrate 110 using a general device isolation process.

A general metal-oxide semiconductor (MOS) transistor manufacturing process is performed to form a gate oxide film 114, a gate electrode 116, and an impurity region (source / drain regions, 118s / 118d) on the semiconductor substrate 110. . The gate oxide film 114 may be formed of a thermal oxide film. The gate electrode 116 may be formed of polysilicon. The impurity regions 118s and 118d may be formed by an ion implantation process.

The first interlayer insulating layer 120 covering the entire surface of the semiconductor substrate 110 including the MOS transistor is formed. The interlayer insulating layer 120 may be formed of a silicon oxide film deposited using a chemical vapor deposition (CVD) method, and preferably, plasma enhanced CVD (PE-CVD). It may be formed of a Teos (TetraEthly OrthoSilicate) film deposited by using a) method. The first interlayer insulating layer 120 may be formed to have a thickness of about 2,000 μs.

Referring to FIG. 1B, the first interlayer insulating layer 120 forms a lower diffusion barrier layer 122 and a second interlayer insulating layer 124 on the first interlayer insulating layer 120. The lower diffusion barrier layer 122 may be formed of a material including aluminum oxide, silicon oxynitride (SiON), or silicon nitride (SiN) as a material that may serve as a barrier to PZT diffusion as well as a barrier property to hydrogen. . The lower diffusion barrier 122 may be formed of a single layer or multiple layers of each of these materials. Preferably, aluminum oxide deposited by atomic layer deposition (ALD) may be used. The lower diffusion barrier 122 may be formed to have a thickness of about 50 ~ 200Å. The thickness of the diffusion barrier can be selected from a minimum thickness that can serve as a barrier to a range that does not interfere with subsequent processes, and a thicker thickness within this range is better. The second interlayer insulating film 124 may be a silicon oxide film formed by the same method as the first interlayer insulating film 120. The second interlayer insulating layer 124 may be formed to have a thickness of about 1,300 Å.

Referring to FIG. 1C, a contact hole exposing a predetermined region of the drain region 118d by etching the second interlayer insulating layer 124, the lower diffusion barrier 122, and the first interlayer insulating layer 120 by a photolithography process. hole, 125). A contact plug 126 is formed to fill the contact hole 125. The contact plug 126 may be formed of, for example, tungsten (W) deposited using a pulsed nucleation layer (PNL) formation method.

Prevents diffusion at the interface between the contact plug 126 and the first and second interlayer insulating films 120 and 124 and the lower diffusion barrier film 122 in contact with each other in a subsequent heat treatment process before the contact plug 126 is formed. In order to do this, a barrier metal film (not shown) may be formed. The barrier metal film may be formed as a double film in which titanium (Ti) and titanium nitride (TiN) are sequentially stacked.

1D and 1E, the capacitor 130 is formed in a predetermined region of the second interlayer insulating layer 124 including the contact plug 126. The capacitor 130 may be formed of a lower electrode, a dielectric layer, and an upper electrode. The dielectric film may be formed of a ferroelectric material. The ferroelectric material may be PZT.

In the etching process for forming the capacitor 130, the second interlayer insulating layer 124 except for the portion where the capacitor 130 is formed may have a recess of about 200˜300 μs (A of FIG. 1E). Accordingly, an upper surface of the lower diffusion barrier 122 is exposed or a portion of the second interlayer insulating layer 124 remains on the lower diffusion barrier 122 according to an etching process margin for forming the capacitor 130. can do.

After the capacitor 130 is formed, the upper diffusion barrier 132 is formed on the second interlayer insulating layer 124 including the capacitor 130. The upper diffusion barrier 132 may be formed of a material including aluminum oxide, silicon oxynitride, or silicon nitride in the same manner as the lower diffusion barrier 122. The upper diffusion barrier 132 may be formed of a single layer or multiple layers of each of these materials. Preferably, aluminum oxide deposited by atomic layer deposition may be used. The upper diffusion barrier 132 may be formed to have a thickness of about 50 ~ 200Å.

The upper diffusion barrier layer 132 covers the recess A that may occur in the second interlayer insulating layer 124 in the portion where the capacitor is not formed. Accordingly, the upper diffusion barrier 132 may be formed in contact with the lower diffusion barrier 122, or may be interposed between the second interlayer insulating layer 124.

Referring to FIG. 1F, a third interlayer insulating layer 134 is formed on the upper diffusion barrier 132. The third interlayer insulating layer 134 may be formed of a silicon oxide film deposited using a chemical vapor deposition method, and preferably, may be formed of a theos film deposited using a plasma enhanced chemical vapor deposition method.

By the method according to the embodiment of the present invention, a capacitor including a dielectric film formed of a ferroelectric material of the ferroelectric memory device may be surrounded by a diffusion barrier. Accordingly, it is possible to provide a ferroelectric memory device capable of preventing the capacitor from deteriorating due to diffusion or reaction of a ferroelectric material and a method of manufacturing the same.

As described above, according to the present invention, by surrounding a capacitor including a dielectric film formed of a ferroelectric material with a diffusion barrier, a ferroelectric memory device capable of preventing a capacitor from deteriorating and improving its performance and a method of manufacturing the same are provided. can do.

Claims (16)

Forming a first interlayer insulating film and a lower diffusion barrier film on the semiconductor substrate; Patterning the lower diffusion barrier layer and the first interlayer insulating layer to form a contact hole exposing a predetermined region of the semiconductor substrate; Filling the contact hole to form a contact plug; Forming a capacitor in a predetermined region of the lower diffusion barrier layer including the contact plug; Forming an upper diffusion barrier layer covering the semiconductor substrate including the capacitor; And And forming a second interlayer insulating film on the upper diffusion barrier, wherein the capacitor is surrounded by the lower and upper diffusion barriers. The method of claim 1, And the first and second interlayer insulating films are formed of silicon oxide. The method of claim 1, The lower and upper diffusion barrier layers are formed of a material including aluminum oxide, silicon oxynitride, or silicon nitride. The method of claim 1, And forming an additional interlayer insulating film on the lower diffusion barrier layer. The method of claim 4, wherein And said interlayer insulating film is formed of silicon oxide. The method of claim 1, And a dielectric layer of the capacitor is formed of a ferroelectric material. The method of claim 6, The ferroelectric material is a method of manufacturing a ferroelectric memory device, characterized in that the PZT. The method of claim 1, And the upper diffusion barrier layer is formed to be in contact with the lower diffusion barrier layer in a region where the capacitor is not formed. Semiconductor substrates; A first interlayer insulating film and a lower diffusion barrier film sequentially formed on the semiconductor substrate; A contact plug connected to a predetermined region of the semiconductor substrate through the lower diffusion barrier layer and the first interlayer insulating layer; A capacitor formed in a predetermined region of the lower diffusion barrier layer including the contact plug; An upper diffusion barrier layer covering the semiconductor substrate including the capacitor; And And a second interlayer insulating film formed on the upper diffusion barrier, wherein the capacitor is surrounded by the lower and upper diffusion barriers. The method of claim 9, And the first and second interlayer insulating films are formed of a silicon oxide film. The method of claim 9, The lower and upper diffusion barrier layers are formed of a single layer or multiple layers including an aluminum oxide layer, a silicon oxynitride layer, or a silicon nitride layer. The method of claim 9, And an interlayer insulating layer formed on the lower diffusion barrier layer. The method of claim 12, And the interlayer insulating film is formed of a silicon oxide film. The method of claim 9, A ferroelectric memory device, characterized in that the dielectric film of the capacitor is made of a ferroelectric material. The method of claim 14, And the ferroelectric material is PZT. The method of claim 9, And the upper diffusion barrier layer is in contact with the lower diffusion barrier layer in a region where the capacitor is not formed.

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