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WO2004064150A1 - Procede de fabrication d'une plaquette de montage de composants electroniques et plaquette de montage electronique fabriquee conformement a ce procede - Google Patents

Procede de fabrication d'une plaquette de montage de composants electroniques et plaquette de montage electronique fabriquee conformement a ce procede Download PDF

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Publication number
WO2004064150A1
WO2004064150A1 PCT/JP2003/000326 JP0300326W WO2004064150A1 WO 2004064150 A1 WO2004064150 A1 WO 2004064150A1 JP 0300326 W JP0300326 W JP 0300326W WO 2004064150 A1 WO2004064150 A1 WO 2004064150A1
Authority
WO
WIPO (PCT)
Prior art keywords
build
electronic component
support substrate
hole
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2003/000326
Other languages
English (en)
Japanese (ja)
Inventor
Motoaki Tani
Yasuo Yamagishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2003/000326 priority Critical patent/WO2004064150A1/fr
Priority to JP2004566275A priority patent/JP3999784B2/ja
Priority to TW092101273A priority patent/TW566065B/zh
Publication of WO2004064150A1 publication Critical patent/WO2004064150A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H10P72/74—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H10W70/05—
    • H10W70/635—
    • H10W70/685—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0376—Etching temporary metallic carrier substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1536—Temporarily stacked PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H10P72/7424—
    • H10W70/682—
    • H10W72/07251—
    • H10W72/20—
    • H10W74/012—
    • H10W74/15—

Definitions

  • the present invention relates to a method of manufacturing an electronic component mounting board used in a circuit system of an electric / electronic device, and an electronic component mounting board manufactured by the method.
  • a method for forming a multilayer wiring structure in a multilayer wiring board there is a build-up method.
  • the formation of an insulating layer and the formation of a wiring pattern on the insulating layer are sequentially repeated on the core substrate, and the wiring is multilayered. Specifically, first, a build-up insulating layer made of an epoxy resin is laminated on a glass epoxy substrate or a BT substrate serving as a core substrate. Next, a via hole is formed in the insulating layer.
  • a method of forming a via hole there is a method of forming a hole in the insulating layer by photolithography using a photosensitive resin as a material of the insulating layer, or a method of forming a hole in the insulating layer by irradiating a laser. Adopted. After forming a via hole in the insulating layer, a conductive material is formed on the insulating layer by electroless plating or electric plating. At this time, a via is formed in the via hole by the conductive material. Next, a wiring pattern is formed by etching the conductive material formed on the insulating layer.
  • transmission characteristics in a high-frequency band are a problem in a multilayer wiring board having a multilayer wiring structure formed by a build-up method.
  • the wiring resistance that is, inductance
  • signal noise is more likely to occur.
  • the IC chip is built into the core substrate so that the electrodes of the IC chip are exposed on the front side of the core substrate.
  • Techniques for forming a multilayer wiring structure on the surface of a core substrate are known (for example, see the following references 1 and 2).
  • Another technique for reducing the wiring resistance by shortening the distance between the IC chip and the capacitor is to form a multilayer wiring structure on the surface of a metal support substrate by a build-up method. After mounting the IC chip on the surface of the outermost layer of the structure and subjecting the reinforcing plate to processing, the entire support substrate is removed, thereby forming solder bumps on the back surface of the exposed insulating layer.
  • Multi-Layer Thin -Film (MLTF) Packaging Technology is known. (For example, see Reference 3 below.)
  • Literature 1 Japanese Unexamined Patent Application Publication No. 2000-3502 174.
  • Literature 2 R. Emery, S. Towle, H. Braunisch, C. Hu, G. Raiser, and G. J.
  • the technologies disclosed in the above-mentioned references 1 and 2 form a multilayer wiring structure by a build-up method after the IC chip is fixed to a supporting substrate in advance, so that it is difficult to align the IC chip with the multilayer wiring structure. It is.
  • the multilayer wiring structure is formed after the IC chip is fixed to the supporting substrate in advance, it is very difficult to reuse the IC chip if a defect occurs in the multilayer wiring structure. In other words, the yield of the multilayer wiring structure is 1
  • an object of the present invention is to provide a method of manufacturing an electronic component mounting board which is excellent in alignment, practicality, and work efficiency while reducing the inductance of the electronic component mounting board. It is in.
  • Another object of the present invention is to provide a chip component mounting board manufactured by such a method.
  • the method for manufacturing an electronic component mounting board includes: a build-up laminating step of alternately forming a build-up insulating layer and a build-up wiring pattern on a surface of a metal support board; A hole forming step of forming a through hole at a position where the electronic component is mounted on the support substrate to expose a build-up insulating layer of the innermost layer; and a build-up of the innermost layer via the through hole of the support substrate. And mounting the electronic component on the up-insulating layer.
  • the electronic components can be mounted after the build-up laminate is formed on the surface of the support substrate. Therefore, build-up laminates Positioning when mounting electronic components can be performed relatively easily. Also, since the electronic components can be mounted after the build-up laminate is formed, the electronic components can be mounted after confirming that the build-up laminate has been properly formed. It is practical without waste. Further, since the support substrate removes only the mounting area for electronic components, the remaining portion of the support substrate plays a role similar to that of the stiffener. Therefore, it has sufficient rigidity for mounting and other handling. Therefore, there is no need to provide a separate step for imparting rigidity, and work efficiency is excellent.
  • the method further includes a sealing step of sealing a gap generated around the electronic component in the through hole after the mounting step with an insulating resin.
  • the method further includes a temporary bonding step of temporarily bonding the back surfaces of the two support substrates before the build-up lamination step, and separating the two support substrates after the build-up lamination step and before the hole forming step.
  • the build-up laminating step is performed on the surface of each support substrate.
  • the temporary bonding step is performed by sandwiching the two support substrates between two resin sheets having a size protruding from the outer peripheral portion of each support substrate, and vacuum laminating the two resin sheets under heating.
  • the two supporting substrates can maintain the joined state without using an adhesive or the like, and for example, only by cutting the resin sheet protruding from the outer peripheral portion, the two supporting substrates are cut. Support substrate Can be easily separated. Also, a part of the resin sheet can be used as the innermost layer of the build-up insulating layer, which is excellent in work efficiency.
  • the method further includes a plating step of forming a metal plating film on at least the protruding portions of the resin sheets after the temporary joining step.
  • a plating step of forming a metal plating film on at least the protruding portions of the resin sheets after the temporary joining step even when a surface roughening process is performed when forming a build-up wiring pattern on a build-up insulating layer in a build-up laminating step, the resin sheet of the protruding portion is surfaced by the metal plating film. Unaffected by coarse treatment. Therefore, even when a multilayer is formed in the build-up lamination process, the resin sheet at the protruding portion is not damaged, and the temporary bonding state of the two support substrates can be more stably maintained.
  • the metal plating film is formed simultaneously with a wiring pattern for the innermost build-up insulating layer. According to such a manufacturing method, the metal plating film can be formed with higher working efficiency.
  • the method further includes a film forming step of forming a protective film of a material different from the metal plating film on the metal plating film after the plating step.
  • a film forming step of forming a protective film of a material different from the metal plating film on the metal plating film after the plating step it is possible to prevent the metal plating film from being removed by, for example, etching performed when forming a wiring pattern using a subtractive method. This can prevent the judging sheet at the protruding portion from being damaged, and can more stably maintain the temporary joining state of the two support substrates.
  • the electronic component further includes a polishing step of polishing a back surface of the innermost build-up insulating layer on which the build-up wiring pattern is not formed and / or a back surface of the support substrate.
  • a polishing step of polishing a back surface of the innermost build-up insulating layer on which the build-up wiring pattern is not formed and / or a back surface of the support substrate According to such a manufacturing method, it is possible to reduce the thickness and size of the entire electronic component mounting machine plate.
  • the electronic component mounting board provided by the second aspect of the present invention is a build-up laminate formed by alternately forming a metal support board and a build-up insulating layer and a build-up wiring pattern on the surface of the support board.
  • An electronic component mounting board comprising: a body; and an electronic component mounted on the build-up laminate, wherein the support substrate has a through hole at a position where the electronic component is mounted;
  • the electronic component is connected to a build-up wiring path in the innermost build-up insulating layer through the through hole of the support substrate. It is characterized in that it is mounted on the back side where turns are not formed.
  • a gap generated around the electronic component in the through hole is sealed with an insulating resin.
  • the electronic component is an IC chip, and a capacitor is mounted on a surface of the outermost build-up insulating layer on which the build-up wiring pattern is formed.
  • the wiring distance between the IC chip and the capacitor can be reduced. Therefore, the inductance can be reduced, and the generation of noise can be suppressed.
  • the metal constituting the supporting substrate has a coefficient of thermal expansion of 1 ppm / K to 20 ppmZK in a temperature range of 165 ° C to 280 ° C.
  • the metal is preferably selected from the group consisting of 42 alloy, molybdenum, kovar, invar, 42 invar, titanium, copper / invar z copper clad material, stainless steel, copper, iron, nickel, and aluminum.
  • FIG. 1 is a sectional view of a chip mounting board according to the present invention.
  • 2a to 2n are cross-sectional views showing a series of steps of a method for manufacturing the chip mounting board.
  • FIG. 3 is a cross-sectional view illustrating a modification of one step of the manufacturing method.
  • FIG. 4 is a cross-sectional view illustrating another modified example of one step of the above manufacturing method.
  • FIG. 1 is a cross-sectional view of a chip mounting board XI according to an embodiment of the present invention.
  • the chip mounting substrate XI includes a support substrate 1 having a front surface 1a and a back surface 1b, a build-up laminate 2 formed on a front surface la, an IC chip 3, and a capacitor 4.
  • the support substrate 1 has a through hole 11 for accommodating the IC chip 3.
  • the through hole 11 is formed from the rear surface 1 b to the front surface 1 a of the support substrate 1 according to the shape of the IC chip 3 to be mounted.
  • the overall shape of the support substrate 1 is, for example, plate-like, and its thickness is preferably approximately the same as the thickness of the IC chip 3. However, the shape and thickness are limited to these. I can't.
  • the support substrate 1 is made of metal.
  • the metal preferably has a coefficient of thermal expansion in the temperature range from 16 ° C. to 280 ° C. from 1 ppm / K to 20 ppm / K.
  • Materials constituting this metal include 42 alloy, molybdenum, copal, Invar, 42 invar, titanium, copper / invar Z copper clad material, stainless steel, copper, iron, nickel, aluminum and the like.
  • the build-up laminate 2 includes insulating layers 21a to 21f, wiring patterns 22a to 22f, vias 23, and overcoat layers 24.
  • the insulating layer 21a is laminated and formed so as to be joined to the surface 1a of the support substrate 1 at the back surface 21a, and the wiring pattern is formed on the surface 21a of the insulating layer 21a.
  • 2 2a is formed.
  • the insulating layer 2 1b is formed so as to be bonded to the surface 2 12a of the insulating layer 21a at the back surface 2 lib, and is formed on the surface 2 1 2b of the insulating layer 2 1b.
  • insulating layers 21c to 21f are sequentially formed.
  • the number of layers of the build-up laminate 2 is not limited to the above, and may be arbitrarily determined as needed.
  • thermosetting resin examples include a polyimide resin, an epoxy resin, a bismaleimide resin, a maleimide resin, a cyanate resin, a thermosetting polyphenylene ether resin, a polyphenylene oxide resin, a fluorine-containing resin, and a wholly aromatic type.
  • thermosetting resin examples include polyester-based liquid crystal polymer resins. Note that the constituent materials of the insulating layers 21a to 21f are not limited to those described above.
  • the wiring patterns 22a to 22f are formed on the insulating layers 21a to 21f, respectively.
  • the wiring patterns between the layers (for example, wiring pattern 22 a and wiring pattern 22 b) are electrically connected by vias 23.
  • the vias 23 are the same as the wiring patterns 22 a to 22 f by the method described later. Sometimes formed.
  • Overcoat layer 2 4 is provided to protect the outermost insulating layer 2 1 f on the patterned wiring pattern 2 2 f, opening a part of the wiring pattern 2 2 f is provided in the Hare by faces It has 24 a.
  • the resin listed above as a constituent material of the insulating layers 21a to 21f, or an epoxy acrylate resin used for a general solder resist is used. Can be used.
  • the IC chip 3 has a plurality of ball electrodes 31, and the innermost insulating layer 21 a from the back surface 1 b side of the support substrate 1 through the through hole 11. Mounted on the back 2 1 1a.
  • the main part of the IC chip 3 is made of a general semiconductor element material such as silicon, and has a coefficient of thermal expansion of 3.0 to 3.5 ppm / K.
  • the plurality of ball electrodes 31 are arranged in a grid array on the surface 3a of the IC chip 3 to form a ball grid array.
  • the ball electrode 31 is made of gold or solder having a predetermined composition.
  • a gap formed around the IC chip 3 in the through hole 11 is resin-sealed with an insulating resin to form a resin-sealed portion 32.
  • the insulating resin used for the resin sealing include an epoxy resin, a polyimide resin, and an isocyanate resin.
  • the capacitor 4 has a plurality of electrode portions 41, and the outermost layer of the outermost layer is formed from the surface 24 side of the overcoat layer 24 through the opening portion 24a. It is mounted on the surface 2 1 2 f of the insulating layer 2 1 f.
  • the number and capacity of the capacitors 4 may be arbitrarily determined as necessary.
  • the surfaces 1a and 1a 'of the two supporting substrates 1 and 1 are degreased and acid-treated and surface-roughened. (For example, in the case of a support substrate made of copper, CZ treatment is performed), and the two support substrates 1 and 1 are stacked so that the back surfaces 1 b and 1 b ′ face each other. Is composed.
  • each support substrate 1, 1 is made of insulating resin.
  • the laminated supporting substrate 10 is sandwiched between two insulating sheets 20 and 20 having a size protruding from the portions lc and 1c ', and vacuum lamination is performed at a predetermined temperature and a predetermined time.
  • the two support substrates 1 and 1 ′ can maintain a stacked state.
  • the insulating resin constituting the insulating sheets 20 and 20 ' include the same materials as those of the insulating layers 21a to 21f described above. Therefore, the portion of the insulating sheets 20 and 20 'that covers the support substrates 1 and 1 functions as the innermost insulating layers 21a and 21a'.
  • FIG. 2B shows a state in which the support substrates 1 and 1 ′ corresponding to one chip mounting substrate XI are vacuum-laminated.
  • a support substrate having a size corresponding to the substrate may be subjected to vacuum lamination, and then divided into a plurality of chip mounting substrates after performing the steps described below.
  • FIG. 2C is an enlarged view of a main part of the laminated support substrate 10 on which the insulating layers 21a and 21a 'are formed.
  • a via hole 23a is formed at a predetermined portion of the insulating layer 21a, and then the resin residue inside the via hole 23a is removed, and the inner wall surface of the via hole 23a and the insulation are removed. Desmearing is performed to roughen the surface 211b of the layer 21a.
  • a carbon dioxide laser, an excimer laser, a UV-YAG laser, or the like can be used as a means for forming the via hole 23a. Note that the steps shown in FIGS. 2c to 2h are the same for both support substrates 1, 1, so that only one support substrate 1 is shown.
  • an electroless nickel plating layer 22a having a thickness of 0.5 to 2 / im is formed at the bottom of the via hole 23a by an electroless nickel plating method. Then, the thickness of 0.1 to 0 is applied to the surface 21b of the insulating layer 21a, the inner wall surface of the via hole 23a, and the upper surface of the electroless nickel plating layer 21a by the electroless copper plating method. .5 Electroless copper plating layer 2 2 2a is formed.
  • the electroless copper plating layer 222 a serves as a seed layer that functions as a current-carrying layer in an electric plating process in a later step.
  • a known method can be adopted as a series of processes in each electroless plating method.
  • a resist pattern 25 is formed on the electroless copper plating layer 222a.
  • dry film layer on electroless copper plating layer 22a A resist pattern 25 is formed by laminating a distant and patterning the dry film resist by an exposure process and a development process corresponding to a desired wiring pattern.
  • an electroless copper plating process is performed using the electroless copper plating layer 222a as a current-carrying layer.
  • an electromechanical layer 223a having a thickness of 10 to 30 ⁇ is deposited and grown on the non-mask region of the resist pattern 25.
  • the electrolytic copper plating method for example, a known method using an acidic copper sulfate plating solution can be employed.
  • the resist pattern 25 is peeled off.
  • a sodium hydroxide aqueous solution or an organic amine-based aqueous solution can be used as the stripping solution.
  • the electroless copper plating layer 222a that is not covered with the electrolytic copper plating layer 222a is removed. Specifically, the electroless copper plating layer 222a is etched away using, for example, a mixed aqueous solution of hydrogen peroxide and sulfuric acid, or an aqueous cupric chloride solution.
  • the etchant acts in the same manner on the exposed portion of the electroless copper plating layer 222 a and the electroless copper plating layer 222 a, but as described above, the electroless copper plating layer 222 a Is thinner than that of the electroplated copper plating layer 2 23 a, only the exposed portions of the electroless copper plating layer 22 2 a disappear first. As a result, a wiring pattern 2 2 a having an electroless copper plating layer 2 2 2 a and an electric copper plating layer 2 2 3 a is formed on the surface 2 1 1 b of the insulating layer 2 1 a. .
  • the series of steps shown in FIGS. 2c to 2h is repeated a predetermined number of times (for example, six times).
  • a predetermined number of times for example, six times.
  • the six-layer wiring patterns 22a to 22f electrically connected to each other via the vias 23 and the six insulating layers 21 a to 21 f are formed.
  • the surfaces thereof are also electrically connected to each other through vias 23 '.
  • Six wiring patterns 22a and six insulating layers 21a are formed.
  • the electroless nickel plating layer may be formed only on the innermost insulating layers 21a and 21a '.
  • a solder resist is printed on the outermost insulating layers 2lf and 21f, and is exposed, developed, and heat-cured.
  • the overcoat layers 24, 24 having the openings 24a, 24a are formed.
  • the portions of the wiring patterns 22 f and 22 f ′ exposed by the openings 24 a and 24 a ′ are formed on the wiring patterns 22 f and 22 f by electroless nickel plating.
  • An electroless nickel plating layer (not shown) having a thickness of 0.5 to 2 m is formed.
  • the portions protruding from the supporting substrate 1, 1 that are not used as the insulating layers 21a, 21a 'in the insulating sheets 20, 20' that is, the edge 20a). , 20 a ').
  • the laminated state of the laminated supporting substrate 10 is released, and the multilayer wiring substrate Y1, as two intermediate products, is obtained.
  • the removal of the edges 20a, 20a 'by cutting may be accompanied by cutting of a part of the supporting substrates 1, 1'.
  • an etching pattern 26 is formed on the back surface 1b of the support substrate 1, as shown in FIG. 2k. Specifically, by laminating a dry film resist on the back surface 1b and performing exposure processing and development processing corresponding to a desired etching pattern, the dry film resist is patterned by etching. A pattern 26 is formed.
  • a through hole 11 is formed in the support substrate 1 by etching. Specifically, the support substrate 1 is removed using an etchant that does not dissolve an epoxy resin such as an aqueous cupric chloride solution or a mixed aqueous solution of hydrogen peroxide and sulfuric acid. As a result, a through hole 11 is formed in the support substrate 1.
  • the via 23 is an electroless nickel plating layer 22 1 a (see FIG. 2 h) provided at the bottom of the via hole 23 a (see FIG. 2 h). The via 23 is not etched.
  • the etching pattern 26 is peeled off.
  • an aqueous solution of sodium hydroxide or an aqueous solution of an organic amine can be used.
  • an electroless gold plating layer having a thickness of 1 to 5 ⁇ is formed on the electroless nickel plating layer 22 a exposed through the through hole 11 by an electroless gold plating method. I do.
  • a known method is used as a series of processes in the electroless gold plating method. Can be adopted.
  • the back surface S 1 of the support substrate 1 is connected to the ball electrode 31 of the IC chip 3 and the via 23 via an electroless gold plating layer (not shown).
  • the IC chip 3 is mounted on the back surface 211 a of the innermost insulating layer 21 a via the through hole 11 from the b side.
  • an insulating resin is injected into a gap formed between the through hole 11 and the IC chip 3 to form an insulating sealing portion 32. Seal.
  • the capacitor 4 is mounted on the overcoat layer 24, as also shown in FIG. At this time, the electrode portion 41 of the capacitor 4 is electrically connected to the outermost wiring pattern 22 f via the opening 24 a of the overcoat layer 24.
  • the chip mounting substrate XI shown in FIG. 1 is manufactured.
  • the laminated support substrate 10 is subjected to vacuum lamination using insulating sheets 20 and 20 ′, and then, as shown in FIG.
  • the steps from Fig. 2c to 2h may be performed.
  • the metal plating film 50 enables the edge portion 20 to be formed by the metal plating film 50 even when the number of build-up laminates 2 is large and the desmearing process performed when forming the via 23 is repeated many times. Since a and 20a are protected, it is possible to more effectively prevent the occurrence of broken holes or the like at the edges 20a and 20a.
  • a copper rack or the like can be used as a constituent material of the metal plating film 50.
  • the metal plating film 50 is subjected to the same processing for the edges 20 a and 20 a ′. It may be formed. By doing so, it is not necessary to provide a separate step for forming the metal plating film 50, and the working efficiency is improved.
  • a protective film 51 is further formed on the metal plating film 50, and then, as shown in FIGS. Each step up to h may be performed.
  • the number of build-up laminates 2 is large, and the seed layer (non- Even if the etching removal of the electrolytic copper plating film) is repeated many times, the metal plating film 50 can be prevented from being removed by etching, and as a result, tears or holes at the edges 20a and 20a 'can be prevented. Can be more effectively prevented.
  • a constituent material of the protective film 51 polytetrafluoroethylene, polypropylene, or the like can be used as a constituent material of the protective film 51.
  • the above-mentioned chip mounting substrate X1 is composed of a force S produced using a laminated supporting substrate 10 in which two supporting substrates 1 and 1 are laminated, a build-up laminate 2 formed on one supporting substrate 1, and an IC It may be manufactured by mounting the chip 3 and the capacitor 4. Also, the mounting positions of the IC chip 3 and the capacitor 4 may be interchanged. Further, after mounting the IC chip 3 or the capacitor 4 on the build-up laminate 2 through the through-hole 11, a step of further polishing the back surface 1 b of the support substrate 1 and the IC chip 3 or the capacitor 4 is performed. It may be provided.
  • the distance between the IC chip 3 and the capacitor 4 can be reduced. Thereby, inductance can be reduced and generation of noise can be suppressed.
  • the IC chip 3 can be mounted after the build-up laminate 2 is formed on the surface 1 a of the support substrate 1, the electrical continuity between the build-up laminate 2 and the IC chip 3 is achieved. Alignment for achieving alignment can be performed relatively easily. Also, since the IC chip 3 can be mounted after the build-up laminate 2 is formed, the IC chip 3 can be mounted after confirming that the build-up laminate 2 has been properly formed. It is excellent in practicality without wasting 3. Further, the support substrate 1 forms a through hole 11 by removing only the mounting area of the IC chip 3. Therefore, the remaining portion of the support substrate 1 plays a role similar to that of the stiffener, and has sufficient rigidity for mounting and other handling. Therefore, there is no need to provide a separate process for imparting rigidity. And work efficiency is excellent.
  • the build-up laminates 2 and 2 ′ and the support substrates 1 and ⁇ ′ are formed.
  • the warpage caused by the difference between the two coefficients of thermal expansion can be reduced. That is, by temporarily joining the back surfaces of the two support substrates 1 and 1 ′, the difference in the coefficient of thermal expansion between one support substrate 1 and the build-up laminate 2 formed on the surface of the support substrate is determined. Even if the warpage caused by the above occurs, the warpage is opposite to the warpage due to the difference in thermal expansion coefficient between the other support substrate 1 ′ and the build-up laminate 2 ′ formed on the surface of the other support substrate. Warping occurs and offset each other. Thereby, mounting reliability is improved.
  • the gap between the IC chip 3 mounted through the through-hole 11 and the through-hole 11 and the build-up laminate 2 is sealed with insulating resin to improve the insulation between wirings.
  • the stability of the mounted state of the IC chip 3 is increased. Therefore, higher reliability of the electrical connection between the IC chip 3 and the build-up laminate 2 can be achieved.
  • the back surface 1 b of the support substrate 1 and the IC chip 3 or the capacitor 4 are further polished, The thickness of the entire chip mounting substrate X1 can be reduced.
  • Two copper plates of 0.5 mm thick and 150 x 150 mm were prepared as a supporting base material, and the surfaces forming the build-up laminate were subjected to degreasing, acid treatment and CZ treatment, respectively. did. Then, the two copper plates were stacked so that their back surfaces face each other.
  • An epoxy resin sheet with a thickness of 50 ⁇ and a size of 200 ⁇ 200 mm (Product name: SH-9) , Made of Ajinomoto) and pressed at 130 ° C for 2 minutes using a vacuum laminator. Furthermore, an insulating layer was formed on the surface of each copper plate by laminating at 170 ° C. for 30 minutes.
  • via holes (diameter 50 / zm) were formed in predetermined positions in each insulating layer using a carbon dioxide laser, and desmearing was performed.
  • an electroless nickel layer having a thickness of 1 ⁇ was formed at the bottom of each via hole.
  • an electroless copper plating layer having a thickness of 0.3 ⁇ m was formed on each insulating layer and each electroless nickel layer.
  • a dry film resist (trade name: RY-340, manufactured by Hitachi Chemical) is formed on each electroless copper plating layer with a predetermined pattern. The electroless copper plating layer was formed using the electroless plating layer as a current-carrying layer.
  • the electroless copper plating film that had been covered with the dry film resist was removed by etching. Thereafter, the wiring pattern and the via were formed by heating at 170 ° C. for 6 ° minutes. Thereafter, the above-described series of steps from the step of forming the insulating layer to the step of forming the wiring pattern and the via was repeated four times to form a five-layer wiring structure.
  • an overcoat layer was laminated on the five-layer wiring structure by screen printing and photolithography.
  • An opening was provided at a predetermined position of the overcoat layer so that a part of the wiring pattern formed last could be seen.
  • a 1-m-thick electroless nickel layer is formed on the wiring pattern facing the opening, followed by a 3-m-thick gold plating layer to establish connection with external terminals.
  • a land electrode was formed. The land electrodes formed here are arranged corresponding to the arrangement of the conductive connecting portions of the capacitor to be mounted later.
  • the laminated state of the two copper plates was released by cutting and removing the epoxy resin sheet protruding from the build-up laminate formed on the surface of the copper plate without forming an insulating layer.
  • a dry film resist (trade name: NIT-50, manufactured by Nichigo Moton Co., Ltd.) is formed in a predetermined pattern on the back surface of the copper plate. (Kanto Kagaku) was used to etch the copper plate to form through holes. At this time, the via was not etched because the electroless nickel layer formed at the bottom of the via hole became a barrier metal.
  • a land electrode for connection with external terminals was formed by forming a 3 im thick gold plating layer on the electroless nickel layer of the via facing the through hole. .
  • the land electrodes formed here are arranged corresponding to the electrode arrangement of the IC chip to be mounted later.
  • the IC chip having a thickness of 0.5 mm was mounted on the build-up laminate by solder bonding via land electrodes in such a manner as to be housed in the through hole.
  • the gap created between the IC chip and the through-hole was sealed with epoxy resin (trade name: U84434-6, manufactured by Namics).
  • the capacitor was mounted on the build-up laminate by solder bonding via the land electrode.
  • via holes (diameter: 50 ⁇ ) were formed in predetermined positions in each insulating layer using a carbon dioxide laser, and desmearing was performed.
  • an electroless nickel layer having a thickness of 1 ⁇ was formed at the bottom of each via hole.
  • an electroless copper plating layer having a thickness of 0.3 ⁇ was formed on each insulating layer and each electroless nickel layer.
  • electroless plating was also performed on the edge (the portion other than the insulating layer) of each epoxy resin sheet to form a metal plating film having a thickness of 3 ⁇ m.
  • a dry film resist (trade name: RY-3240, manufactured by Hitachi Chemical) was formed in a predetermined pattern on each electroless copper plating layer.
  • the electroless copper plating layer was formed using the electroless copper plating layer as a current-carrying layer. After peeling off the dry film resist, the electroless copper plating film that had been covered with the dry film resist was removed by etching. Thereafter, by heating at 170 ° C. for 60 minutes, a wiring pattern and a via were formed. Thereafter, a wiring pattern and a via are formed from the step of forming the insulating layer described above. By repeating the series of steps up to the four steps four times, a five-layer wiring structure was formed.
  • an overcoat layer was laminated on the five-layer wiring structure by screen printing and photolithography.
  • An opening was provided at a predetermined position of the overcoat layer so that a part of the wiring pattern formed last could be seen.
  • an electroless nickel layer having a thickness of 1 ⁇ is formed on the wiring pattern facing the opening, and then a gold plating layer having a thickness is formed.
  • a land electrode was formed. The land electrodes formed here are arranged corresponding to the arrangement of the conductive connecting portions of the capacitor to be mounted later.
  • the laminated state of the two stainless steel plates was released by cutting and removing the epoxy resin sheet protruding from the build-up laminate formed on the surface of the stainless steel plate without forming an insulating layer.
  • a dry film resist (trade name: NI 4-40, manufactured by Nichigo Morton) is formed on the back surface of the stainless steel plate in a predetermined pattern, and using the mask as a mask, the stainless steel plate is etched using an etching solution. Etching was performed to form through holes.
  • a land electrode for connection with external terminals is formed by forming a gold plating layer with a thickness of 3 ⁇ on the electroless nickel layer of the via facing the through hole. did.
  • the land electrodes formed here are arranged corresponding to the electrode arrangement of an IC chip to be mounted later.
  • the IC chip having a thickness of 0.3 mm was mounted on the build-up laminate by soldering via land electrodes in such a manner as to be housed in the through hole.
  • the gap created between the IC chip and the through-hole was sealed with epoxy resin (trade name: U84434-6, manufactured by Namics).
  • the capacitor was mounted on the build-up laminate by solder bonding via the land electrode.
  • the IC chip and the build-up A chip that is relatively easy to align, suppresses waste of Ic chips due to the yield of the build-up laminate, and is efficient and has excellent mountability without additional rigidity.
  • the mounting substrate can be manufactured.
  • the manufactured chip mounting board has a small inductance due to a small distance between the IC chip and the capacitor, thereby reducing noise.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

La présente invention se rapporte à une plaquette de montage de composants électroniques qui est fabriquée conformément au procédé suivant. Premièrement, des couches d'isolation assemblées (21a-21f) et des motifs de câblage assemblés (22a-22f) sont formés alternativement sur la surface (1a) d'un substrat de support métallique (1) (étape de stratification par assemblage). Ensuite un trou traversant (11) allant de la face arrière (1b) du substrat de support (1) jusqu'à la face avant (1a) est formé afin d'exposer la face arrière (211a) de la couche d'isolation assemblée la plus interne (21a) (étape de perforation). Enfin, un composant électronique (3) est monté sur la face arrière (211a) de la couche d'isolation assemblée la plus interne (21a) à travers le trou traversant (11) du substrat de support (1) (étape de montage).
PCT/JP2003/000326 2003-01-16 2003-01-16 Procede de fabrication d'une plaquette de montage de composants electroniques et plaquette de montage electronique fabriquee conformement a ce procede Ceased WO2004064150A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2003/000326 WO2004064150A1 (fr) 2003-01-16 2003-01-16 Procede de fabrication d'une plaquette de montage de composants electroniques et plaquette de montage electronique fabriquee conformement a ce procede
JP2004566275A JP3999784B2 (ja) 2003-01-16 2003-01-16 電子部品搭載基板の製造方法
TW092101273A TW566065B (en) 2003-01-16 2003-01-21 Method of making electronic component-mounted substrate, and chip-mounted substrate made by using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2003/000326 WO2004064150A1 (fr) 2003-01-16 2003-01-16 Procede de fabrication d'une plaquette de montage de composants electroniques et plaquette de montage electronique fabriquee conformement a ce procede

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Cited By (10)

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JP2006066522A (ja) * 2004-08-25 2006-03-09 Fujitsu Ltd 半導体装置およびその製造方法
JP2007266443A (ja) * 2006-03-29 2007-10-11 Shinko Electric Ind Co Ltd 配線基板の製造方法、及び半導体装置の製造方法
JP2008198846A (ja) * 2007-02-14 2008-08-28 Fujitsu Ltd 多層配線基板およびその製造方法
JP2009224415A (ja) * 2008-03-13 2009-10-01 Ngk Spark Plug Co Ltd 多層配線基板の製造方法、及び多層配線基板の中間製品
JP2009278060A (ja) * 2008-05-13 2009-11-26 Samsung Electro-Mechanics Co Ltd 印刷回路基板及びその製造方法
JP2010114291A (ja) * 2008-11-07 2010-05-20 Renesas Technology Corp シールド付き電子部品およびその製造方法
JP2011138868A (ja) * 2009-12-28 2011-07-14 Ngk Spark Plug Co Ltd 多層配線基板
TWI393231B (zh) * 2008-05-21 2013-04-11 欣興電子股份有限公司 嵌埋半導體晶片之封裝基板及其製法
JP2013093623A (ja) * 2013-02-18 2013-05-16 Shinko Electric Ind Co Ltd 半導体パッケージ
JP2018098491A (ja) * 2016-12-16 2018-06-21 サムソン エレクトロ−メカニックス カンパニーリミテッド． プリント回路基板、パッケージ及びプリント回路基板の製造方法

Families Citing this family (2)

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TWI407870B (zh) * 2006-04-25 2013-09-01 日本特殊陶業股份有限公司 配線基板之製造方法
JP2015065400A (ja) * 2013-09-25 2015-04-09 サムソン エレクトロ−メカニックス カンパニーリミテッド． 素子内蔵型印刷回路基板及びその製造方法

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US20020001937A1 (en) * 2000-06-30 2002-01-03 Nec Corporation Semiconductor package board using a metal base
JP2002026171A (ja) * 2000-07-06 2002-01-25 Sumitomo Bakelite Co Ltd 多層配線板の製造方法および多層配線板
JP2002319760A (ja) * 2001-04-20 2002-10-31 Ngk Spark Plug Co Ltd 配線基板の製造方法

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US6031284A (en) * 1997-03-14 2000-02-29 Lg Semicon Co., Ltd. Package body and semiconductor chip package using same
US20020001937A1 (en) * 2000-06-30 2002-01-03 Nec Corporation Semiconductor package board using a metal base
JP2002026171A (ja) * 2000-07-06 2002-01-25 Sumitomo Bakelite Co Ltd 多層配線板の製造方法および多層配線板
JP2002319760A (ja) * 2001-04-20 2002-10-31 Ngk Spark Plug Co Ltd 配線基板の製造方法

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006066522A (ja) * 2004-08-25 2006-03-09 Fujitsu Ltd 半導体装置およびその製造方法
JP2007266443A (ja) * 2006-03-29 2007-10-11 Shinko Electric Ind Co Ltd 配線基板の製造方法、及び半導体装置の製造方法
JP2008198846A (ja) * 2007-02-14 2008-08-28 Fujitsu Ltd 多層配線基板およびその製造方法
JP2009224415A (ja) * 2008-03-13 2009-10-01 Ngk Spark Plug Co Ltd 多層配線基板の製造方法、及び多層配線基板の中間製品
JP2009278060A (ja) * 2008-05-13 2009-11-26 Samsung Electro-Mechanics Co Ltd 印刷回路基板及びその製造方法
TWI393231B (zh) * 2008-05-21 2013-04-11 欣興電子股份有限公司 嵌埋半導體晶片之封裝基板及其製法
JP2010114291A (ja) * 2008-11-07 2010-05-20 Renesas Technology Corp シールド付き電子部品およびその製造方法
US9001528B2 (en) 2008-11-07 2015-04-07 Renesas Electronics Corporation Shielded electronic components and method of manufacturing the same
JP2011138868A (ja) * 2009-12-28 2011-07-14 Ngk Spark Plug Co Ltd 多層配線基板
JP2013093623A (ja) * 2013-02-18 2013-05-16 Shinko Electric Ind Co Ltd 半導体パッケージ
JP2018098491A (ja) * 2016-12-16 2018-06-21 サムソン エレクトロ−メカニックス カンパニーリミテッド． プリント回路基板、パッケージ及びプリント回路基板の製造方法

Also Published As

Publication number Publication date
JP3999784B2 (ja) 2007-10-31
TW200414856A (en) 2004-08-01
JPWO2004064150A1 (ja) 2006-05-18
TW566065B (en) 2003-12-11

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