WO2004049576A2

WO2004049576A2 - Track and hold circuit

Info

Publication number: WO2004049576A2
Application number: PCT/EP2003/050867
Authority: WO
Inventors: Walter Snoeijs
Original assignee: Individual
Current assignee: Individual
Priority date: 2002-11-22
Filing date: 2003-11-21
Publication date: 2004-06-10
Anticipated expiration: 2005-05-22
Also published as: AU2003298306A8; AU2003298306A1; WO2004049576A3

Abstract

A circuit comprises at least one storage element. This storage element can be affected by a non-linear element controlled in part by the input and in part by actively driving the storage element to adapt and optimize the operating condition of the non-linear element at any given time. The transfer of the signal to be stored on this storage element can be interrupted prior to obtaining the required accuracy, where this required accuracy is recovered by treating a reference signal or reference signals in a similar way as the input signal. The stored signal can be read from the storage element incrementally in several phases to optimize the dynamic range and gain of the subsequent circuitry. The stored signal can be read from the storage element without buffer deteriorating the stored signal beyond the required accuracy, where this required accuracy is recovered by treating a reference signal or reference signals in a similar way as the input signal. The invention relates to sample-and-hold circuits, track-and-hold circuits, charge transfer amplifiers, and to analog-to-digital converters and signal processors using such circuits or amplifiers.

Description

Track and Hold circuit

Field of the invention

The invention relates to track and hold and sample and hold circuits. It also relates to an analog-to-digital conversion circuits {A/D conversion circuit) employing such track and hold circuits. It also relates to signal processors incorporating such A/D conversion circuits, or track and hold and sample and hold circuits. It also relates to charge transfer amplifiers.

Description of related art

Track and hold and sample and hold circuits have been extensively used in analog-to-digital converters to reduce the bandwidth requirements of the subsequent circuitry. The track and hold or sample and hold circuit captures the value of an input signal at certain instances and holds it for a certain period of time while presenting it to the subsequent circuit. As a result, this subsequent circuit acts on a signal which is essentially constant within the hold period instead of acting on the time- varying input signal itself. This usually severely reduces the required bandwidth for this subsequent circuit and hence its cost and power consumption.

In most track and hold or sample and hold implementations, a charge which is a measure of the input signal is generated and stored onto a capacitor. A general problem caused by the trend towards lower voltage in present-day electronic systems is that the thermal noise becomes more of a limitation and storing a charge on a storage capacitor is no exception: thermal fluctuations cause the stored charge on a storage capacitor to vary by the square root of (kTC) rms where k is Boltzmann's constant, T is absolute temperature, and C is the capacitance value of the storage capacitor. This noise charge corresponds to a noise voltage of V(kT/C) rms on the storage capacitor. For a fixed signal to noise ratio the value of the sample capacitor is inversely proportional to the input voltage range imposing the use of very large sampling capacitors for lower voltage ranges. This causes bandwidth problems and pushes towards larger power consumption. Note that the input bandwidth often needs to be significantly larger than the bandwidth of the input signal itself in order to allow the voltage on the sample capacitor to settle to the input signal within the required accuracy.

As an example, Fig. 1 shows a conventional prior art sample and hold circuit consisting of a capacitor CS, a switch SW and an output buffer B. In track mode, the switch SW is closed and the input signal Vin forces a voltage on the capacitor CS through the switch SW. At the transition into hold mode, the switch SW is opened and, ideally, the voltage of the input signal Vin at that moment is held onto the capacitor CS while the switch SW is kept open. The buffer B drives the subsequent circuitry without corrupting the signal held on CS.

If the switch SW is implemented with a semiconductor device, this circuit suffers from several problems limiting its performance, among which: first, when the switch SW is opened, its resistance increases, resulting in an increasing RC time constant yielding a poor definition of the aperture time. Second, the switching off dumps an input dependent charge onto the storage capacitor CS.

The latter can be remedied by a well-known circuit shown in fig. 2, wherein a second switch SW2 has been added to the circuit of fig. 1. During the tracking period, both switches SW and SW2 are closed, and operation is similar to that of the circuit shown in fig. 1. During the transition into hold mode, the second switch SW2 is opened first, and the switch SW is opened only thereafter. Since the voltages seen by the second switch SW2 are to first order independent of the input signal Vin, charge injection by the second switch SW2 is roughly independent of the input signal Vin. If the parasitic capacitance of the node linking the storage capacitor CS and the second switch SW2 is minimal, the opening of the second switch SW2 defines the transition into hold mode, because at that point one terminal of the storage capacitor CS is floating and the opening of the switch SW will not cause severe charge injection into the storage capacitor CS. After opening of the switch SW, the second switch SW2 can be closed again, and the signal held on the storage capacitor CS is then ideally equal to the value of the input signal Vin at the instant of the transition into hold mode. In another implementation, the terminal of the storage capacitor CS connected to the second switch SW2 can be linked by means of another switch to the input of a charge amplifier or to the input of an integrator once the switches SW2 and SW are open.

For the circuits of fig. 1 and fig. 2, the on-resistance of the switches SW and SW2 determines the track and hold circuit's input bandwidth, which will degrade for large values of the sample capacitor CS. In addition, unless a buffer is implemented, the input is loaded by the full sample capacitor CS, thus requiring significant drive capability from the circuit providing the input signal Vin.

Fig. 3 shows yet another implementation of a track and hold circuit: the input signal Vin is applied to the base of a first bipolar transistor BJT1, the collector of which is connected to the circuit's power supply. A current source 11, which is switched on and off by means of a control signal CLK, pulls current out of the emitter of the first bipolar transistor BJT1. The emitter of the first bipolar transistor BJT1 is also connected to the sample capacitor C1, and when the current source 11 is on, the first bipolar transistor BJT1 and the current source 11 form a buffer for the input signal Vin driving the sample capacitor C1. At the transition from track mode into hold mode, the control signal CLK turns the current source 11 off and the sample capacitor C1 is isolated from the input signal Vin to hold its voltage of that moment. A buffer formed by a second bipolar transistor BJT2 and a second current source 12 is linked to the sample capacitor C1 to drive the subsequent circuitry without corrupting the signal held by the sample capacitor C1. While this circuit could also function with MOS transistors, it is often implemented using bipolar transistors due to their superior transconductance. In fact, the fastest prior art track and hold circuits are implemented as in Fig. 3, but in practice considerable circuitry has to be added to prevent hold mode feedthrough from the input to the held signal, and to minimize the loading of the hold node by the base current of the second bipolar transistor BJT2. Also here the bandwidth will degrade when the sample capacitor C1 is increased, and the current to the first bipolar transistor BJT1 will typically very significantly contribute to the overall power consumption of the circuit.

It is thus an aim of the present invention to alleviate the bandwidth problem in track and hold and sample and hold circuits.

Another aim of the present invention is to provide a low power solution to sample an input signal.

Recently, charge transfer amplifiers have received considerable interest due to their ability to amplify an input signal without standing current. Fig. 4 shows an example of a prior art charge transfer amplifier: the input signal Vin is applied to the gate terminal GN of an NMOS transistor TN. The source of the transistor TN is connected to a first capacitance CN1 and to a first switch SN1 allowing to reset the source of the transistor TN to a first voltage VNS. Similarly, the drain of the transistor TN is connected to a second capacitance CN2 and to a second switch SN2 allowing to reset the drain of the transistor TN to a second voltage VND. The operation of the circuit of fig. 4 is as follows: during the reset phase, both switches SN1 and SN2 are closed, resetting the potential on source and drain of the transistor TN to the desired values VNS, respectively VND. During the precharge phase, the first switch SN1 is opened and the first capacitance CN1 is discharged through the transistor TN which gradually turns off. At a certain point, the second switch SN2 is opened and the current flowing through the transistor TN still discharging the first capacitance CN1 starts to charge the second capacitance CN2. The charging of the second capacitance CN2 by the discharge current of the first capacitance CN1 will cause the potential variation across the second capacitance CN2 to be ideally equal in magnitude to the potential variation times the ratio of the capacitance values of the first and the second capacitances CN1 and CN2. If the value of the first capacitance CN1 is larger than the value of the second capacitance CN2, voltage gain is achieved. The value of Vin will determine when the transfer of charge between the capacitors ends, and the resulting voltage Vout across CN2 is an amplified representation of the input voltage Vin. In practice, a reference voltage Vref is often applied to the gate GN of the transistor TN during the precharge phase, Vref being lower than any possible input value Vin. The precharge phase ends by opening the switch SN2 and applying Vin to the gate GN. The transistor TN becomes more conductive and the amount of charge transfer from the first capacitance CN1 to the second capacitance CN2 will be determined by the input signal Vin.

While such a charge transfer amplifier has several advantages, its maximal operating frequency is limited because as the charge transfer proceeds, the transistor TN is gradually turned off, thus deteriorating the bandwidth of the circuit and causing severe peak detecting behavior. This can be remedied by introducing switches to interrupt the discharge prior to completion, but for significantly incomplete charge transfer the output voltage will become sensitive to time jitter of the control signals of these switches. Furthermore, for large values of the first capacitance CN1, care has to be taken that the transistor TN remains dominant in the charge transfer process, i.e. the on-resistance of the switches has to be sufficiently small.

It has to be noted that charge transfer in the context of charge transfer amplifiers has to be distinguished from charge redistribution which happens when two storage nodes at different potential, each associated with a capacitor, are connected together by means of a switch. This charge redistribution will never exhibit gain without an additional amplifier. In the example of fig. 4, charge is transferred from one capacitor to another one through a non-linear element, the NMOS transistor TN, which contributes to the gain by providing a high impedance for the node to which the charge is transferred, and a low impedance for the node delivering the charge. In the following charge transfer in the context of charge transfer amplifiers is meant to be capable of providing voltage gain without an additional amplifier. In principle, a prior art charge transfer amplifier could be the basis of a track and hold circuit with very limited power consumption due to the absence of standing current, but it suffers from the disadvantages described above. In fact, even if only the first capacitance CN1 is present in the circuit of fig. 4 and the drain of the transistor TN is always connected to the potential VND, so it is no longer a charge transfer amplifier, a track and hold circuit could be implemented where the voltage held on the first capacitance CN1 would represent the value of the input signal Vin at the transition into hold mode. This circuit would be similar to the first stage of the track and hold circuit of fig. 3, in this case not an emitter follower but a source follower since the active device is a MOS transistor. However, since no DC current is applied to the MOS transistor, the source follower exhibits an extremely bad bandwidth as its active device is gradually turned off. Again, prematurely ending the discharge would alleviate the bandwidth problem but would introduce large time jitter sensitivity. For such circuit, the same limitations apply for using it as track and hold circuit as for the full charge transfer amplifier of fig. 4.

It is thus another aim of the present invention to provide a way to alleviate this bandwidth problem and sensitivity to timing jitter for charge transfer amplifiers and for sample and hold or track and hold circuits. As will be seen further, the invention allows for constructing track and hold circuits and charge transfer amplifiers with large bandwidth and low time jitter sensitivity and without standing current, resulting in very low power consumption.

Since comparators can be implemented as a special case of charge transfer amplifiers or sample and hold circuits, the solutions provided by this invention can be advantageously applied to comparators.

The trend towards lower power supply voltages also creates limitations in the circuitry reading the held signal from the sample capacitors or from capacitors on which charge is stored: the circuits need to be linear over the full range and if this full range corresponds to a very limited voltage range, this again pushes towards higher power consumption to overcome the noise. It is a further aim of the invention to provide a solution to this problem.

A further disadvantage when reading the signal charge from a storage capacitor is that, in order to avoid loading this capacitor and deteriorating the stored signal, a power consuming buffer typically needs to be provided. It is still a further aim of the invention to provide a way to read out the stored signal by capacitive loading without buffering and with correction for the signal deterioration sufficient to meet the precision requirements.

Brief summary of the invention

According to the invention, these aims are achieved by a circuit having the characteristics of the independent claim, advantageous embodiments being furthermore given by the dependent claims.

These aims are achieved in particular by a circuit comprising at least one storage element and a non-linear element, wherein the storage element has a reference terminal and a storage terminal, wherein an input signal to the circuit can affect the storage element at least in part by means of the non-linear element, and wherein the operation of the non-linear element is further controlled by actively driving the reference terminal with at least one control signal.

As will be seen further, the circuit of the invention allows for instance the construction of track and hold circuits or of charge transfer amplifier circuits for which at least one of the following holds:

- At least one of the sample capacitors or of the capacitors from or to which charge is transferred is influenced by the input signal at least in part by means of a non-linear element such as for example a transistor, and is actively driven by a driving signal from the terminal of said at least one capacitor which, in prior art circuits, is traditionally connected to a fixed potential during the tracking or amplification periods. Driving the non-linear element from this reference terminal of the capacitor can be used for instance to turn on the non-linear element and maximize its bandwidth at desired moments, for instance during the tracking or amplification periods, and also to turn off the non-linear element at the transition to hold mode or at the end of the amplification cycle to isolate the capacitor from the input signal, where at least one of the sample capacitors or of the capacitors from or to which charge is transferred is connected to the input signal by means of a non-linear element which only conducts significant current for a limited fraction of the total sample or amplification period, thus optimizing the power consumption for a certain bandwidth;

- Charge transfer from or to the capacitors is interrupted prior to completion, the sensitivity to time jitter being severely reduced, if necessary, by treating reference signals at the same time in a similar way and using the incomplete charge transfer from those as a reference to accurately reconstruct the input signal or its amplified version, thus allowing faster operation without sacrificing accuracy;

- The charge stored on the capacitors is injected or measured by the subsequent circuitry in several steps, each corresponding to a certain fraction of the total charge. For this purpose, the sample capacitors are preferably made of several sample capacitors in parallel. As will be explained in detail below, this allows the subsequent circuitry to treat signals of reduced range, and creates significant headroom in low voltage applications, and allows to eliminate additional gain stages,

- The deterioration of the signal charge stored on the capacitor or capacitors due to charge redistribution which occurs when loading said capacitor or capacitors by connecting the storage node to a capacitive load for readout is corrected. This may be done by introducing a similar charge redistribution on a sampled reference signal and using the result as a reference to accurately reconstruct the input signal or its amplified version.

In a preferred embodiment, the circuit comprises:

- at least one non-linear element controlled in part by the input signal;

- a capacitor with one terminal, designated in the following description as the storage terminal, directly connected to one of the terminals of said at least one non-linear element, the other terminal of the capacitor, designated in the following description as the reference terminal, being driven by a driving signal to control the charge transfer from and to the capacitor through said at least one non-linear element;

In case significant linearity or accuracy is required for the output response to an input signal, the circuit in a preferred embodiment further comprises a reference circuit comprising:

- another at least one non-linear element controlled in part by a reference signal;

- a capacitor with its storage terminal directly connected to one of the terminals of said another at least one non-linear element, its reference terminal being driven in a similar way to control the charge transfer from and to the capacitor through said another at least one non-linear element;

In this preferred embodiment, the reference circuit provides a reference output to which the output corresponding to the input signal can be compared or normalized. This provides a way to correct for errors due to timing jitter and incomplete settling and charge redistribution, and allows high current and very low duty cycle operation while minimizing accuracy and linearity penalties.

In a preferred embodiment, the capacitors are driven to maximally turn said non-linear elements on when actual amplification or tracking or sampling is taking place, and furthermore to turn them off at the desired moment. This optimizes current consumption for a certain bandwidth and reduces the influence of the on-resistance of the switches as the non-linear element acts as a switch itself, thus eliminating the need for another switch in series.

In an embodiment, switches are added to reset said capacitors or to connect and disconnect the input signal and/or reference signal from said non-linear elements.

In an embodiment, at least one of the capacitors from or to which charge is transferred is split into several capacitors which can be read out or addressed by or connected to the subsequent circuitry in more than one phase. This embodiment is particularly useful in an analog-to-digital converter which produces the bits in different phases, the most significant bits being determined in the first phase, and the least significant bits in the last phase, for instance in a successive approximation converter.

In an a preferred embodiment where a charge is transferred from a first capacitor to a second one through a non-linear element in the context of charge transfer amplification, this transfer phase is carried out after sampling or tracking of the input signal, in a phase distinctly different from this sampling or tracking phase. The separation of these two phases allows to optimize them separately: the sampling or tracking phase can be optimized for bandwidth and the transfer phase for maximal charge transfer. This also allows to carry out the charge transfer when the signal input no longer has any influence on the transferred signal providing lower parasitic feedthrough behavior. In an embodiment, these charge transfer circuits are cascaded to obtain a circuit similar to a bucket brigade but using standard CMOS technology rather than dedicated CCD technology. Charge is transferred from a preceding stage circuit of which the output is connected to the input of a subsequent stage circuit. Furthermore, the outputs of these charge transfer circuits can be combined by for instance connecting them to add their signals, before inputting them to a subsequent stage circuit. This can be advantageous for instance to increase the size of the input signal of the subsequent circuit or to cancel a common mode signal. Furthermore, the outputs of these charge transfer circuits can also be split into several outputs. This can be advantageous for instance to maximally profit from the dynamic range of the subsequent circuit.

Brief Description of the Drawings

The invention and its additional features, which may optionally be used to implement the invention to best advantage, will be apparent from and elucidated with reference to the embodiments described hereafter with reference to the accompanying drawings, wherein:

Previously discussed fig. 1 shows a prior art open loop track and hold circuit;

Previously discussed fig. 2 shows a prior art open loop track and hold circuit improved by using a well known technique to minimize input dependent charge injection;

Previously discussed fig. 3 shows another prior art open loop track and hold circuit;

Previously discussed fig. 4 shows a prior art charge transfer amplifier circuit-

Fig. 5A shows, in schematic form, a preferred embodiment of a track and hold circuit according to the present invention; Fig. 5B shows the control signals for the circuit of fig. 5A;

Fig. 6A shows another preferred embodiment of a track and hold circuit according to the present invention;

Fig. 6B shows the control signals for the circuit of fig. 6A;

Fig. 6C shows a block diagram representation of the circuit of fig.

6A;

Fig. 7A, fig. 7B and fig. 7C show, for the circuit of fig. 6A, a possible input signal, the corresponding signal at the input terminal of the non-linear element, and the corresponding output signal, respectively;

Fig. 8A, fig. 8B and fig. 8C show for three different time periods the signals shown in fig. 7A, fig. 7B and fig. 7C in more detail;

Fig. 9 shows a preferred embodiment of a pseudo-differential track and hold circuit according to the invention, based on the circuit of fig. 6A and fig. 6C, including a reference circuit to allow normalization to a reference signal;

Fig. 10A, fig. 10B and fig. 10C show, for three different time instances, the difference between input signals, the difference between the corresponding signals at the inputs of the non-linear elements, and the difference between the corresponding outputs, illustrating the need for normalization to a reference signal;

Fig. 10D shows the difference between reference input signals and the difference between the corresponding outputs, further illustrating the need for normalization to a reference signal;

Fig. 11 A, fig. 11 B, fig. 11 C and fig. 11 D show, for various time instances or periods, the difference between input signals and the difference between corresponding output signals after normalization to the corresponding reference signals;

Fig. 12A shows an embodiment of a track and hold circuit according to the present invention with two capacitors in parallel, each being driven by their own driving signal to create current peaks in the nonlinear element at two different instances in time;

Fig. 12B shows the control signals for the circuit of fig. 12A;

Fig. 13 shows another embodiment of a track and hold circuit according to the present invention where the non-linear element is a diode;

Fig. 14 shows an embodiment of a comparator circuit based on the present invention;

Fig. 15A to 15J relate to circuits according to the invention carrying out charge transfer from one capacitor to another one, where:

Fig. 15A shows an embodiment of a charge transfer circuit according to the invention comprising two non-linear elements, where the charge is transferred to a node fully isolated from the input signal;

Fig. 15B, fig. 15C and fig. 15D show three different sets of possible control signals for the circuit of fig. 15A;

Fig. 15E shows another embodiment of a charge transfer circuit according to the invention;

Fig. 15F shows the control signals for the embodiment of fig- 15E; Fig. 15G shows an integrator which can replace the capacitor to which the charge is transferred in the embodiments of fig. 15A and fig. 15E;

Fig. 15H shows a dynamic latch which can serve as an output device for two charge transfer circuits according to the embodiments of fig. 15A and/or of fig. 15E to implement a comparator;

Fig. 151 shows another embodiment of a charge transfer circuit according to the invention, wherein the capacitor to which charge is transferred is split into several capacitors for allowing treatment of the transferred charge in multiple phases;

Fig. 15J shows still another embodiment of a charge transfer circuit according to the present invention wherein inventive charge transfer circuits are cascaded to form a bucket brigade;

Fig. 16A shows an embodiment of a circuit allowing for a normalization of the outputs of the circuit of fig. 9 with respect to a reference signal-

Fig. 16B shows the detail of the capacitor array CC in fig. 16A;

Fig. 17A shows an embodiment of a circuit wherein the injection capacitor is split into several capacitors for allowing the injection of the signal into the subsequent circuitry in several phases;

Fig. 17B shows a block diagram of the circuit of fig. 17A;

Fig. 18 shows another embodiment of a circuit allowing for a normalization of the outputs of the circuit of fig. 9 with respect to a reference signal;

Fig. 19A shows another embodiment of a capacitor array; Fig. 19B shows a block diagram of the capacitor array of fig. 19A;

Fig. 20 shows an embodiment of a circuit allowing the correction of the charge redistribution , wherein the sample capacitors are loaded directly by the subsequent circuitry, and wherein the injection of the sampled signal is carried out in several phases;

Fig. 21 shows an embodiment of a track and hold circuit according to the invention allowing to inject the signal into the subsequent circuitry in several phases;

Detailed Description of the Invention

Fig. 5A shows a preferred embodiment of a track and hold circuit according to the present invention: the gate G of an NMOS transistor T, for example, can be connected to an input signal Vin by means of a first switch S1, and to a fixed potential VG by means of a second switch S2. The source of the transistor T is the output terminal of the circuit, providing an output signal Vout. It is connected to the storage terminal of a storage element, in this example a sample capacitor C, and can be connected to a second fixed potential VS by means of a third switch S3. The reference terminal of the sample capacitor C is driven by a driving signal TRH. In a variant embodiment, one or both of the fixed potentials VG and VS are the ground potential. The drain of the transistor T is connected to the circuit's power supply. The control signals for the circuit are shown in fig. 5B: a reset signal RST controls the third switch S3, a track signal TR controls the first switch S1 and the complement of TR (not represented) controls the second switch S2. The switches S1, S2 and S3 are closed or conducting when the corresponding control signal is high. So, in this embodiment, the first switch S1 is conducting when the second switch S2 is not and vice versa. In principle, the first and second switches S1 and S2 should not be both conducting at the same time, as that would short the input signal Vin to the fixed potential VG. A short period of time is preferably foreseen during which both switches S1 and S2 are off, in order to guarantee that the conduction periods of both switches are non-overlapping. The second terminal, or reference terminal, of the sample capacitor C is driven by the driving signal TRH.

The circuit operates as follows: in the reset phase, the driving signal TRH is brought up to its maximum, the first and third switches S1 and S3 are turned on and the second switch S2 is turned off. This causes the gate of the transistor T to be at the input potential, the source of the transistor T to be at the fixed potential VS, and the sample capacitor C to be charged. The third switch S3, controlled by the reset signal RST, is then opened and if the potential of the input signal Vin is high enough to turn on the transistor T, the sample capacitor C starts discharging through the transistor T. If the potential of the input signal Vin is not high enough to turn on the transistor T, the sample capacitor C doesn't discharge yet. Then, the driving signal TRH is brought down, pulling the source potential of the transistor T down. The swing on the driving signal TRH is sufficiently large to always turn on the transistor T and to evacuate some charge on the sample capacitor C through the transistor T. After the driving signal TRH is brought down, the discharge continues until the hold command is given by pulling the driving signal TRH back up. Raising the driving signal TRH pulls the source potential of the transistor T up and turns the transistor T off, effectively interrupting the discharge of the sample capacitor C. The gate G is disconnected from the input and connected to the fixed potential VG using the track signal TR and its complement. This avoids corruption of the held signal Vout by further variations of the input signal Vin.

Fig. 6A shows another embodiment of a track and hold circuit according to the invention which is different from the embodiment shown in fig. 5A. Instead of being linked to a fixed potential during hold mode, the gate G is capacitively coupled to a second track signal TR2 which can have the same time dependence as the track signal TR or have a falling edge which is slightly delayed with respect to the falling edge of the track signal TR. The amplitude of the second track signal TR2 can be the same as that of the track signal TR or different. The idea is that when the input signal Vin is disconnected from the gate G of the transistor T, the gate G can be pulled down by the second track signal TR2 through said capacitive coupling. Apart from this modification, the operation of the circuit shown in fig. 6A is identical to that of the circuit of fig. 5A, as can be seen from the command signals illustrated in fig. 6B. The advantage of the embodiment of fig. 6A is that the drop of the potential on the gate G is roughly independent from the input signal Vin. The embodiment of fig. 6A is further represented in block diagram form in fig. 6C: the circuit receives an input signal Vin and outputs an output signal Vout, and receives the control signals TR, TR2, TRH and RST shown for example in fig. 6B in order to operate correctly.

Fig. 7A, 7B and 7C further illustrate the operation of the circuit of fig. 6A for a certain input signal Vin shown as an example in fig. 7A as a function of time (time is expressed in nanoseconds). Fig. 7B shows the potential on the gate G of the transistor T, and fig. 7C shows the output voltage Vout. The sampling period has been chosen to be 10ns for this example. The reset phase lasts 1ns for this example, and starts at 0ns for the first sample period, at 10ns for the second, etc. Fig. 7A, 7B and 7C illustrate that the potential on the gate G is connected to the input during the reset and tracking phase and that it is held constant during the hold period. Its level is roughly equal to the input value when the hold command was given, minus a constant potential. This is because just after the hold command is given, the gate G is disconnected from the input signal Vin and capacitively pulled down by the second track signal TR2. During the hold period the output voltage Vout is held and is a measure of the input voltage Vin at the instant when the hold command was given.

Fig. 8A, 8B and 8C show the signals Vin and Vout as well as the potential on the gate G in more detail around the track and hold commands for three consecutive sample periods. The figures show the end of a hold period, a reset and a track period, and the beginning of the next hold period. Since three consecutive sample periods are shown, the hold state at the end in fig. 8A is the hold state at the beginning in fig. 8B, and the hold state at the end in fig. 8B is the hold state at the beginning in fig. 8C. At the end of the hold period, the driving signal TRH is brought up to its maximum just prior to reset. This causes the sudden rise of Vout and, due to the capacitive coupling from the output node to the gate of the transistor T, the rise of the potential on the gate G. Then the reset phase is started: the input signal Vin is connected to the gate G, so that the potential on the gate G tracks Vin, and the output signal Vout is linked to the fixed potential VS. After ending the reset period, discharge of the transistor C starts immediately for a sufficiently high input signal Vin. This is for instance the case in fig. 8B where the output signal Vout is seen to rise slightly even before the driving signal TRH is brought down. For fig. 8A and fig. 8C, the input signal Vin is not high enough to turn the transistor C on at the end of the reset phase. The driving signal TRH is brought down very fast shortly after the end of the reset period, which causes the output voltage Vout, the potential on the source of the transistor T, to undergo a sudden drop. The amplitude of the drop in Vout is determined by the input voltage Vin: the higher the input signal Vin, the smaller the drop, as the transistor T turns on sooner to clamp the output voltage Vout. The drop in the output signal Vout is followed by a rise of Vout, which is due to the fact that the transistor T is turned on and starts to discharge the capacitor C.

The hold command is given by bringing up the driving signal TRH. This causes a sudden rise of the output signal Vout, effectively turns the transistor T off and ends the discharge of the capacitor C, bringing the charge of capacitor C back up at least in part at about 0.4 ns after the end of the reset command, for this example. This causes the output voltage Vout to suddenly rise, resulting in the turning off of the transistor T and the interruption of the discharge of the capacitor C. The gate G is disconnected from the input signal Vin and pulled down by the second track signal TR2. For this example, the driving signal TRH is such that the output signal Vout, while being lower than the input signal Vin when the transistor T is turned on, is pushed up to slightly above the original input signal Vin. The potential on the gate G is pulled down by the second track signal TR2 to slightly below the original input signal Vin at the moment of the hold command. This guarantees the turn off of the transistor T. It can be seen in the figures 8A, 8B and 8C that the signal shape is similar for the three cases near the end of the discharge of the transistor C, just prior to the hold command. In fact, the control signals have brought the transistor T in about the same state (about the same current and same gate-to-source voltage) just prior to the hold command, so that Vout has become a good measure of Vin at the hold command, which was the purpose of the track and hold circuit. How good this measure of Vin is will be further clarified for the differential version of this circuit. Driving the driving signal TRH up at the hold command provides a very nice means to turn off the discharge because the hold command provides a voltage jump to first order independent of the input signal Vin, so signal dependent charge injection is minimized. Note that discharge is not complete when the hold command is given (the slope of Vout is not zero prior to the hold command). This circuit consumes current only during a very limited fraction of the total sample period exactly when bandwidth is needed. This yields a sampler with very low power consumption.

To better understand how good the output signal Vout after the hold command is as a measure of the input signal Vin at the hold instant, it is instructive to consider a pseudo-differential version of the circuit, illustrated in fig. 9. The pseudo-differential circuit of fig. 9 preferably comprises four track and hold circuits such as the one illustrated in fig. 6A and in fig. 6C receiving respectively a first input signal VinL, a second input signal VinR, a first reference signal REFL and a second reference signal REFR, and providing the corresponding output signals VoutL, VoutR, REFOL and REFOR, respectively.

First consider operation without taking the reference signals into account: Fig. 10A, 10B and 10C show, for three consecutive sampling periods, the differential input Vind which is the difference between the first input signal VinL and the second input signal VinR, the differential gate potential GD which is the difference between the corresponding gate potentials and the differential output Dvout which is the difference between the corresponding output signals VoutL and VoutR. The figures show how the differential gate potential GD tracks the differential input Vind during the tracking phase and how the differential output Dvout approaches the differential input Vind after the hold command. However, the figures illustrate that, due to the incomplete charging of the sample capacitor, the differential output Dvout does not fully equal the differential input Vind at that moment, but falls short by a few percent. A slight change in the duration of the discharge of the sample capacitor will change this percentage. Time jitter would thus create an often too large uncertainty in this percentage.

This problem can be remedied for example by using reference signals as illustrated in fig. 9, wherein all track and hold circuits are preferably controlled by the same command signals TR, TR2, TRH and RST. Fig. 10D shows the differential reference output DvoutR which is the difference between the first reference output signal REFOL and the second reference output signal REFOR and the differential reference input VindR which is the difference between the first reference input signal REFL and the second reference input signal REFR. The percentage by which the differential reference output signal DvoutR corresponding to the reference inputs falls short of the differential reference input VindR will be very similar, if the same control signals are used to obtain Dvout and DvoutR, to the percentage by which the differential output Dvout falls short of the differential input Vind. (Note that fig. 10D shows that settling is incomplete even for the outputs corresponding to the time invariant reference inputs!). Therefore, renormalizing the differential output Dvout to the differential reference output DvoutR to obtain a representation Voutd of the differential input Vind, will to first order eliminate errors due to time jitter and incomplete settling.

This is illustrated in fig. 11 A, 11B, 11C and 11D, which show that the renormalized differential output Voutd is a much better representation of the differential input Vind than the differential output DVout without normalization. Eliminating or severely reducing these errors and obtaining a relatively accurate estimate of an input signal even after incomplete settling by means of renormalization provides the possibility to operate the circuit of the invention at very high speeds while still conserving accuracy . How this renormalization can be carried out will be discussed further below. First, some variant embodiments of the track and hold circuit of the invention will be discussed, as well as the application of the present invention to charge transfer amplification.

Fig. 12A shows another embodiment of a track and hold circuit according to the present invention. According to this embodiment, the storage element is made up of a first sample capacitor CH1 and of a second sample capacitor CH2, driven respectively by a first driving signal TRH1 and a second driving signal TRH2. As shown in fig. 12B, the first and second driving signals TRH1 and TRH2 differ only in that the falling edge of the second driving signal TRH2 is slightly delayed with respect to that of the first driving signal TRH1. This increases the bandwidth a second time during the discharge. This can be used to further improve the precision of the signal about to be held. A similar effect could be obtained by controlling the circuit in fig. 6A with a driving signal TRH which is dropped to a first level to guarantee initiation of the discharge of the sample capacitor C, and then afterwards to another lower level to increase the bandwidth just prior to hold mode. All this is an illustration how driving the second terminal, also called reference terminal, of the sample capacitor creates the freedom to modulate the current in the circuit in almost arbitrary way and how this can be used advantageously.

The driving signal TRH is preferably generated by precharging and discharging capacitors to obtain fast signal transitions without significant standing current. If necessary capacitive boosting to increase voltage, well known to a person skilled in the art, can be used. Another advantage provided by the invention is that the circuitry generating the driving signal TRH does not need to act on severely input dependent signals (only its drive capability needs to be sufficiently large) easing the design of this part of the circuit.

Note that in these examples MOS devices were shown primarily for the non-linear elements. Controlling the emitter of a bipolar device or the source of a JFET transistor in a similar way as the source of these MOS devices will provide similar advantages. However, the bipolar transistor and the JFET exhibit base or gate current and care has to be taken in that case not to cause any signal deterioration on the storage element.

Another possible non-linear element is a diode, and the principle of the invention can also be applied making use of a diode. This is illustrated in fig. 13: an input signal Vin is applied to the positive terminal P of a diode D by means of a first switch SD1. This positive terminal P can also be linked to a fixed potential VG by means of a second switch SD2. The negative terminal N of the diode D is the output node yielding the output signal Vout. One terminal of the storage capacitor CD, its storage terminal, is linked to the output node, and the other terminal of the storage capacitor CD, its reference terminal, is driven by the driving signal TRH. The output node N can also be reset by linking it to a fixed potential VS by means of a third switch SD3.

The operation of the circuit of fig. 13 is similar as for the previously mentioned embodiments. During the reset phase, the driving signal TRH controlling the reference terminal of the storage capacitor CD is brought up to maximum, the positive terminal P is linked to the input signal Vin by the first switch SD1 and the negative terminal N is linked to the fixed potential VS by the third switch SD3. The first and third switches SD1 and SD3 are thus closed, and the second switch SD2 is open. Then the third switch SD3 is opened and, if the input signal Vin is sufficiently large, the storage capacitor CD will start to discharge through the diode D. The driving signal TRH can be brought down at the same time or somewhat later, and the swing of the driving signal TRH is sufficiently large to always turn on the diode D and discharge the storage capacitor CD at least to some extent.

The discharge of the storage capacitor CD during the tracking phase is ended by giving the hold command by bringing up the driving signal TRH to turn off the diode D. The positive terminal P is disconnected from the input signal Vin by opening the first switch SD1 and linked to the fixed potential VG by closing the second switch SD2. The charge remaining on the storage capacitor CD is the stored signal. Fig. 14 shows how a comparator can be constructed based on the invention. The principle is to compare the outputs of two samplers XL and XR according to the invention. XL and XR could be for example an embodiment as shown in fig. 5, in fig. 6A (and corresponding block diagram in fig. 6C) or in fig. 13, or any other embodiment of a track-and- hold circuit, or sampler, according to the invention. A first input signal VinL and a second input signal VinR are sampled by the first sampler XL and the second sampler XR respectively, whose output signals VoutL and VoutR respectively are directed for example to a cross-coupled transistor pair consisting of a first transistor TL and a second transistor TR. During reset, the output signals VoutL and VoutR are pulled low and the cross-coupled NMOS transistor pair TL and TR is turned off. The resetting mechanism of the track-and-hold circuits XL and XR will also reset the cross-coupled transistor pair TL, TR. The driving signal TRH is brought down to track the input signals VinL and VinR and discharge in part the storage capacitors of the samplers XL and XR. When the driving signal TRH is brought back up, the output voltages VoutL and VoutR are a measure of the input voltages VinL and VinR, and if the rise of the driving signal TRH is sufficient to turn on one or both of the transistors TL or TR, the positive feedback of the transistors TL and TR will amplify the difference between the output voltages VoutL and VoutR, and will provide a comparison signal.

Fig. 15A to 15J relate to various embodiments of, applications of and advantages provided by the present invention in the field of charge transfer amplifiers.

Fig. 15A shows a preferred embodiment of a charge transfer amplifier according to the present invention and fig. 15B, fig. 15C and fig. 15D show different variations of control signals for this embodiment. A first part of the embodiment in Fig. 15A is similar to the embodiment in fig. 6A: the gate GX of a first non-linear element, for example an NMOS transistor TXN, can be connected to the input signal Vin by means of a first switch SX1. The gate GX is also capacitively coupled to a first track signal SWX1 which can be used to further turn off the first transistor TXN during hold mode. The source of the first transistor TXN is connected to the storage terminal of a first capacitor CX1. The reference terminal of the first capacitor CX1 is driven by a driving signal TRHX. The drain of the first transistor TXN is connected to the circuit's power supply. A second nonlinear element is added to the circuit, for example a PMOS transistor TXP, the gate of which is connected to a fixed potential VGPX while its source is connected to the source of the first transistor TXN. The drain of the second transistor TXP is the output of the circuit and is further connected to the storage terminal of a second capacitor CX2, the reference terminal of which is for example connected to a fixed potential, for instance to the ground as shown in fig. 15A. The drain of the second transistor TXP can be reset to a fixed potential VPX by means of a second switch SX2.

In a variant embodiment (not represented), a third switch is linked to the source of the first transistor TXN (and thus to the source of the second transistor TXP) with the same function as the switch S3 in fig. 6A, but the circuit can also function without this third switch, in which case reset is carried out by driving the first capacitor CX1 up to make the second transistor TXP conductive and closing the second switch SX2 to clamp the drain of the second transistor TXP to the fixed potential VPX.

A first embodiment of the control signals for the circuit of fig. 15A are shown in fig. 15B: the track signal SWX1 controls the first switch SX1 and can also be used as the signal to which the gate GX is capacitively coupled to further turn off the first transistor TXN during hold mode, the second track signal SWX2 controls the second switch SX2, and the driving signal TRHX drives the first capacitor CX1.

According to this embodiment, the circuit operates as follows: in the reset phase the driving signal TRHX is brought up to maximum, the first and second switches SX1 and SX2 are turned on. This causes the gate GX of the first transistor TXN to be at the input potential Vin, and the drain of the second transistor TXP to be at the fixed potential VPX and causes the first capacitor CX1 to be charged. Then the driving signal TRHX is brought down, pulling the source potential of the first transistor TXN down. The swing on the driving signal TRHX is sufficiently large to always turn the first transistor TXN on and to turn the second transistor TXP off, and to evacuate some charge on the first capacitor CX1 through the first transistor TXN. After the driving signal TRHX is brought down, discharge continues until the driving signal TRHX is pulled back up. At this time the second switch SX2 is opened by means of the second track signal SWX2. Raising the driving signal TRHX subsequently pulls up the source potential of the first transistor TXN and of the second transistor TXP and turns the first transistor TXN off, effectively interrupting the discharge of the first capacitor CX1 through the first transistor TXN, and turns the second transistor TXP on causing the first capacitor CX1 to deliver some of its charge to the second capacitor CX2. The gate GX is disconnected from the input by opening the first switch SX1. This avoids corruption of the held signal by further variations of the input signal Vin. In the mean time, charge transfer from the first capacitor CX1 to the second capacitor CX2 is continued until the driving signal TRHX is brought back down turning the second transistor TXP off and possibly turning the first transistor TXN on. At that point, a charge which is a measure of the input signal is held on the second capacitor CX2.

Making the second capacitor CX2 significantly smaller than the first capacitor CX1 will provide gain between the input signal Vin and the signal held on the second capacitor CX2. If the first transistor TXN is turned on, some charge on the first capacitor CX1 is evacuated through the first transistor TXN. The rectangle in dashed line denotes the charge receiving part CRB of the charge transfer amplifier.

The advantages of this embodiment over the prior art charge transfer amplifiers are multiple, among which:

First, the tracking phase of the input signal Vin is separated from the phase in which charge is transferred to the second capacitor CX2, thus allowing to optimize these phases separately: the sampling or tracking phase can be optimized for bandwidth and the transfer phase for maximal charge transfer. This also allows to carry out the charge transfer when the input signal no longer influences the transferred signal, providing lower parasitic feedthrough behavior. Second, driving the capacitor from which charge is transferred by means of the driving signal TRHX applied to its reference terminal allows to turn the non-linear elements on and off without additional switches in series.

Third, the charge transfer amplifier according to the invention allows to modulate the current in the non-linear elements TXN, TXP to obtain more bandwidth when it is really needed and optimizes power consumption for a given bandwidth.

Fig. 15E shows another embodiment of a charge transfer amplifier according to the invention, wherein the storage element is made up of two capacitors CXA and CXB driven by a first driving signal TRHXA and a second driving signal TRHXB, respectively. The rectangle in dashed line again denotes the charge receiving part CRB of the charge transfer amplifier. The falling edge of the second driving signal TRHXB during tracking of the input signal Vin is slightly delayed with respect to the falling edge of the first driving signal TRHXA in order to increase the current through the first transistor TXN and obtain a larger bandwidth just before the first transistor TXN is switched off.

Fig. 15F illustrates the corresponding control signals. Note that the variant embodiment of control signals shown in fig. 15C have a similar effect for the embodiment in fig. 15A. The idea is that a larger bandwidth of the first transistor TXN can be obtained towards the end of the tracking phase by pulling its source down by means of a pulse over an additional capacitor CXB as in fig. 15E or by means of another signal transition of the driving signal TRHX, as in fig. 15C, over the same capacitor CX1 in the embodiment of fig. 15A. All this is an illustration of the fact that it is possible to control the conduction through the non-linear element TXN by controlling the reference terminal of one or more storage capacitors CX1 or CXA and CXB.

According to a variant embodiment, the charge receiving part can be something else than a capacitor. The charge receiving part CRB can for example be replaced by an integrator: fig. 15G shows an embodiment of an integrator consisting of an inverting amplifier INV, a feedback capacitor CSH and a reset switch SXH in parallel with the capacitor CSH. The advantage of using such an integrator as a charge receiving circuit CRB is that the drain of the second transistor TXP can be kept at a constant potential and that the capacitor CSH can be made very small resulting in very high gain if so desired. Note that using a PMOS transistor TXP as a second non-linear element, together with an integrator as in fig. 15G, in such a way that the PMOS transistor TXP remains in saturation allows the capacitor CX1 or the capacitors CXA and CXB not to be seen as a load by the integrator. Note as well that in case two charge transfer amplifiers are used to treat two different input signals, a differential integrator can be used to serve as charge receiving block for both charge transfer amplifiers. Similarly, a differential latch of which Fig. 15H shows an embodiment can be used as charge receiving block CRB for two charge transfer amplifiers driven by different input signals in order to implement a comparator.

According to further embodiments of the invention, the second non-linear element is split up into more than one transistor. Fig. 151 shows for example an embodiment of a charge amplifier according to the invention comprising two PMOS transistors TXP1 and TXP2. Each PMOS transistor TXP1, TXP2 is connected to a separate charge receiving block consisting for instance of a switch and a capacitor: a switch SXX1 and a capacitor CXX1 corresponding to the first PMOS transistor TXP1, and a switch SXX2 and a capacitor CXX2 corresponding to the second PMOS transistor TXP2. This allows the distribution of the charge on the capacitor CX1 over different capacitors. As will be clarified further below, this can provide significant advantages for instance in a sample and hold circuit, for instance when it is used in an analog-to-digital converter.

Fig. 15J shows an embodiment of a cascade of charge transfer amplifiers according to the invention, equivalent to a bucket brigade in CCD technology, but implemented for example here in standard CMOS technology. The charge receiving block CRB shown in fig. 15E is replaced by a second capacitor CY2 driven by a driving signal TRHY2 and two transistors, an NMOS transistor TYN2 and a PMOS transistor TYP2 both having their source connected to the storage terminal CR of the capacitor CY2 and their gate biased at a fixed potential VGNY, VGPY. The operation of the circuit is as follows. Before charge is transferred from a first capacitor CY1 through a PMOS transistor TYP to the charge receiving circuit, the charge receiving terminal CR is reset low by making the NMOS transistor TYN2 conduct through a decrease in voltage of the driving signal TRHY2. Any charge arriving on this node charges this node CR up. It is assumed that the PMOS transistor TXP2 is biased such that for normal signal ranges this charge does not make it conduct. Only when the driving signal TRHY2 is raised again, the PMOS transistor TXP2 starts to conduct and transfers charge to the next stage. In this manner, transfer of charge can be realized similarly to a bucket brigade. This allows to store charge in a pipeline and can have applications in filters, etc.

The benefit of renormalizing the sampled input signal to sampled references has been explained. Several ways are possible to carry out this renormalization using known circuits carrying out a division between input signal and reference signal. This may have the disadvantage that the division adversely affects the linearity of the circuit. However, according to the invention, an easy way to effectively carry out this renormalization in conjunction with an analog-to-digital converter in a highly linear way is the following: if the converter is based on one or more integrators with one or more digital-to-analog converters (DACs) constructed from a capacitance array, the reference outputs of the circuit in fig. 9 can be used to generate the reference voltage in the DAC or DACs. The coarse conversion is carried out on the sampled output prior to renormalization, which normally only affects the input signal at the level of a few percent. When the DAC output is generated however, it is scaled by the difference of the sampled references, so that the result of the subtraction between sampled input and the DAC output representing the coarse conversion still remains to be renormalized. So, in fact, the coarse conversion acts on the raw sampled signal, but the subtraction takes the normalization into account, so that the same principle can be applied on the residue for the full series of coarse conversions, finally yielding the full conversion. In a successive approximation ADC the input signals and sampled references will normally only be sampled again after completion of the full conversion. For a pipelined ADC both residue and the reference outputs need to be sampled and held for the subsequent conversions, so that the first sample and hold stage is freed completely to treat the next sample, including the sampling of the references.

This principle works in this form if the renormalization affects the input signal only at a level less than the precision of the coarse conversion. If this renormalization affects the input signal at a more significant level, a time-invariant correction can be provided in the coarse converter on the condition that the variation from sample to sample on the normalization is not larger than the precision of the coarse conversion.

Fig. 16A shows an embodiment of a circuit implementing this renormalization: the outputs of the sample and hold circuit shown for example in fig. 9 are applied to four buffers: the first output signal Voutl is applied to the first output buffer BOL, the second output signal Voutr to the second output buffer BOR, the first reference output REFOL to the first reference buffer BFL and the second reference output REFOR to the second reference buffer BFR. The buffer outputs are connected to capacitors linked with their other terminal to the inputs IL and IR of an integrator consisting of an amplifier A providing the outputs OL and OR which are fed back by a first feedback capacitor CFL to the first input IL and a by a second feedback capacitor CFR to the second input IR respectively. Switches SFL and SFR in parallel with the feed-back capacitors CFL and CFR, respectively, provide means to reset the integrator. The output IBL of the first output buffer BOL drives the first input IL through a first injection capacitor CIL and the output IBR of the second output buffer BOR drives the second input IR through a second injection capacitor CIR. The outputs VBL and VBR of the reference buffers BFL and BFR drive the inputs IL and IR through an array of capacitors CC further detailed in fig. 16B consisting of two series of N capacitors CD1L to CDNL and CD1R to CDNR. The first input IL is driven by a first series of capacitors CD1 L to CDNL, and the second input IR is driven by a second series of capacitors CD1R to CDNR. All capacitors of both series can be connected with their second terminal either to the first reference buffer output VBL or to the second reference buffer output VBR, effectively forming a digital to analog converter (DAC) with the difference between the reference buffer outputs VBL and VBR as its voltage reference: switching capacitors between the outputs VBL and VBR injects some charge into the integrator, which is then transferred to the feedback capacitors CFL and CFR resulting in a change in the outputs OL and OR. The outputs OL and OR of the integrator are applied to a circuit carrying out an analog-to-digital conversion yielding one or more bits corresponding to the difference in potential between the outputs OL and OR. These one or more bits are then used to control the switching of some of the capacitors in the capacitance array CC from VBL to VBR and vice versa to improve the approximation of the input by the DAC output, so that, in a next step, an analog-to-digital conversion can be carried out on the residue between sampled input and DAC output.

Note that in this implementation, the residue and its representation at the outputs OL and OR will decrease in amplitude after every conversion and new residue generation, necessitating a gain adaptation in front of or in the conversion part for every coarse conversion until the conversion of the corresponding sample of the input has been completed. This requirement to change the gain creates an additional cost in circuitry and power consumption and is preferably avoided.

According to a variant embodiment of the invention, a way to avoid this gain adaptation is for example to inject the charge corresponding to a certain sample of the input in several phases into the integrator. This can be done by splitting the injection capacitors CIL and CIR of fig. 16A into a number of capacitors. In the example discussed and illustrated in fig. 17A and fig. 17B, the injection capacitor CIL is split into three capacitors CIL1, CIL2 and CIL3. The injection capacitor CIR is split into three capacitors CIR1, CIR2 and CIR3 in an identical way. In the following the details will only be discussed and illustrated for the three capacitors CIL1, CIL2 and CIL3. The details are completely similar for the three capacitors CIR1, CIR2 and CIR3. The ratio of the capacitance values of the capacitors CIL1, CIL2 and CIL3 is carefully chosen such that the residue obtained after each coarse conversion has the same range. Therefore, instead of having the residue decrease in amplitude after every coarse conversion as in the embodiment of fig. 16A, the charge corresponding to the sampled input from which the residue is obtained is increased after every coarse conversion (so also the amplitude of the DAC value has to adapted accordingly). This is done by connecting the first capacitor CIL1 to the first buffer output IBL using switch SIL1 in fig 17A to obtain sufficient charge corresponding to the sampled input for the first coarse conversion. After this first conversion the second capacitor CIL2 is connected to the first buffer output IBL as well, injecting an additional fraction of the total sample charge into the integrator, while at the same injecting charge using the DAC to obtain a residue. The third time CIL3 is connected to the first buffer output IBL as well and for this example where the injection capacitor CIL is split up into three injection capacitors CIL1, CIL2, CIL3 only, this injects the full remainder of the sample charge into the integrator. Again the DAC output is adapted to this new full range.

This approach provides a constant residue range and a constant gain for the conversion and avoids the gain adaptation circuitry in front of or in the conversion part. The relative accuracy still improves after every coarse conversion as the input range increases while the residue range remains constant. A very significant advantage is that in this case the output swing of the integrator only needs to be designed for the residue range and not for the full range, since in the beginning only a small part of the total sample charge is injected. This means that headroom requirements for this integrator can be significantly relaxed allowing very low voltage operation. Normally the headroom limitations will be relaxed to such an extent that also the gain of this integrator can be increased to relax requirements on all subsequent circuitry. In short, this injection of the sampled charge in multiple steps provides very significant advantages.

Another embodiment of the same principle to carry out the renormalization is shown in Fig. 18. The difference between this embodiment and the one of fig. 16A is that the buffers for the sampled signals have been omitted, so that the sample capacitors, or other storage elements of the (not represented) track and hold circuits, directly drive the injection capacitors CIL, CIR, CC for the integrator. These injection capacitors CIL, CIR, CC are switched between a reference voltage VPX and the sample capacitors. This can corrupt the signal if the sample capacitors are not sufficiently large with respect to the injection capacitors CIL, CIR, CC. The signal is corrupted in two ways: the first is related to charge redistribution, and the second is related to kTC noise. When an injection capacitor is switched from the reference voltage VPX to one of the sample capacitors, the charge on the injection capacitor and the sample capacitor will redistribute. This will create a step in the voltage across the sample capacitor and will rarely be negligible. However, in the absence of noise this step is deterministic, and a way to correct it is explained below. The second contribution to signal corruption is kTC noise: after opening the switch connecting the injection capacitor to VPX, this capacitor will carry kTC noise, which will affect the resulting voltage on the sample capacitor to which the injection capacitor is connected. This kTC noise is a random effect and cannot be corrected in a deterministic way. However, if the sample capacitor is significantly larger than the injection capacitor, this kTC noise contribution will be negligible.

When two capacitors C1 and C2 are connected each with a first terminal to a certain fixed potential or a virtual ground (which can be different for the two capacitors) and precharged to a certain value V1 and V2 and then connected together by means of their second terminal, ideally the voltage change on C1 equals:

C2(V2-V1)

ΔV1 =

C1+C2

If the two injection capacitors CIL and CIR connected by one terminal to IL and IR respectively and having the same capacitance value C1 are switched at the same time between VPX and VOUTL and between VPX and VOUTR, respectively, the change in VOUTL-VOUTR equals:

C2 (VOUTL-VOUTR) Δ(VOUTL-VOUTR) = —

C1+C2

C2 in this formula is the total capacitance associated with VOUTL and with VOUTR. So, the relative change in voltage is a function of the capacitance values only and not of VOUTL and VOUTR. Therefore, if the capacitances associated with REFOL and REFOR have the same value and a similar switch is carried out for capacitors from VPX to REFOL and from VPX to REFOR where those capacitors are not connected to the inputs IL and IR of the integrator but to some other fixed potential to prevent them from acting as injection capacitors for the integrator, the ratio between REFOL- REFOR and VOUTL-VOUTR should remain unaffected. If in addition the DAC is realized in such a way that when capacitances are switched in the capacitor array of the DAC linked to REFOL and REFOR, there is a corresponding switch in a similar capacitor array linked to the sampled inputs but not connected to the input of the integrator but to ground, this should not affect the aforementioned ratio either. In other words, carrying out the switching as described preserves the validity of the renormalization of VOUTL-VOUTR by VREFOL-VREFOR.

All this is illustrated in fig. 20. The capacitor array CC2 in fig. 20 is detailed in fig. 19A and represented in block diagram form in fig. 19B. This capacitor array allows to switch the capacitors not only between its two inputs XL and XR but also to connect them to a fixed potential VPX. This is done to be consistent in the illustration of switching capacitors between a fixed potential VPX and an input. In practice, one can also use the capacitance array CC of fig 16B for the sampled references REFOL and REFOR as shown in fig. 16A and an identical capacitance array CCid (not represented) for the sampled inputs VOUTL and VOUTR, where Ccid is not connected to IL and IR but to a fixed potential. Fig. 20 shows the full embodiment using the capacitor arrays CC2 described earlier. As long as the capacitors that are switched in these arrays are significantly smaller than the sample capacitors, kTC noise due to the switching will be negligible, while the signal corruption due to charge redistribution is cancelled. This scheme, in combination with the renormalization to the sampled reference, allows therefore a direct connection to the sample capacitors and elimination of the buffers providing significant power savings.

Injecting the sampled signal into the subsequent circuitry into several phases can also be applied in a case where the sampled signal is not renormalized to a sampled reference varying in time, but to a fixed reference VREF. An embodiment of this is shown for example in fig. 21. According to this embodiment, during the tracking period, the sample capacitors are connected to the input with their storage terminal and to a fixed potential VGP with their reference terminal. During the tracking period, switches SWL1, SWL2, SWL3 thus connect the first input signal VINL to sample capacitances CSL1, CSL2, CSL3, while switches SWR1, SWR2, SWR3 connect the second input signal VINR to sample capacitances CSR1, CSR2, CSR3. Switches SUL1, SUL2, SUL3 and SUR1, SUR2, SUR3 connect the sample capacitors during the tracking period to a fixed potential VGP.

The hold command is then given by opening these switches SUL1, SUL2, SUL3 and SUR1, SUR2, SUR3. After subsequent opening of SWL1, SWL2, SWL3 and SWR1, SWR2, SWR3 to isolate the sample capacitors from the input signals VINL and VINR, the switches SUL1, SUL2, SUL3 and SUR1, SUR2, SUR3 connect the sample capacitors CSL1, CSL2, CSL3 to the first input IL and the sample capacitors CSR1, CSR2, CSR3 to the second input IR of the integrator. The integrator consists of an amplifier A with feedback capacitors CFL and CFR and reset switches SFL and SFR.

In addition to the aforementioned switches, a switch SLR is opened during track mode and closed only after the transition into hold mode in order to inject the charge of the sample capacitors into the integrator. The storage nodes of CSL1 and CSL2 can be connected to each other by a switch SVL1, and the storage nodes of CSL2 and CSL3 can be connected to each other by a switch SVL2. Similarly, the storage nodes of CSR1 and CSR2 can be connected to each other by a switch SVR1, and the storage nodes of CSR2 and CSR3 can be connected to each other by a switch SVR2. During track mode, the switches SVL1, SVL2, SVR1 and SVR2 can be closed but they have to be opened prior to closing the switch SLR. This allows the switch SLR to connect the storage nodes of CSL1 and CSR1 to each other after transition into hold mode, without affecting at that stage the storage node of CSL2, CSL3, CSR2 and CSR3. Closing the switch SLR will cause the differential charge signal on CSL1 and CSR1 to be injected into the integrator.

After carrying out a first conversion based on the outputs OL and OR of the integrator, the digital-to-analog converter DAC based on a capacitor array is switched according to the result of this first conversion while at the same time the switches SVL1 and SVR1 are closed. This injects an additional fraction of the sample charge into the integrator, together with the charge generated in the DAC, the combination of which will result in the generation of a first residue at the outputs OL and OR of the integrator. This residue is converted, the DAC state is changed accordingly while closing the switches SVL2 and SVR2 to generate the final residue for the final conversion. In this case the digital-to-analog converter DAC makes use of a reference VREF which is ideally time invariant.

In many applications the signal to be converted is composed of a baseline which can be time variant, but which can often be guessed rather accurately prior to the conversion, and of a signal, which contains the true information and often is much smaller than the baseline signal. The embodiment of the invention where a sampled signal is injected into the subsequent circuitry in several phases is particularly suited for treating such input signals. The DAC could, for the first conversion, already be set to the expected value of the baseline, and the conversion of the signal could start immediately with the conversion of the difference between the actual signal and the expected baseline, and also this residue could be injected in several phases into the subsequent circuitry. Such an arrangement could for instance be used in radio frequency applications, where the high frequency carrier is modulated by the real signal, and where the dynamic range of the resulting signal is many orders of magnitude larger than the dynamic range of the meaningful signal itself. Another example of such application is sensor readout where a DC or near DC offset has to be subtracted from the sensor output to obtain the meaningful signal.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects as illustrative and not restrictive.

Claims

1. A circuit comprising at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) and a non-linear element (T, D, TXN, TYN), wherein said at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) has a reference terminal and a storage terminal, wherein an input signal (Vin) to said circuit can affect said at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) at least in part by means of said nonlinear element (T, D, TXN, TYN), and wherein the operation of said nonlinear element (T, D, TXN, TYN) is further controlled by actively driving said reference terminal with at least one control signal (TRH, TRH1, TRH2, TRHX, TRHXA, TRHXB, TRHY2).

2. The circuit of claim 1, wherein said at least one control signal (TRH, TRH1, TRH2, TRHX, TRHXA, TRHXB, TRHY2) makes said non-linear element (T, D, TXN, TYN) conduct a significant current only for a small fraction of time.

3. The circuit of one of the claims 1 or 2, wherein said at least one control signal (TRH, TRH1, TRH2, TRHX, TRHXA, TRHXB, TRHY2) modulates the current in said non-linear element (T, D, TXN, TYN) to obtain maximum signal bandwidth at specific moments in time.

4. The circuit of one of the claims 1 to 3, wherein said at least one control signal (TRH, TRH1, TRH2, TRHX, TRHXA, TRHXB, TRHY2) is used to disconnect said storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) from said input signal (Vin) to hold its signal value at that time.

5. The circuit of one of the claims 1 to 4, outputting an output signal (Vout) being a measure of said input signal (Vin) at specific moments in time.

6. The circuit of one of the claims 1 to 5, comprising a sample and hold circuit or a track and hold circuit.

7. The circuit of one of the claims 1 to 6, wherein said non-linear element is a transistor (T, TXN, TYN).

8. The circuit of one of the claims 1 to 7, wherein said non-linear element is a diode (D).

9. The circuit of one of the claims 1 to 8, wherein said storage element comprises at least one capacitor (C, CH1, CH2, CD, CX1, CXA, CXB, CY1).

10. The circuit of one of the claims 1 to 9, further comprising a second non-linear element (TXP, TXP1, TXP2, TYP) and a charge receiving block (CRB), said first storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) being at least partially discharged at specific moments in time onto said charge receiving block (CRB) through said second non-linear element (TXP, TXP1, TXP2, TYP).

11. The circuit of claim 10, said charge receiving block (CRB) comprising at least one capacitor (CX2, CXX1, CXX2, CY2).

12. The circuit of one of the claims 10 or 11, said charge receiving block (CRB) comprising an integrator.

13. The circuit of one of the claims 10 or 12, said charge receiving block (CRB) comprising a differential latch.

14. The circuit of one of the claims 10 or 13, comprising a charge transfer amplifier.

15. The circuit of claim 14, being a cascade of charge transfer amplifiers.

16. The circuit of one of the claims 1 to 15, wherein at least part of said input signal (Vin) is transferred to said storage element (C, CH1,

CH2, CD, CX1, CXA, CXB, CY1) over said non-linear element (T, D, TXN, TYN), said transfer being interrupted prior to achieving the required accuracy, and wherein said required accuracy is recovered by treating reference signals in a similar way and deriving the required correction from the result of treating the reference signals.

17. The circuit of one of the claims 1 to 16, said at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) holding a signal being a measure of said input signal, said held signal being read out without a buffer and where the deterministic part of the deterioration of said held signal due to this way of readout is corrected by treating reference signals in a similar way.

18. The circuit of one of the claims 16 or 17 where said reference signals are transferred to storage elements similar to said at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1).

19. The circuit of one of the claims 1 to 18, wherein a signal held on said at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) is incrementally applied to the subsequent circuitry in several succeeding phases to allow said subsequent circuitry to operate on signals of reduced range.

20. The circuit of claim 19, wherein said at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) is split into several elements, each corresponding to one of said several succeeding phases and storing the fraction of the signal incrementally applied to said subsequent circuitry during said one of said several succeeding phases.

21. The circuit of one of the claims 19 or 20, where a reduced range or a constant full range is obtained by injecting during said succeeding phases an estimate of said input signal (Vin) with the appropriate sign to obtain a residue corresponding to said reduced range or constant full range.

22. The circuit of claim 21, wherein said estimate is generated using a digital-to-analog converter.

23. The circuit of one of the claims 19 to 22, wherein an estimate of the signal on the storage element can be subtracted from the signal on the storage element to form a residue which is injected into the subsequent circuitry already during a first injection phase.

24. An analog-to-digital converter comprising a circuit according to one of the claims 1 to 23.

25. The analog-to-digital converter of claim 24, being of the successive approximation type.

26. The analog-to-digital converter of claim 24, being of the pipelined type.

27. A circuit comprising at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) for holding a signal being a measure of an input signal (Vin), wherein the transfer of said signal to be held to said at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) is interrupted prior to achieving the required accuracy, and wherein said required accuracy is recovered by treating reference signals in a similar way as said input signal (Vin) and deriving the required correction from the result of treating said reference signals.

28. The circuit of claim 27 wherein said reference signals are transferred to storage elements similar to said at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1).

29. A circuit comprising at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) wherein a signal on said at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) being a measure of an input signal (Vin) is incrementally applied to a subsequent circuitry in several succeeding phases.

30. The circuit of claim 29 allowing said subsequent circuitry to operate on signals of reduced range.

31. The circuit of claim 29 allowing said subsequent circuitry to operate on signals of constant full range.

32. The circuit of one of the claims 30 or 31, wherein said reduced range or said constant full range is obtained by injecting during said succeeding phases an estimate of said input signal (Vin) with the appropriate sign to obtain a residue corresponding to said reduced range or said constant full range.

33. The circuit of claim 32, wherein said estimate is generated using a digital-to-analog converter.

34. The circuit of one of the claims 29 to 33, wherein said at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) is split into several elements each corresponding to one of said several succeeding phases and storing a fraction of said signal incrementally applied to said subsequent circuitry during said one of said several succeeding phases.

35. The circuit according claims 29 to 34 wherein an estimate of said signal on said at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) can be subtracted from said signal on said at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) to form a residue which is injected into said subsequent circuitry already during a first injection phase.

36. A circuit comprising at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) wherein a signal held on said at least one storage element (C, CH1, CH2, CD, CX1, CXA, CXB, CY1) is read out without a buffer and wherein the deterministic part of the deterioration of said signal due to this way of readout is corrected by treating reference signals in a similar way.

37. The circuit of claim 36 wherein said reference signals are held on storage elements similar to said at least one storage element.

38. The circuit of one of the claims 29 to 37 wherein said at least one storage element comprises a capacitor (C, CH1, CH2, CD, CX1, CXA, CXB, CY1).

39. The circuit of one of the claims 29 to 38 being a charge transfer amplifier.

40. The circuit of one of the claims 29 to 38 being a cascade of charge transfer amplifiers.

41. The circuit of one of the claims 29 to 38 being a sample and hold or track and hold circuit.

42. An analog-to-digital converter comprising the circuit of claim 41.

43. The analog-to-digital converter of claim 42 being of the successive approximation type.

44. The analog-to-digital converter of claim 42 being of the pipelined type.