CN107911118A - A kind of multi-channel sampling tracking keeps equipment and signal sampling method - Google Patents
A kind of multi-channel sampling tracking keeps equipment and signal sampling method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract
The present invention discloses a kind of multi-channel sampling tracking and keeps equipment, including：Power-devided circuit, is provided with an input terminal and multiple output terminals；Multi-channel sampling track and hold circuit, is provided with plurality of passages, and each passage is provided with a sub-sampling track and hold circuit, each output terminal of the power-devided circuit is connected with a sub-sampling track and hold circuit respectively；Multi-phase clock generation circuit, while be connected with each sub-sampling track and hold circuit, and the clock signal intervals transmitted to adjacent two sub-sampling track and hold circuits are equal.The present invention can not improve chip exterior sample clock frequency or without chip exterior sampling clock in the case of realize to the high frequency sampling of former high speed signal, high request will not be produced to the analog-digital converter being followed by.
Description
Technical field
The present invention relates to signal sampling field, and in particular to a kind of multi-channel sampling tracking keeps equipment and signal sampling side
Method.
Background technology
It is more and more for the process demand of high-speed high frequency signal with the development of high-speed high frequency circuit, including high speed mould
Chip demand including number converter is also increasing, and it is that analog-digital converter chip front end is common to sample track and hold circuit
Modular circuit, its performance indicator directly influence the quantified precision of analog-digital converter.High-speed high frequency signal processing needs to pass through first
After over-sampling track and hold circuit, then it is input in analog-digital converter and handles.Sample for high speed signal, mainly use at present
Scheme is realized by improving sample clock frequency, using newest technological process, can realize adopting for up to tens Gbps
Sample rate.
But had very using the processing speed of analog-digital converter of the sampling track and hold circuit of high clock frequency to being followed by
High requirement, of high cost, difficulty is big.
The content of the invention
In view of this, the application provides a kind of multi-channel sampling tracking and keeps equipment and signal sampling method, it will at a high speed
Wait that the number of accepting and believing is divided into multichannel branch signal by power-devided circuit, then by multi-channel sampling track and hold circuit to per branch all the way
Signal is sampled, and by increasing multi-phase clock generation circuit on the basis of original sample circuit, thus can be not
Improve chip exterior sample clock frequency or without chip exterior sampling clock in the case of realize to the height of former high speed signal
Frequency sampling, will not produce high request to the analog-digital converter being followed by.To solve above technical problem, technical side provided by the invention
Case is as follows：
A kind of multi-channel sampling tracking keeps equipment, including：
Power-devided circuit, is provided with an input terminal and multiple output terminals；
Multi-channel sampling track and hold circuit, is provided with plurality of passages, and each passage is provided with a sub-sampling tracking
Holding circuit, each output terminal of the power-devided circuit are connected with a sub-sampling track and hold circuit respectively；
Multi-phase clock generation circuit, while be connected with each sub-sampling track and hold circuit, and adopted to adjacent two strip
The clock signal intervals of sample track and hold circuit transmission are equal.
Further, the multi-phase clock generation circuit is L grades of multi-phase clock generation circuits, wherein, L >=1, first order
The input terminal of clock generation circuit be the multi-phase clock generation circuit input terminal, the output of L grades of sub-clock generation circuits
Hold and produced for the output terminal of the multi-phase clock generation circuit, output terminal and the rear stage sub-clock of previous stage sub-clock generation circuit
The input terminal connection of raw circuit.Need exist for explanation, L grade multi-phase clock generation circuits be L strips clock generation circuit according to
Secondary connection, the first strip clock generation circuit are first order multi-phase clock generation circuit, and L strip clock generation circuits are
L grades of multi-phase clock generation circuits.
Further, the sub-clock generation circuit includes N number of resistance and N number of capacitance, N number of resistance and N number of capacitance
It is sequentially connected in series by 2N bar connecting lines, closed loop is formed after the completion of connection, wherein, an electricity is in series between each two resistance
Hold, a resistance, the port number of N >=multi-channel sampling track and hold circuit are in series between each two capacitance；
The first order sub-clock generation circuit is including by two input terminals drawn on connecting line and by drawing on connecting line
The N number of output terminal gone out, the remaining N number of input terminal included per level-one sub-clock generation circuit by being drawn on connecting line and N number of
Output terminal, the connecting line where the input terminal and output terminal of every grade of sub-clock generation circuit is differing from each other, every grade of period of the day from 11 p.m. to 1 a.m
Include between the adjacent output terminal of clock generation circuit and only include a resistance and a capacitance.Explanation is needed exist for, it is more
The clock number of phases of phase clock generation circuit is N phase clock generation circuits, during the specific implementation present invention, usually make the value of N with it is more
The port number of channel sample track and hold circuit is equal, alternatively, it is also possible to allow the passages of N ＞ multi-channel sampling track and hold circuits
Number, the purpose so set are, when needing the port number of appropriate increase sampling track and hold circuit in the later stage, it is not necessary to multiphase
Clock generation circuit is separately altered, flexibly and easily.
Further, the series of the multi-phase clock generation circuit is three-level or level Four or Pyatyi.
Further, the sub-sampling track and hold circuit includes：
Input buffer amplifier of the input terminal as the input terminal of the sub-sampling track and hold circuit；
The first resistor of the output terminal of one end and input buffer amplifier connection；
The holding switch of the output terminal of one end and input buffer amplifier connection, it is described to keep switch to be produced according to multi-phase clock
The output signal of raw circuit is turned off and closed；
Anode is grounded, the first power supply of the other end connection of cathode connection input buffer amplifier opposite with first resistor；
Plus earth, anode and the second source for keeping the opposite other end connection for being connected input buffer amplifier of switch；
The tracking switch that one end is connected with second source anode, the tracking switch is according to the defeated of multi-phase clock generation circuit
Go out signal to turn off and close；
The output terminal of basis set and input buffer amplifier connects, and collector is connected with the cathode of the first power supply, emitter and
The triode of the other end connection of the opposite connection second source of tracking switch；
One end is grounded, the sampling capacitance that the other end is connected with the emitter of the triode；
Input terminal is connected with the emitter of the triode, output of the output terminal as the sub-sampling track and hold circuit
The output buffer amplifier at end.
Further, also it is in series with slow wave between every sub-sampling track and hold circuit and multi-phase clock generation circuit
Phase modulation circuit.
Further, the slow wave phase modulation circuit includes first group of grounded metal, second group of grounded metal, the 3rd group of ground connection
Metal, the 4th group of grounded metal and a signal wire：
First group of grounded metal is concatenated by the source electrode and drain electrode of first group of metal-oxide-semiconductor with second group of grounded metal；
Second group of grounded metal is concatenated by the source electrode and drain electrode of second group of metal-oxide-semiconductor with the 3rd group of grounded metal；
The grid of first group of metal-oxide-semiconductor and second group of metal-oxide-semiconductor is circumscribed with the 3rd power supply；
The 4th group of grounded metal is connected with first group of grounded metal and the 3rd group of grounded metal at the same time, and first group connects
Ground metal, second group of grounded metal and the 3rd group of grounded metal are respectively positioned on the lower section of the 4th group of grounded metal；
The signal wire is between the top of second group of grounded metal and the bottom of the 4th group of grounded metal, and signal wire
Both ends respectively as the slow wave phase modulation circuit input terminal and output terminal.
Further, every sub-sampling track and hold circuit and multi-phase clock generation circuit are wrapped up using metal.
The present invention also provides a kind of method for being tracked with above-mentioned multi-channel sampling and keeping equipment to carry out signal sampling, including：
It will wait that the number of accepting and believing is divided into multichannel branch and waits the number of accepting and believing by power-devided circuit；
It will wait that the number of accepting and believing sends multi-channel sampling track and hold circuit to per branch all the way, wherein, branch is waited to accept and believe all the way
A number corresponding sub-sampling track and hold circuit；
By multi-channel sampling track and hold circuit to waiting that the number of accepting and believing samples per branch all the way, wherein, each strip
The clock signal for sampling track and hold circuit is produced by same multi-phase clock generation circuit, and adjacent two-way branch waits that the number of accepting and believing is right
The clock signal intervals that the two sub-sampling track and hold circuits answered receive are equal.
Further, by multi-channel sampling track and hold circuit to waiting that the number of accepting and believing carries out sampling specific bag per branch all the way
Include：
Multi-phase clock signal is obtained by multi-phase clock generation circuit, wherein, the adjacent two phase clock sigtnal interval is equal；
To the first clock signal carry out slow wave phase modulation then by the first clock signal send to first sub-sampling with
Track holding circuit；
The first clock signal received to first sub-sampling track and hold circuit carries out electrical level judging, if received
The first clock signal arrived is high level, carries out step A, if the first clock signal received is low level, is carried out
Step B；
Step A：Received branch is docked by first sub-sampling track and hold circuit and waits that the number of accepting and believing carries out sampling holding；
Step B：Received branch is docked by first sub-sampling track and hold circuit and waits that the number of accepting and believing carries out sampling tracking；
To the second clock signal carry out slow wave phase modulation then by the second clock signal send to Article 2 sub-sampling with
Track holding circuit；
The second clock signal received to Article 2 sub-sampling track and hold circuit carries out electrical level judging, if received
The second clock signal arrived is high level, carries out step C, if the second clock signal received is low level, is carried out
Step D；
Step C：Received branch is docked by Article 2 sub-sampling track and hold circuit and waits that the number of accepting and believing carries out sampling holding；
Step D：Received branch is docked by Article 2 sub-sampling track and hold circuit and waits that the number of accepting and believing carries out sampling tracking；
And so on, the sampling for the number of accepting and believing is waited until completing every branch all the way, wherein, between the adjacent two phase clock signal
Every equal.
A kind of multi-channel sampling tracking provided by the invention keeps equipment, it will wait that the number of accepting and believing passes through power-devided circuit point at a high speed
For multiple signals, then by multi-channel sampling track and hold circuit to being sampled per tributary signal all the way, and the present invention exists
Increase multi-phase clock generation circuit on the basis of original sampling hold circuit, multi-phase clock generation circuit can control sample circuit
In the different time to being sampled per signal all the way, for per signal all the way, sample frequency is not high, but adjacent two-way
The sampling time of signal is different and interval is equal, specifically, per the sample frequency of signal all the way and the product of signalling channel number
The as sample frequency of high speed signal, so as to fulfill the mesh to the high sampling rate of high speed signal is completed with low sample clock frequency
, thus can not improve chip exterior sample clock frequency or without chip exterior sampling clock in the case of realize
To the high frequency sampling of former high speed signal, high request will not be produced to the analog-digital converter being followed by.In addition, multi-phase clock generation circuit
The form cascaded using a plurality of sub-clock generation circuit can realize high phase place precision, but the bar number of sub-clock generation circuit is got over
More, circuit loss is bigger, therefore is weighed the advantages and disadvantages according to actual conditions, selects the level bracing of most suitable sub-clock generation circuit
Number, by experiment, three to five proper；What the slow wave phase modulation circuit of addition can produce multi-phase clock generation circuit
Clock signal carries out phase adjusted, improves sampling precision；Every sampling track and hold circuit and multi-phase clock generation circuit is equal
Wrapped up using metal, the isolation between signal can be strengthened, improve the antijamming capability of circuit.
Brief description of the drawings
Fig. 1 is the structural schematic block diagram that four-way sampling tracking keeps equipment.
Fig. 2 is the structure diagram of four phase clock generation circuit of three-level.
Fig. 3 is clock distribution schematic diagram when four-way samples.
Fig. 4 is the circuit structure diagram of a sub-sampling track and hold circuit.
Fig. 5 is the front view of slow wave phase modulation circuit.
Fig. 6 is the bottom view of slow wave phase modulation circuit.
Reference numeral：R1-first resistor, C1-sampling capacitance, D1-triode, A1-input buffer amplifier, A2-
Output buffer amplifier, K1-holding switch, K2-tracking switch, the power supplys of U1-first, the electricity of U2-second source, U3 the-the 3rd
Source, J1-the first group grounded metal, J2-the second group grounded metal, J3-three group grounded metal, J4-four group ground connection gold
Belong to, T1-the first group metal-oxide-semiconductor, T2-the second group metal-oxide-semiconductor, P-signal wire.
Embodiment
It is below in conjunction with the accompanying drawings and specific real in order to make those skilled in the art more fully understand technical scheme
Applying example, the present invention is described in further detail.
Embodiment 1
Tracked the present embodiment provides a kind of multi-channel sampling and keep equipment, including：Power-devided circuit, is provided with an input terminal
With multiple output terminals；Multi-channel sampling track and hold circuit, is provided with plurality of passages, and each passage is provided with a sub-sampling
Track and hold circuit, each output terminal of the power-devided circuit are connected with a sub-sampling track and hold circuit respectively；Multiphase
Clock generation circuit, while be connected with each sub-sampling track and hold circuit, and tracked to adjacent two sub-samplings and keep electricity
The clock signal intervals of road transmission are equal.
In the present embodiment, can also connect slow wave between every sub-sampling track and hold circuit and multi-phase clock generation circuit
Phase modulation circuit, and every sub-sampling track and hold circuit and multi-phase clock generation circuit are wrapped up using metal.
Wherein, multi-phase clock generation circuit is L grades of multi-phase clock generation circuits, wherein, L >=1, first order sub-clock produces
The input terminal of circuit is the input terminal of the multi-phase clock generation circuit, and the output terminal of L grades of sub-clock generation circuits is described
The output terminal of multi-phase clock generation circuit, output terminal and the rear stage sub-clock generation circuit of previous stage sub-clock generation circuit
Input terminal connects.
Specifically, sub-clock generation circuit includes N number of resistance and N number of capacitance, and N number of resistance and N number of capacitance pass through 2N
Bar connecting line is sequentially connected in series, and closed loop is formed after the completion of connection, wherein, a capacitance is in series between each two resistance, often
A resistance, the port number of N >=multi-channel sampling track and hold circuit are in series between two capacitances.
Specifically, first order sub-clock generation circuit is including by two input terminals drawn on connecting line and by connecting line
The N number of output terminal drawn, the remaining N number of input terminal and N included per level-one sub-clock generation circuit by being drawn on connecting line
A output terminal, the connecting line where the input terminal and output terminal of every grade of sub-clock generation circuit is differing from each other, every grade of son
Include between the adjacent output terminal of clock generation circuit and only include a resistance and a capacitance.
Specifically, as shown in figure 4, sub-sampling track and hold circuit includes：
Input buffer amplifier A1 of the input terminal as sub-sampling track and hold circuit input terminal；
The first resistor R1 that one end is connected with the output terminal of input buffer amplifier A1；
The holding switch K1 that one end is connected with the output terminal of input buffer amplifier A1, the holding switch K1 is according to multiphase
The output signal of clock generation circuit is turned off and closed；
Anode is grounded, the first electricity of the other end connection of cathode connection input buffer amplifier A1 opposite with first resistor R1
Source U1；
Plus earth, the second electricity of the other end connection of anode connection input buffer amplifier A1 opposite with keeping switch K1
Source U2；
Tracking the switch K2, the tracking switch K2 that one end is connected with second source U2 anode produce electricity according to multi-phase clock
The output signal on road is turned off and closed；
Basis set is connected with the output terminal of input buffer amplifier A1, and collector is connected with the cathode of the first power supply U1, transmitting
The triode D1 of the other end connection of pole connection second source U2 opposite with tracking switch K2；
One end is grounded, the sampling capacitance C1 that the other end is connected with the emitter of the triode D1；
Input terminal is connected with the emitter of the triode D1, output terminal of the output terminal as sub-sampling track and hold circuit
Output buffer amplifier A2.
Specifically, as shown in Figure 5 and Figure 6, slow wave phase modulation circuit includes first group of grounded metal J1, second group of grounded metal
J2, the 3rd group of grounded metal J3, the 4th group of grounded metal J4 and a signal wire P：
First group of grounded metal J1 is concatenated by the source electrode and drain electrode of first group of metal-oxide-semiconductor T1 with second group of grounded metal J2；
Second group of grounded metal J2 is concatenated by the source electrode and drain electrode of second group of metal-oxide-semiconductor T2 with the 3rd group of grounded metal J3；
The grid of first group of metal-oxide-semiconductor T1 and second group of metal-oxide-semiconductor T2 is circumscribed with a 3rd power supply U3；
4th group of grounded metal J4 is connected with first group of grounded metal J1 and the 3rd group of grounded metal J3 at the same time, and first group
Grounded metal J1, second group of grounded metal J2 and the 3rd group of grounded metal J3 are respectively positioned on the lower section of the 4th group of grounded metal J4；
Signal wire P is between the top of second group of grounded metal J2 and the bottom of the 4th group of grounded metal J4, and signal
Input terminal and output terminal of the both ends of line P respectively as slow wave phase modulation circuit.
Wherein, first group of metal-oxide-semiconductor and second group of metal-oxide-semiconductor are N-channel MOS pipe.
, it is necessary to which the high speed signal of sampling is divided into multichannel branch by power-devided circuit network and waits to accept and believe when implementing the present embodiment
Number, then it will wait that the number of accepting and believing is separately input to the sub-sampling track and hold circuit being connected with power-devided circuit output terminal per branch all the way
In, the input signal of multi-phase clock generation circuit is external differential clock signal, is finally produced by multi-phase clock generation circuit
Multi-phase clock signal, the sub-sampling track and hold circuit that each is connected with power-devided circuit output terminal receive multi-phase clock and produce electricity
The clock signal that road produces, and according to the clock signal break it is open and close keep switching and tracking switchs, multichannel adopts
The operation principle of sample track and hold circuit is as follows：During tracking mode, tracking switch K2 closures, keep switch K1 to disconnect, triode
D1 is turned on, and the voltage at sampling capacitance C1 both ends changes with the change of input voltage, and is exported by output buffer amplifier A2,
So as to carry out tracking sampling to high speed signal；During hold mode, tracking switch K2 is disconnected, and keeps switch K1 closures, first resistor
Larger pressure drop is produced on R1, triode D1 cut-offs, sampling capacitance C1 is without discharge and recharge, and the both end voltage of sampling capacitance C1 is not
Become, keep current voltage, realize and keep function.Due to being produced with what each sub-sampling track and hold circuit was connected by multi-phase clock
The clock signal phase that raw circuit produces is different, therefore also different to the time point per the sampling of high speed signal all the way, although
For certain road high speed signal, sample clock frequency does not improve, but the sampling time of adjacent two paths of signals is different, so that real
Current low sample clock frequency completes the purpose to the high sampling rate of high speed signal, can thus be adopted not improving chip exterior
Sample clock frequency or without chip exterior sampling clock in the case of realize to the high frequency sampling of former high speed signal, will not be to rear
The analog-digital converter connect produces high request.
When it is implemented, waiting that the sample frequency for the number of accepting and believing is identical per branch all the way, the sampling for the number of accepting and believing is waited per branch all the way
The product of frequency and way is the sample frequency that high speed signal needs.
In order to embody the present embodiment, sampled exemplified by tracking keeps equipment be further described by four-way below,
In the present embodiment, four-way sampling tracking is kept in equipment, and clock sampling track and hold circuit is four phase clock generation circuits, is adopted
Sample track and hold circuit samples track and hold circuit, including 4 sub-sampling track and hold circuits for four-way, and four phase clocks produce
Circuit is four phase clock generation circuit of three-level, and each clock signal can be tracked by slow wave phase modulation circuit and a sub-sampling
Holding circuit connects.
Specifically, as shown in Figure 1, the dotted line in figure represents clock signal trend, solid line is expressed as being moved towards by the number of accepting and believing.Four
Channel sample track and hold circuit includes：
One power-devided circuit with four output terminals；
Four sampling track and hold circuits with an output terminal and two input terminals, each sampling tracking keep electricity
First input terminal on road and an output terminal of power-devided circuit connect；
The slow wave phase modulation circuit that four output terminals are connected with second input terminal of four sampling track and hold circuits respectively；
Four phase clock generation circuits of one input termination differential clock signal, four phases that four phase clock generation circuits produce
Clock signal is respectively transmitted to the input terminal of four slow wave phase modulation circuits.
Wherein, as shown in Fig. 2, four phase clock generation circuits are four phase clock generation circuit of three-level, including three sub-clocks
Generation circuit, each sub-clock generation circuit includes four resistance and four capacitances, and each sub-clock generation circuit is set
Four output terminals are equipped with, the four tunnel clock signals which produces are respectively 0 ° of clock signal, 90 ° of clock letters
Number, 180 ° of clock signals and 270 ° of clock signals.
As shown in figure 3, when being sampled to high speed signal, if the repetition pulse that the high speed signal before work(point is 32GHz,
So under the distribution of four phase clock generation circuits, it is only necessary to 8GHz is reached just to the sample frequency per high speed signal all the way,
Can thus achieve the purpose that core can also be not being improved to the high sampling rate of high speed signal with the completion of low sample clock frequency
Piece external sampling clock frequency or without chip exterior sampling clock in the case of realize to the high frequency sampling of former high speed signal,
High request will not be produced to the analog-digital converter being followed by.
When it is implemented, power-devided circuit can sample T-shaped power division network figure, by one-to-two, two point four of topological structure,
And suitable line characteristic impedance is selected, it can realize preferable bandwidth allocation, the sub-clock production of multi-phase clock generation circuit
Raw circuit bar is several to be reasonably selected according to actual conditions.
Embodiment 2
The present embodiment provides the multi-channel sampling that a kind of signal sampling method, the signal sampling method are provided with embodiment 1
Tracking keeps equipment to carry out signal sampling, including：
It will wait that the number of accepting and believing is divided into multichannel branch and waits the number of accepting and believing by power-devided circuit；
It will wait that the number of accepting and believing sends multi-channel sampling track and hold circuit to per branch all the way, wherein, branch is waited to accept and believe all the way
A number corresponding sub-sampling track and hold circuit；
By multi-channel sampling track and hold circuit to waiting that the number of accepting and believing samples per branch all the way, wherein, each strip
The clock signal for sampling track and hold circuit is produced by same multi-phase clock generation circuit, and adjacent two-way branch waits that the number of accepting and believing is right
The clock signal intervals that the two sub-sampling track and hold circuits answered receive are equal.
Specifically, by multi-channel sampling track and hold circuit to waiting that the number of accepting and believing carries out sampling specific bag per branch all the way
Include：
Multi-phase clock signal is obtained by multi-phase clock generation circuit, wherein, the adjacent two phase clock sigtnal interval is equal；
To the first clock signal carry out slow wave phase modulation then by the first clock signal send to first sub-sampling with
Track holding circuit；
The first clock signal received to first sub-sampling track and hold circuit carries out electrical level judging, if received
The first clock signal arrived is high level, carries out step A, if the first clock signal received is low level, is carried out
Step B；
Step A：Received branch is docked by first sub-sampling track and hold circuit and waits that the number of accepting and believing carries out sampling holding；
Step B：Received branch is docked by first sub-sampling track and hold circuit and waits that the number of accepting and believing carries out sampling tracking；
To the second clock signal carry out slow wave phase modulation then by the second clock signal send to Article 2 sub-sampling with
Track holding circuit；
The second clock signal received to Article 2 sub-sampling track and hold circuit carries out electrical level judging, if received
The second clock signal arrived is high level, carries out step C, if the second clock signal received is low level, is carried out
Step D；
Step C：Received branch is docked by Article 2 sub-sampling track and hold circuit and waits that the number of accepting and believing carries out sampling holding；
Step D：Received branch is docked by Article 2 sub-sampling track and hold circuit and waits that the number of accepting and believing carries out sampling tracking；
And so on, the sampling for the number of accepting and believing, the adjacent two phase clock sigtnal interval phase are waited until completing every branch all the way
Deng.
It the above is only the preferred embodiment of the present invention, it is noted that above-mentioned preferred embodiment is not construed as pair
The limitation of the present invention, protection scope of the present invention should be subject to claim limited range.For the art
For those of ordinary skill, without departing from the spirit and scope of the present invention, some improvements and modifications can also be made, these change
Protection scope of the present invention is also should be regarded as into retouching.
Claims (10)
1. a kind of multi-channel sampling tracking keeps equipment, it is characterised in that including：
Power-devided circuit, is provided with an input terminal and multiple output terminals；
Multi-channel sampling track and hold circuit, is provided with plurality of passages, and each passage is provided with a sub-sampling tracking and keeps
Circuit, each output terminal of the power-devided circuit are connected with a sub-sampling track and hold circuit respectively；
Multi-phase clock generation circuit, while be connected with each sub-sampling track and hold circuit, and to adjacent two sub-samplings with
The clock signal intervals of track holding circuit transmission are equal.
2. a kind of multi-channel sampling tracking according to claim 1 keeps equipment, it is characterised in that the multi-phase clock production
Raw circuit is L grades of multi-phase clock generation circuits, wherein, L >=1, the input terminal of first order sub-clock generation circuit is the multiphase
The input terminal of clock generation circuit, the output terminal of L grades of sub-clock generation circuits are the output of the multi-phase clock generation circuit
End, the output terminal of previous stage sub-clock generation circuit are connected with the input terminal of rear stage sub-clock generation circuit.
3. a kind of multi-channel sampling tracking according to claim 2 keeps equipment, it is characterised in that
The sub-clock generation circuit includes N number of resistance and N number of capacitance, and N number of resistance and N number of capacitance pass through 2N bar connecting lines
It is sequentially connected in series, closed loop is formed after the completion of connection, wherein, a capacitance, each two capacitance are in series between each two resistance
Between be in series with a resistance, the port number of N >=multi-channel sampling track and hold circuit；
The first order sub-clock generation circuit is included by two input terminals drawn on connecting line and the N by being drawn on connecting line
A output terminal, it is remaining to include per level-one sub-clock generation circuit by the N number of input terminal drawn on connecting line and N number of output
End, the connecting line where the input terminal and output terminal of every grade of sub-clock generation circuit is differing from each other, every grade of sub-clock production
Include between the adjacent output terminal of raw circuit and only include a resistance and a capacitance.
4. a kind of multi-channel sampling tracking according to Claims 2 or 3 keeps equipment, it is characterised in that during the multiphase
The series of clock generation circuit is three-level or level Four or Pyatyi.
5. a kind of multi-channel sampling tracking according to claim 1 keeps equipment, it is characterised in that the sub-sampling tracking
Holding circuit includes：
Input buffer amplifier (A1) of the input terminal as the input terminal of the sub-sampling track and hold circuit；
The first resistor (R1) that one end is connected with the output terminal of input buffer amplifier (A1)；
The holding switch (K1) that one end is connected with the output terminal of input buffer amplifier (A1), it is described to keep switch (K1) according to more
The output signal of phase clock generation circuit is turned off and closed；
Anode is grounded, the first electricity of the cathode other end connection for being connected input buffer amplifier (A1) opposite with first resistor (R1)
Source (U1)；
Plus earth, anode and the second electricity for keeping the opposite other end connection for being connected input buffer amplifier (A1) of switch (K1)
Source (U2)；
The tracking switch (K2) that one end is connected with second source (U2) anode, the tracking switch (K2) produce according to multi-phase clock
The output signal of circuit is turned off and closed；
Basis set is connected with the output terminal of input buffer amplifier (A1), and collector is connected with the cathode of the first power supply (U1), transmitting
The triode (D1) of the pole other end connection for being connected second source (U2) opposite with tracking switch (K2)；
One end is grounded, the sampling capacitance (C1) that the other end is connected with the emitter of the triode (D1)；
Input terminal is connected with the emitter of the triode (D1), output of the output terminal as the sub-sampling track and hold circuit
The output buffer amplifier (A2) at end.
6. a kind of multi-channel sampling tracking according to claim 1 keeps equipment, it is characterised in that every sub-sampling
Slow wave phase modulation circuit is also in series between track and hold circuit and multi-phase clock generation circuit.
7. a kind of multi-channel sampling tracking according to claim 6 keeps equipment, it is characterised in that the slow wave phase modulation electricity
Road includes first group of grounded metal (J1), second group of grounded metal (J2), the 3rd group of grounded metal (J3), the 4th group of grounded metal
(J4) and a signal wire (P)：
First group of grounded metal (J1) passes through the source electrode of first group of metal-oxide-semiconductor (T1) and drain electrode and second group of grounded metal (J2)
Concatenation；The source electrode and drain electrode and the 3rd group of grounded metal that second group of grounded metal (J2) passes through second group of metal-oxide-semiconductor (T2)
(J3) concatenate；The grid of first group of metal-oxide-semiconductor (T1) and second group of metal-oxide-semiconductor (T2) is circumscribed with the 3rd power supply (U3)；
The 4th group of grounded metal (J4) while it is connected with first group of grounded metal (J1) and the 3rd group of grounded metal (J3), and
First group of grounded metal (J1), second group of grounded metal (J2) and the 3rd group of grounded metal (J3) are respectively positioned on the 4th group of grounded metal
(J4) lower section；
The signal wire (P) between the top of second group of grounded metal (J2) and the bottom of the 4th group of grounded metal (J4),
And the both ends of signal wire (P) are respectively as the input terminal and output terminal of the slow wave phase modulation circuit.
8. a kind of multi-channel sampling tracking according to claim 1 keeps equipment, it is characterised in that every sub-sampling
Track and hold circuit and multi-phase clock generation circuit are wrapped up using metal.
9. a kind of method that a kind of multi-channel sampling tracking with described in claim 1 keeps equipment to carry out signal sampling, it is special
Sign is, including：
It will wait that the number of accepting and believing is divided into multichannel branch and waits the number of accepting and believing by power-devided circuit；
It will wait that the number of accepting and believing sends multi-channel sampling track and hold circuit to per branch all the way, wherein, branch waits that the number of accepting and believing is right all the way
Answer a sub-sampling track and hold circuit；
By multi-channel sampling track and hold circuit to waiting that the number of accepting and believing samples per branch all the way, wherein, each sub-sampling
The clock signal of track and hold circuit is produced by same multi-phase clock generation circuit, and adjacent two-way branch waits that the number of accepting and believing is corresponding
The clock signal intervals that two sub-sampling track and hold circuits receive are equal.
10. a kind of signal sampling method according to claim 9, it is characterised in that tracked and kept by multi-channel sampling
Circuit per branch all the way to waiting that the number of accepting and believing carries out sampling and specifically includes：
Multi-phase clock signal is obtained by multi-phase clock generation circuit, wherein, the adjacent two phase clock sigtnal interval is equal；
Slow wave phase modulation is carried out to the first clock signal and then sends the first clock signal to first sub-sampling tracking protecting
Hold circuit；
The first clock signal received to first sub-sampling track and hold circuit carries out electrical level judging, if receive
First clock signal is high level, carries out step A, if the first clock signal received is low level, carries out step
B；
Step A：Received branch is docked by first sub-sampling track and hold circuit and waits that the number of accepting and believing carries out sampling holding；
Step B：Received branch is docked by first sub-sampling track and hold circuit and waits that the number of accepting and believing carries out sampling tracking；
Slow wave phase modulation is carried out to the second clock signal and then sends the second clock signal the tracking of to Article 2 sub-sampling protecting
Hold circuit；
The second clock signal received to Article 2 sub-sampling track and hold circuit carries out electrical level judging, if receive
Second clock signal is high level, carries out step C, if the second clock signal received is low level, carries out step
D；
Step C：Received branch is docked by Article 2 sub-sampling track and hold circuit and waits that the number of accepting and believing carries out sampling holding；
Step D：Received branch is docked by Article 2 sub-sampling track and hold circuit and waits that the number of accepting and believing carries out sampling tracking；
And so on, the sampling for the number of accepting and believing is waited until completing every branch all the way, the adjacent two phase clock sigtnal interval is equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711295055.XA CN107911118A (en) | 2017-12-08 | 2017-12-08 | A kind of multi-channel sampling tracking keeps equipment and signal sampling method |
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|---|---|---|---|
| CN201711295055.XA CN107911118A (en) | 2017-12-08 | 2017-12-08 | A kind of multi-channel sampling tracking keeps equipment and signal sampling method |
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| CN107911118A true CN107911118A (en) | 2018-04-13 |
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