WO2004049453A1

WO2004049453A1 - Retrograde channel doping to improve short channel effect

Info

Publication number: WO2004049453A1
Application number: PCT/US2003/021682
Authority: WO
Inventors: Wei Zheng; Zhizheng Liu; Mark W. Randolph; Yi He
Original assignee: Advanced Micro Devices Inc
Current assignee: Advanced Micro Devices Inc
Priority date: 2002-11-26
Filing date: 2003-07-10
Publication date: 2004-06-10
Anticipated expiration: 2005-05-26
Also published as: TW200409211A; AU2003259111A1

Abstract

A memory semiconductor cell (30) comprises a gate region (16), a source region (14) and a drain region (14). A channel region (17) is formed between the source region (14) and the drain region (14). The channel region (17) comprises a first channel portion (33) with a first concentration of doping material, the first channel portion (33) disposed adjacent to an edge of the channel region (17) closest to and substantially parallel to the gate region (16). The channel region (17) further comprises a second channel portion (31) with a second concentration of doping material, the second channel portion (31) disposed substantially parallel to the first channel portion (33) and a third channel portion (32), disposed between the first channel portion (33) and the second channel portion (31), with a third concentration of doping material. The third concentration is lower than the first concentration and lower than the second concentration. The memory cell may be one of two general types of non-volatile memory, a floating gate cell or a nitride read only memory (NROM), whereby layer (12B) in a floating gate or a nitride layer respectively.

Description

RETROGRADE CHANNELDOPING TOIMPROVE SHORT CHANNEL EFFECT

TECHNICAL FIELD Embodiments of the present inventio relate to design of sub-micron metal oxide semiconductors. More particularly, embodiments of the present invention provide retrograde channel doping to improve the short channel effect.

BACKGROUND ART

Figure 1 shows a memory cell 10 as has been well known in the conventional art. Regions 14 are the drain and/or source regions for memory cell 10. They may be used as source and/or drain interchangeably. Control gate 16 is used to control the operation of memory cell 10. A channel region 17 is formed between source/drain regions 14. Feature size 18 is the nominal size of the smallest feature that can be created by a particular semiconductor process. In memory cells of this type, the gate 16 width and channel 17 length typically correspond approximately to feature size 18. Memory cell 10 may also have a source/drain extension 11 structure. Source/drain extension 11 is a shallow diffusion that connects the channel 17 with the deeper source/drain 14, typically intended to prevent degradation of drive current. Memory cell 10 may be one of two general types of non- volatile memory, a "floating gate" cell or a nitride read only memory (NROM) cell. In a floating gate cell, layer 12B of the gate stack is typically conductive polysilicon. Layers 12A and 12C are insulating materials which isolate or "float" gate layer 12B, which is usually referred to as a floating gate. Floating gate 12B is the storage element of memory cell 10.

Silicon nitride based flash memory has many advantages as compared to its floating gate and tunneling oxide based counterparts. Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) is potentially very dense in terms of number of cells per unit area that can be used and it requires fewer process steps as compared to floating gate memory. Moreover, it can be easily integrated with standard SRAM process technology. A further advantage of using SONOS devices is their suitability for applications requiring large temperature variations and radiation hardening. The SONOS stack is a gate dielectric stack and consists of a single layer of polysilicon, a triple stack ONO (Oxide-Nitride-Oxide) gate dielectric layer and a MOS channel 17. The ONO structure may consist of a tunnel oxide 12A, a nitride memory storage layer 12B and a blocking oxide layer 12C.

Memory device manufacturers are continually challenged to provide ever greater amounts of memory at ever lower costs. Recently, Advanced Micro Devices, Incorporated of California has introduced MIRROR BIT ™ nitride-based flash ROM that stores multiple bits per memory cell 10 physically separated in nitride layer 12B. Such storage of multiple bits per cell increases the storage density of the memory device, thereby reducing the cost per bit of storage.

Another primary approach employed to achieve lower memory costs is the industry-wide on-going reduction in semiconductor feature size. By making features, such as signal lines and transistors smaller, more memory devices may be placed in a given die area, resulting in lower production costs. However, as feature size decreases to, for example, about 0.3 microns and smaller, the channel length also decreases. As channel length grows shorter, threshold voltage begins to decrease and leakage current increases. These effects are commonly referred to in the semiconductor arts as the "short channel effect." An increase in leakage current is particularly onerous in flash memory devices as flash has found wide acceptance in very low power applications, for example mobile phones, due to the ability of flash to retain information without applied power. Increases in leakage current may have a significant deleterious effect on total power consumption of the flash device and the product using the flash device. Consequently, much research and development effort has gone into mitigating the short channel effect.

Prior art approaches to improve leakage current and reduce the short channel effect include, for example, "halo" doping and retrograde wells. Halo doping 20 creates a steep dopant profile at the edges of the source/drain regions, as shown in Figure 1. A conventional retrograde well has a non-uniform doping concentration that increases, for example, linearly with depth 22 in the channel region 17. The doping of a conventional retrograde well generally follows a continuous, monotonically increasing profile with no abrupt changes. Conventional retrograde wells are typically created by using a slow diffusing dopant species such as arsenic or antimony for PMOS devices and indium for NMOS devices. Both halo doping and retrograde well profiles serve to inhibit the flow of charge carriers, raising the threshold voltage and reducing leakage current for the device.

However, both halo doping and conventional retrograde wells, alone and in combination, are found to be lacking. Such prior art approaches simply do not reduce leakage current to commercially acceptable levels for flash memory at modern process feature sizes, for example, 0.17 microns and smaller.

Semiconductor processing equipment is extremely expensive. Fundamental semiconductor processing steps, e.g., doping, typically require long periods of development and extensive qualification testing. Any solution to the short channel effect should be compatible with existing semiconductor processes and equipment without the need for revamping well established tools and techniques.

Thus a need exists to prevent short channel effects in memory cells. A further need exists for preventing short channel effects in a manner that is compatible and complimentary with conventional approaches to minimize short channel effects. A still further need exists for the above mentioned needs to be achieved with existing semiconductor processes and equipment without revamping well established tools and techniques.

DISCLOSURE OF THE INVENTION Embodiments of the present invention provide a means to prevent short channel effects in memory cells. Further embodiments of the present invention prevent short channel effects in a manner that is compatible and complimentary with existing approaches to minimize short channel effects. Still further embodiments of the present invention provide for the above mentioned solutions to be achieved with existing semiconductor processes and equipment without revamping well established tools and techniques.

A memory semiconductor cell comprises a gate region, a source region and a drain region. A channel region is formed between the source region and the drain region. The channel region comprises a first channel portion with a first concentration of doping material, the first channel portion disposed adjacent to an edge of the channel region closest to and substantially parallel to the gate region. The channel region further comprises a second channel portion with a second concentration of doping material, the second portion disposed substantially parallel to the first channel portion and a third channel portion, disposed between the first channel portion and the second channel portion, with a third concentration of doping material. The third concentration is lower than the first concentration and lower than the second concentration.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a memory cell as has been well known in the conventional art.

Figure 2 illustrates a memory cell with a retrograde channel, according to an embodiment of the present invention. Figure 3 illustrates an exemplary profile of doping concentration in a channel region versus channel depth, according to an embodiment of the present invention. Figures 4A, 4B and 4C illustrate a charge carrier flow through a channel region of a memory cell, according to an embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION In the following detailed description of the present invention, retrograde channel doping to improve short channel effect, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one skilled in the art that the present invention may be practiced without these specific details or with equivalents thereof. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. RETROGRADE CHANNEL DOPING TO IMPROVE SHORT CHANNEL EFFECT

Embodiments of the present invention are described in the context of design and operation of flash memory devices. However, it is appreciated that embodiments of the present invention may be utilized in other areas of electronic design and operation.

Figure 2 illustrates a memory cell 30 with a novel retrograde channel, according to an embodiment of the present invention. The channel region comprises three portions, 31, 32 and 33. Channel portion 33 is closest to gate 16 and substantially parallel to the long axis of gate 16. Channel portion 32 is substantially parallel to channel portion 33 and at a greater depth into the substrate material than channel portion 32. Channel portion 31 is substantially parallel to channel portion 32 and at a still greater depth into the substrate material. Channel portion 32 is disposed between channel portions 31 and 33. It is appreciated that memory cell 30 is shown with source/drain extensions 11 and halo implant regions 20. Embodiments of the present invention are well suited to memory cells with or without these features. If one or both were absent, channel portions 31, 32 and 33 would extend horizontally to the halo implant or the source drain extension or the source/drain.

By well known semiconductor processing techniques, for example implantation and diffusion, channel portion 33 may be constructed and given a particular concentration of doping material. Likewise, channel portion 31 may be constructed and given a particular concentration of doping material. In general, no specific operations are performed to construct channel portion 32, rather channel portion 32 is a result of constructing portions 31 and 33 with no overlap. The bottom of channel portion 31 may be, for example, 0.1 μm from the top edge of the substrate.

According to an embodiment of the present invention, the doping concentration in both channel portion 31 and channel portion 33 is higher than the doping concentration of channel portion 32. Graph 40 of Figure 3 illustrates an exemplary profile 41 of doping concentration in a channel region versus channel depth. Channel portion 33 may have a doping concentration as depicted by profile 41 in region 33A. Channel portion 32 may have a doping concentration as depicted by profile 41 in region 32 A. Channel portion 31 may have a doping concentration as depicted by profile 41 in region 31 A. It is to be appreciated that, in contrast to conventional retrograde wells, the doping profile of this novel well is neither monotonic nor necessarily continuous, according to an embodiment of the present invention. There may be relatively abrupt (as allowed by semiconductor physics) changes in doping profile at the boundaries between channel portions, for example between channel portions 31 and 32, and between channel portions 32 and 33. In channel portions 31 and 33 charge carrier migration is hindered due to the to relatively high concentration of doping material(s). Consequently, the effective channel region is reduced to approximately channel portion 32. For example, channel portion 32 may form a "tunnel" (not to be confused with quantum effect tunneling) between channel portions 31 and 33. As a beneficial result of the reduced effective channel, threshold voltage is increased and leakage current is decreased, reducing or eliminating the short channel effect. It is to be appreciated that the depths, thickness and doping concentrations of the respective channel portions will vary according to a wide range of variables including, for example, source/drain thickness, channel length, operating voltage, doping materials and whether the device operates as a P channel or an N channel.

Channel portion 31 may be initially formed by using a slow diffusing dopant species, for example, arsenic or antimony for PMOS devices. Such a diffusion process may enable high concentrations of doping material to reach the channel depths required. Channel portion 33 may be formed by using faster diffusing dopants, e.g., boron. A shorter diffusion may produce a high concentration of doping material at relatively shallow depths in the channel region.

Figures 4A, 4B and 4C further illustrate a charge carrier flow through a channel region of memory cell 30, according to an embodiment of the present invention. In Figure 4A, charge carriers, for example, electrons 403 attempt to flow from source/drain region 401 to source/drain region 402. Electrons are impeded from flowing into channel portion 33 due to a high concentration of doping material. Likewise, electrons 405 are impeded from flowing into channel portion 31 due to a high concentration of doping material. In contrast, electrons 404 are able to overcome a relatively small energy barrier and flow into channel portion 32.

As shown in Figure 4B, electrons 403, otherwise disposed to travel horizontally (as depicted) into channel region 33, must change direction to travel around the "corner" of channel region 33 in order to enter channel region 32, wherein electrons are more able to flow. Such changes of direction require energy, resulting in a higher energy budget for electrons traversing a complex path, in contrast to electrons which may be able to travel in substantially a straight line. In addition, because region 401 is fully populated with charge carriers, e.g., electrons 404 and 405, additional energy is required to overcome the electrostatic repulsion of like charges in order to move the charge carriers closer together. As a beneficial result of the increased path length, the indirect nature of the path, as well as electrostatic repulsion, electrons 403 require more energy to travel from region 401 to 402 and consequently have a beneficially higher threshold voltage for embodiments of the present invention when compared to the prior art.

In a similar manner, electrons 405 must change direction and overcome electrostatic repulsion in order to travel into channel portion 32 from their original positions adjacent to channel portion 31. Consequently, electrons 405 have a higher threshold voltage than would otherwise be required.

Electrons 404, while disposed adjacent to channel portion 32, are also beneficially affected by embodiments of the present invention. Although electrons 404 are not obviously redirected to avoid channel portions of higher doping concentration, electrons 404 are affected by the localized increased concentration of charge carriers resulting in electrostatic forces acting upon electrons 404 in a similar manner to the electrostatic forces acting upon electrons 403 and 405.

Figure 4C shows a cumulative effect of the present retrograde channel on charge carrier flow, according to an embodiment of the present invention. Electrons in region 401 are inhibited from flowing in channel portions 33 and 31, favoring channel portion 32. However, due to the physically constrictive nature of channel portion 32 combined with electrostatic forces acting upon the like charge carriers, the electrons tend to "bunch up" at the interface between region 401 and channel portion 32. The net effect of "bunching up" is seen externally as a desirable increase in threshold voltage, and a corresponding decrease in leakage current. It is to be appreciated that although a PMOS device has been illustrated herein, embodiments of the present invention are well suited to NMOS devices as well. The choices of materials, e.g., for dopants, for use with NMOS devices are well understood in the semiconductor arts.

This novel design and method to implement this design reduce and/or eliminate the short channel effect, allowing for decreased feature size and increased density of memory cells. These beneficial results allow for less expensive memory devices with lower power consumption, rendering a competitive advantage to the users practicing embodiments of the present invention.

Embodiments of the present invention provide a means to prevent short channel effects in memory cells. Further embodiments of the present invention prevent short channel effects in a manner that is compatible and complimentary with existing approaches to minimize short channel effects. Still further embodiments of the present invention provide for the above mentioned solutions to be achieved with existing semiconductor processes and equipment without revamping well established tools and techniques.

The preferred embodiment of the present invention retrograde channel doping to improve short channel effect is thus described. While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as limited by such embodiments, but rather construed according to the below claims.

Claims

CLAIMSWhat is claimed is:

1. A method of manufacturing a memory semiconductor cell (30) comprising: forming a first channel portion (33) to produce a first concentration of doping material, said first channel portion (33) disposed adjacent to an edge of a channel region closest to and substantially parallel to a gate region (16) of said memory semiconductor cell; forming a second channel portion (31) to produce a second concentration of doping material, said second portion (31) disposed substantially parallel to said first channel portion (33); and forming a third channel portion (32), disposed between said first channel portion (33) and said second channel portion (31), comprising a third concentration of doping material, wherein said third concentration is lower than said first concentration and lower than said second concentration.

2. The method as described in Claim 1 further comprising implanting a halo implant (20) disposed adjacent to a source region or a drain region of said memory semiconductor cell (30).

3. The memory semiconductor cell (30) described in Claim 1 wherein a source region of said memory semiconductor cell comprises a source extension region (11).

4. The method as described in Claim 1 further comprising forming said second channel portion (31) prior to the formation of said first channel portion (33).

5. The method as described in Claim 1 wherein said memory semiconductor cell (30) is nonvolatile.

6. The method as described in Claim 5 wherein said memory semiconductor cell (30) comprises a nitride layer as a storage element (12B).

7. The method as described in Claim 5 wherein said memory semiconductor cell comprises a floating gate (12B) as a storage element.

8. A memory semiconductor cell (30) comprising: a gate region (16), a source region (14) and a drain region (14); a channel region (17) between said source region (14) and said drain region (14); wherein said channel region (17) comprises: a first channel portion (33) comprising a first concentration of doping material, said first channel portion (33) disposed adjacent to an edge of said channel region (17) closest to and substantially parallel to said gate region (16); a second channel portion (31) comprising a second concentration of doping material, said second portion (31) disposed substantially parallel to said first channel portion (33); and a third channel portion (32), disposed between said first channel portion (33) and said second channel portion (31), comprising a third concentration of doping material, wherein said third concentration is lower than said first concentration and lower than said second concentration.

9. The memory semiconductor cell described in Claim 8 wherein said channel region (17) further comprises a halo implant (20) disposed adjacent to said source region (14) or said drain region (14).

10. The memory semiconductor cell described in Claim 8 wherein said source region (17) comprises a source extension region (11).