[go: up one dir, main page]

WO2003030008A3 - Elektrische schaltung - Google Patents

Elektrische schaltung Download PDF

Info

Publication number
WO2003030008A3
WO2003030008A3 PCT/DE2002/003646 DE0203646W WO03030008A3 WO 2003030008 A3 WO2003030008 A3 WO 2003030008A3 DE 0203646 W DE0203646 W DE 0203646W WO 03030008 A3 WO03030008 A3 WO 03030008A3
Authority
WO
WIPO (PCT)
Prior art keywords
electrical circuit
clock signal
signal
clock
implementation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2002/003646
Other languages
English (en)
French (fr)
Other versions
WO2003030008A2 (de
Inventor
Sammy Baradie
Martin Kaibel
Andreas Weisgerber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to EP02774422A priority Critical patent/EP1464000A2/de
Priority to US10/491,070 priority patent/US7225348B2/en
Publication of WO2003030008A2 publication Critical patent/WO2003030008A2/de
Anticipated expiration legal-status Critical
Publication of WO2003030008A3 publication Critical patent/WO2003030008A3/de
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Microcomputers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Executing Machine-Instructions (AREA)
  • Electrotherapy Devices (AREA)

Abstract

Es wird eine elektrische Schaltung mit miteinander kooperierenden Komponenten beschrieben. Die beschriebene elektrische Schaltung zeichnet sich dadurch aus: dass einer Komponente der elektrischen Schaltung, die auf die Ausführung einer von einer anderen Komponente auszuführenden Aktion wartet, kurz vor der Ausführung der betreffenden Aktion mittels eines Quittierungssignals signalisiert wird, dass die Ausführung der Aktion unmittelbar bevorsteht, und/oder; dass die elektrische Schaltung einen einen Master-Taktgenerator, eine Taktsteuereinrichtung und mehrere Taktsignalerzeugungseinrichtungen enthaltenden Taktgenerator aufweist, wobei: der Master-Taktgenerator ein Master-Taktsignal erzeugt und dieses allen Taktsignalerzeugungseinrichtungen zuführt; die Taktsteuereinrichtung mehrere Freigabesignale erzeugt, und jeder Taktsignalerzeugungseinrichtung ein Freigabesignal zuführt, und; jede der Taktsignalerzeugungseinrichtungen einen durch das Freigabesignal bestimmten Teil des Master-Taktsignals passieren lässt und dieses Signal als Taktsignal an eine oder mehrere Komponenten der elektrischen Schaltung weiterleitet.
PCT/DE2002/003646 2001-09-28 2002-09-25 Elektrische schaltung Ceased WO2003030008A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP02774422A EP1464000A2 (de) 2001-09-28 2002-09-25 Elektrische schaltung
US10/491,070 US7225348B2 (en) 2001-09-28 2002-09-25 Electrical circuit having cooperating components

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10148134A DE10148134B4 (de) 2001-09-28 2001-09-28 Verfahren zur Busansteuerung
DE10148134.9 2001-09-28

Publications (2)

Publication Number Publication Date
WO2003030008A2 WO2003030008A2 (de) 2003-04-10
WO2003030008A3 true WO2003030008A3 (de) 2004-08-05

Family

ID=7700796

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/003646 Ceased WO2003030008A2 (de) 2001-09-28 2002-09-25 Elektrische schaltung

Country Status (4)

Country Link
US (1) US7225348B2 (de)
EP (1) EP1464000A2 (de)
DE (1) DE10148134B4 (de)
WO (1) WO2003030008A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006024507B4 (de) 2006-05-23 2017-06-01 Infineon Technologies Ag Integrierte Schaltung und Verfahren zum Erkennen von Laufzeitfehlern in integrierten Schaltungen
US20080155296A1 (en) * 2006-12-22 2008-06-26 Fujitsu Limited Apparatus for controlling clock signals to processor circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4757439A (en) * 1984-11-02 1988-07-12 Measurex Corporation Memory bus architecture
US4941157A (en) * 1989-04-14 1990-07-10 Ncr Corporation Slow peripheral handshake interface circuit
US5491814A (en) * 1991-02-01 1996-02-13 Intel Corporation Apparatus using a state machine for generating selectable clock frequencies and a fixed frequency for operating a computer bus
US5969550A (en) * 1995-03-31 1999-10-19 Telefonkatiebolaget Lm Ericsson Method and apparatus for mutual synchronization of ASIC devices
US6211715B1 (en) * 1997-03-31 2001-04-03 Nec Corporation Semiconductor integrated circuit incorporating therein clock supply circuit

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4021784A (en) * 1976-03-12 1977-05-03 Sperry Rand Corporation Clock synchronization system
GB1561961A (en) * 1977-04-20 1980-03-05 Int Computers Ltd Data processing units
US5265243A (en) * 1989-03-27 1993-11-23 Motorola, Inc. Processor interface controller for interfacing peripheral devices to a processor
DE3931382C1 (en) * 1989-09-20 1990-11-22 Siemens Ag, 1000 Berlin Und 8000 Muenchen, De Data transfer method between modules e.g. computers and peripherals - applying smallest of pulse frequencies of module to sync. bus as pulse frequency
GB2294561B (en) * 1994-10-27 1999-03-31 Advanced Risc Mach Ltd Circuit synchronization with multiple clock signals
JPH08147161A (ja) * 1994-11-21 1996-06-07 Nec Corp データ処理装置
US5498981A (en) * 1995-01-31 1996-03-12 Nec Corporation Ready signal control apparatus capable of automatically deactivating ready signal
DE19510800C1 (de) * 1995-03-24 1996-07-04 Siemens Ag Anordnung zur Umschaltung zwischen mehreren Benutzern zugeordneten Taktsignalen
US5680594A (en) * 1995-05-24 1997-10-21 Eastman Kodak Company Asic bus interface having a master state machine and a plurality of synchronizing state machines for controlling subsystems operating at different clock frequencies
US5862373A (en) * 1996-09-06 1999-01-19 Intel Corporation Pad cells for a 2/N mode clocking scheme
US5796995A (en) * 1997-02-28 1998-08-18 Texas Instruments Incorporated Circuit and method for translating signals between clock domains in a microprocessor
US5960053A (en) * 1997-05-19 1999-09-28 Lexmark International Inc Method and apparatus for generating a clock signal having a frequency equal to an oscillator frequency divided by a fraction
US5964856A (en) * 1997-09-30 1999-10-12 Intel Corporation Mechanism for data strobe pre-driving during master changeover on a parallel bus
US6047346A (en) * 1998-02-02 2000-04-04 Rambus Inc. System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers
US6247089B1 (en) * 1998-09-16 2001-06-12 Advanced Micro Devices, Inc. Efficient data loading scheme to minimize PCI bus arbitrations delays and wait states
US6266779B1 (en) * 1998-10-08 2001-07-24 Intel Corporation Clock enable generation, synchronization, and distribution
US6118314A (en) * 1998-10-14 2000-09-12 Vlsi Technology, Inc. Circuit assembly and method of synchronizing plural circuits

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4757439A (en) * 1984-11-02 1988-07-12 Measurex Corporation Memory bus architecture
US4941157A (en) * 1989-04-14 1990-07-10 Ncr Corporation Slow peripheral handshake interface circuit
US5491814A (en) * 1991-02-01 1996-02-13 Intel Corporation Apparatus using a state machine for generating selectable clock frequencies and a fixed frequency for operating a computer bus
US5969550A (en) * 1995-03-31 1999-10-19 Telefonkatiebolaget Lm Ericsson Method and apparatus for mutual synchronization of ASIC devices
US6211715B1 (en) * 1997-03-31 2001-04-03 Nec Corporation Semiconductor integrated circuit incorporating therein clock supply circuit

Also Published As

Publication number Publication date
DE10148134B4 (de) 2007-04-19
US20050110549A1 (en) 2005-05-26
WO2003030008A2 (de) 2003-04-10
DE10148134A1 (de) 2003-04-24
US7225348B2 (en) 2007-05-29
EP1464000A2 (de) 2004-10-06

Similar Documents

Publication Publication Date Title
WO2001046987A3 (en) Inkjet-fabricated integrated circuits
WO2003030611A1 (en) Optimalization apparatus, mounting apparatus, and electronic part mounting system
WO2004061635A3 (en) Adaptive power control
AU2001230975A1 (en) Redundant system for assembly of electronic components to substrates
AU2002325994A1 (en) Hydraulic circuit architecture for an aircraft braking system
WO1999015539A3 (de) Pentopyranosyl-nucleosid, seine herstellung und verwendung
SG108989A1 (en) Etchant, replenishment solution and method for producing copper wiring using the same
AU2002352284A1 (en) A method and a system for executing operating system functions, as well as an electronic device
WO2005041251A3 (en) Digitally controlled delay cells
AU2003284573A1 (en) Circuit board, multi-layer wiring board, method for making circuit board, and method for making multi-layer wiring board
WO2000041057A3 (en) Method and apparatus for reducing power consumption
WO2003069484A3 (en) Method and apparatus for supplementary command bus in a computer system
EP0940758A3 (de) Serielle Busbeschleunigungsschaltung
WO2002029545A3 (en) Asynchronously controlling data transfers within a circuit
EP1085434A3 (de) Taktschaltung und Verfahren zu deren Entwurf
AU2003274094A1 (en) Method for producing a semi-finished printed circuit board, a semi-finished printed circuit board produced by a method of this type and a multi-layer printed circuit board configured from the same
EP1333578A3 (de) Verschachtelter Taktsignalgenerator mit einer in Reihe geschaltete Verzögerungslemente und Ringzähler aufweisenden Architektur
WO2003030008A3 (de) Elektrische schaltung
WO2007005051A3 (en) System and method of managing clock speed in an electronic device
AU2002357592A1 (en) Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package
WO2004034159A3 (en) A method of controlling an electronic or computer system
WO2008113767A3 (en) Method of manufacturing a printed circuit board
WO2005055561A3 (en) System and method for managing oss component configuration
WO2002082246A3 (en) Reset circuit and method therefor
TWI256539B (en) Apparatus and method for generating a clock signal

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FR GB GR IE IT LU MC NL PT SE SK TR

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2002774422

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2002774422

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 10491070

Country of ref document: US