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WO2003005434A3 - Procede de diminution de la rugosite de surface d'une tranche semicondutrice - Google Patents

Procede de diminution de la rugosite de surface d'une tranche semicondutrice Download PDF

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Publication number
WO2003005434A3
WO2003005434A3 PCT/FR2002/002341 FR0202341W WO03005434A3 WO 2003005434 A3 WO2003005434 A3 WO 2003005434A3 FR 0202341 W FR0202341 W FR 0202341W WO 03005434 A3 WO03005434 A3 WO 03005434A3
Authority
WO
WIPO (PCT)
Prior art keywords
rugosity
reducing surface
free surface
semiconductor slice
surface rugosity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/FR2002/002341
Other languages
English (en)
Other versions
WO2003005434A2 (fr
Inventor
Eric Neyret
Ludovic Ecarnot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to JP2003511301A priority Critical patent/JP2004538627A/ja
Priority to EP20020782466 priority patent/EP1412972A2/fr
Priority to AU2002333957A priority patent/AU2002333957A1/en
Priority to KR1020047000100A priority patent/KR100784581B1/ko
Publication of WO2003005434A2 publication Critical patent/WO2003005434A2/fr
Publication of WO2003005434A3 publication Critical patent/WO2003005434A3/fr
Priority to US10/750,443 priority patent/US6962858B2/en
Anticipated expiration legal-status Critical
Priority to US11/189,899 priority patent/US7883628B2/en
Priority to US11/189,849 priority patent/US7749910B2/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Formation Of Insulating Films (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention propose un procédé de diminution de la rugosité de la surface libre d'une tranche de matériau semiconducteur (50). Un recuit thermique rapide est réalisé dans une atmosphère composée exclusivement d’argon pur. La tranchée peut être obtenue à partir d’un substrat mis en contact avec un raidisseur, par clivage du substrat au niveau d’une zone préalablement affaiblie par implantation.
PCT/FR2002/002341 2001-07-04 2002-07-04 Procede de diminution de la rugosite de surface d'une tranche semicondutrice Ceased WO2003005434A2 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2003511301A JP2004538627A (ja) 2001-07-04 2002-07-04 表面しわを減少させる方法
EP20020782466 EP1412972A2 (fr) 2001-07-04 2002-07-04 Procede de diminution de rugosite de surface
AU2002333957A AU2002333957A1 (en) 2001-07-04 2002-07-04 Method for reducing surface rugosity of a semiconductor slice
KR1020047000100A KR100784581B1 (ko) 2001-07-04 2002-07-04 표면 거칠기 감소 방법
US10/750,443 US6962858B2 (en) 2001-07-04 2003-12-30 Method for reducing free surface roughness of a semiconductor wafer
US11/189,899 US7883628B2 (en) 2001-07-04 2005-07-27 Method of reducing the surface roughness of a semiconductor wafer
US11/189,849 US7749910B2 (en) 2001-07-04 2005-07-27 Method of reducing the surface roughness of a semiconductor wafer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0108859 2001-07-04
FR0108859A FR2827078B1 (fr) 2001-07-04 2001-07-04 Procede de diminution de rugosite de surface

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/006380 Continuation-In-Part WO2005055308A1 (fr) 2001-07-04 2003-12-03 Procede permettant de reduire la rugosite de surface d'une tranche

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/750,443 Continuation US6962858B2 (en) 2001-07-04 2003-12-30 Method for reducing free surface roughness of a semiconductor wafer

Publications (2)

Publication Number Publication Date
WO2003005434A2 WO2003005434A2 (fr) 2003-01-16
WO2003005434A3 true WO2003005434A3 (fr) 2003-11-06

Family

ID=8865109

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2002/002341 Ceased WO2003005434A2 (fr) 2001-07-04 2002-07-04 Procede de diminution de la rugosite de surface d'une tranche semicondutrice

Country Status (8)

Country Link
US (1) US6962858B2 (fr)
EP (1) EP1412972A2 (fr)
JP (1) JP2004538627A (fr)
KR (1) KR100784581B1 (fr)
CN (1) CN1321443C (fr)
AU (1) AU2002333957A1 (fr)
FR (1) FR2827078B1 (fr)
WO (1) WO2003005434A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7863158B2 (en) 2006-07-13 2011-01-04 S.O.I.Tec Silicon On Insulator Technologies Treatment for bonding interface stabilization

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US7749910B2 (en) 2001-07-04 2010-07-06 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
US7883628B2 (en) 2001-07-04 2011-02-08 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
FR2852143B1 (fr) * 2003-03-04 2005-10-14 Soitec Silicon On Insulator Procede de traitement preventif de la couronne d'une tranche multicouche
JP2007500435A (ja) * 2003-07-29 2007-01-11 エス．オー．アイ．テック、シリコン、オン、インシュレター、テクノロジーズ 共注入と熱アニールによって特性の改善された薄層を得るための方法
US7563697B2 (en) 2003-09-05 2009-07-21 Sumco Corporation Method for producing SOI wafer
EP1667209B1 (fr) * 2003-09-08 2012-05-09 SUMCO Corporation Procede de production de plaquette soi
ATE498904T1 (de) * 2003-12-03 2011-03-15 Soitec Silicon On Insulator Verfahren zur verbesserung der öberflächenrauhigkeit eines halbleiterwafers
FR2863771B1 (fr) * 2003-12-10 2007-03-02 Soitec Silicon On Insulator Procede de traitement d'une tranche multicouche presentant un differentiel de caracteristiques thermiques
JP4285244B2 (ja) 2004-01-08 2009-06-24 株式会社Ｓｕｍｃｏ Ｓｏｉウェーハの作製方法
FR2867607B1 (fr) * 2004-03-10 2006-07-14 Soitec Silicon On Insulator Procede de fabrication d'un substrat pour la microelectronique, l'opto-electronique et l'optique avec limitaton des lignes de glissement et substrat correspondant
KR20070107180A (ko) 2005-02-28 2007-11-06 실리콘 제너시스 코포레이션 기판 강화 방법 및 그 결과물인 디바이스
US7642205B2 (en) * 2005-04-08 2010-01-05 Mattson Technology, Inc. Rapid thermal processing using energy transfer layers
FR2888663B1 (fr) * 2005-07-13 2008-04-18 Soitec Silicon On Insulator Procede de diminution de la rugosite d'une couche epaisse d'isolant
US7674687B2 (en) * 2005-07-27 2010-03-09 Silicon Genesis Corporation Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
US7166520B1 (en) * 2005-08-08 2007-01-23 Silicon Genesis Corporation Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process
US20070029043A1 (en) * 2005-08-08 2007-02-08 Silicon Genesis Corporation Pre-made cleavable substrate method and structure of fabricating devices using one or more films provided by a layer transfer process
US7427554B2 (en) * 2005-08-12 2008-09-23 Silicon Genesis Corporation Manufacturing strained silicon substrates using a backing material
WO2007080013A1 (fr) * 2006-01-09 2007-07-19 International Business Machines Corporation Procede et appareil de traitement de substrats semiconducteurs en tranches collees
CN100490860C (zh) * 2006-01-25 2009-05-27 余内逊 一种微米松花珍珠四女子益肝养颜口服液制备方法
US7863157B2 (en) 2006-03-17 2011-01-04 Silicon Genesis Corporation Method and structure for fabricating solar cells using a layer transfer process
US7598153B2 (en) * 2006-03-31 2009-10-06 Silicon Genesis Corporation Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species
EP2002484A4 (fr) 2006-04-05 2016-06-08 Silicon Genesis Corp Procede et structure conçus pour fabriquer des cellules photovoltaiques au moyen d'un processus de transfert de couche
US8153513B2 (en) 2006-07-25 2012-04-10 Silicon Genesis Corporation Method and system for continuous large-area scanning implantation process
WO2008082920A1 (fr) * 2006-12-28 2008-07-10 Memc Electronic Materials, Inc. Procédé de production de plaquettes lisses
JP5143477B2 (ja) * 2007-05-31 2013-02-13 信越化学工業株式会社 Ｓｏｉウエーハの製造方法
JP5466410B2 (ja) * 2008-02-14 2014-04-09 信越化学工業株式会社 Ｓｏｉ基板の表面処理方法
WO2010062852A1 (fr) * 2008-11-26 2010-06-03 Memc Electronic Materials, Inc. Procédé de traitement d’une structure silicium sur isolant
FR2943458B1 (fr) * 2009-03-18 2011-06-10 Soitec Silicon On Insulator Procede de finition d'un substrat de type "silicium sur isolant" soi
US9560953B2 (en) 2010-09-20 2017-02-07 Endochoice, Inc. Operational interface in a multi-viewing element endoscope
CN103835000A (zh) * 2012-11-20 2014-06-04 上海华虹宏力半导体制造有限公司 一种高温改善多晶硅表面粗糙度的方法
CN103065956B (zh) * 2012-12-27 2015-02-25 南京大学 一种实现硅表面结构平滑的方法与设备
FR3046877B1 (fr) * 2016-01-14 2018-01-19 Soitec Procede de lissage de la surface d'une structure
CN109346562A (zh) * 2018-08-30 2019-02-15 华灿光电（浙江）有限公司 一种发光二极管外延片的制备方法及发光二极管外延片
CN111270196B (zh) * 2019-03-07 2022-03-04 苏州微创关节医疗科技有限公司 制备锆铌合金表面氧化陶瓷层的方法及应用
CN114664657A (zh) * 2021-10-29 2022-06-24 中国科学院上海微系统与信息技术研究所 一种晶圆表面处理方法

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FR2777115A1 (fr) * 1998-04-07 1999-10-08 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
EP1045448A1 (fr) * 1998-10-16 2000-10-18 Shin-Etsu Handotai Co., Ltd Procede de production de tranche soi utilisant un procede de separation d'implantation d'ions hydrogene et tranche soi produite a l'aide du procede
EP1061565A1 (fr) * 1998-12-28 2000-12-20 Shin-Etsu Handotai Co., Ltd Procede de recuit thermique d'une plaquette de silicium, et plaquette de silicium
FR2797713A1 (fr) * 1999-08-20 2001-02-23 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
WO2001028000A1 (fr) * 1999-10-14 2001-04-19 Shin-Etsu Handotai Co., Ltd. Procede de fabrication d'une tranche de soi, et tranche de soi

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FR2777115A1 (fr) * 1998-04-07 1999-10-08 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
EP1045448A1 (fr) * 1998-10-16 2000-10-18 Shin-Etsu Handotai Co., Ltd Procede de production de tranche soi utilisant un procede de separation d'implantation d'ions hydrogene et tranche soi produite a l'aide du procede
EP1061565A1 (fr) * 1998-12-28 2000-12-20 Shin-Etsu Handotai Co., Ltd Procede de recuit thermique d'une plaquette de silicium, et plaquette de silicium
FR2797713A1 (fr) * 1999-08-20 2001-02-23 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
WO2001028000A1 (fr) * 1999-10-14 2001-04-19 Shin-Etsu Handotai Co., Ltd. Procede de fabrication d'une tranche de soi, et tranche de soi
EP1158581A1 (fr) * 1999-10-14 2001-11-28 Shin-Etsu Handotai Co., Ltd Procede de fabrication d'une tranche de soi, et tranche de soi

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7863158B2 (en) 2006-07-13 2011-01-04 S.O.I.Tec Silicon On Insulator Technologies Treatment for bonding interface stabilization
US8216916B2 (en) 2006-07-13 2012-07-10 S.O.I. Tec Silicon On Insulator Technologies Treatment for bonding interface stabilization

Also Published As

Publication number Publication date
WO2003005434A2 (fr) 2003-01-16
FR2827078B1 (fr) 2005-02-04
US6962858B2 (en) 2005-11-08
JP2004538627A (ja) 2004-12-24
KR100784581B1 (ko) 2007-12-10
CN1524289A (zh) 2004-08-25
FR2827078A1 (fr) 2003-01-10
US20040171257A1 (en) 2004-09-02
KR20040013106A (ko) 2004-02-11
AU2002333957A1 (en) 2003-01-21
EP1412972A2 (fr) 2004-04-28
CN1321443C (zh) 2007-06-13

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