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AU2003299368A1 - Method of the production of cavities in a silicon sheet - Google Patents

Method of the production of cavities in a silicon sheet

Info

Publication number
AU2003299368A1
AU2003299368A1 AU2003299368A AU2003299368A AU2003299368A1 AU 2003299368 A1 AU2003299368 A1 AU 2003299368A1 AU 2003299368 A AU2003299368 A AU 2003299368A AU 2003299368 A AU2003299368 A AU 2003299368A AU 2003299368 A1 AU2003299368 A1 AU 2003299368A1
Authority
AU
Australia
Prior art keywords
production
cavities
silicon sheet
insulation layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003299368A
Inventor
Christophe Maleville
Walter Schwarzenbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0216409A external-priority patent/FR2849269B1/en
Application filed by Soitec SA filed Critical Soitec SA
Publication of AU2003299368A1 publication Critical patent/AU2003299368A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/005—Bulk micromachining
    • B81C1/00507—Formation of buried layers by techniques other than deposition, e.g. by deep implantation of elements
    • H10P30/204—
    • H10P30/208—
    • H10P90/1906—
    • H10W10/021—
    • H10W10/181—
    • H10W10/20—
    • H10P30/22—

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Silicon Compounds (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

The invention relates to a method for production of a semiconductor structure of the SOI type, comprising a surface layer of silicon, a covered insulation layer and a substrate, comprising the following method steps: an atomic implantation step through at least a part of the insulation layer and an engraving step for the insulation layer in at least a part of said layer affected by the atomic implantation.
AU2003299368A 2002-12-20 2003-12-19 Method of the production of cavities in a silicon sheet Abandoned AU2003299368A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
FR02/16409 2002-12-20
FR0216409A FR2849269B1 (en) 2002-12-20 2002-12-20 METHOD FOR PRODUCING CAVITIES IN A SILICON PLATE
US44812403P 2003-02-20 2003-02-20
US60/448,124 2003-02-20
PCT/FR2003/003820 WO2004059725A1 (en) 2002-12-20 2003-12-19 Method of the production of cavities in a silicon sheet

Publications (1)

Publication Number Publication Date
AU2003299368A1 true AU2003299368A1 (en) 2004-07-22

Family

ID=32683899

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003299368A Abandoned AU2003299368A1 (en) 2002-12-20 2003-12-19 Method of the production of cavities in a silicon sheet

Country Status (5)

Country Link
EP (1) EP1573802B1 (en)
AT (1) ATE415703T1 (en)
AU (1) AU2003299368A1 (en)
DE (1) DE60324960D1 (en)
WO (1) WO2004059725A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005083775A1 (en) * 2004-02-19 2005-09-09 International Business Machines Corporation FORMATION OF PATTERNED SILICON-ON-INSULATOR (SOI)/SILICON-ON-NOTHING (SON) COMPOSITE STRUCTURE BY POROUS Si ENGINEERING
FR2875947B1 (en) 2004-09-30 2007-09-07 Tracit Technologies NOVEL STRUCTURE FOR MICROELECTRONICS AND MICROSYSTEMS AND METHOD OF MAKING SAME
FR2876220B1 (en) 2004-10-06 2007-09-28 Commissariat Energie Atomique METHOD FOR PRODUCING MIXED STACKED STRUCTURES, VARIOUS INSULATING AREAS AND / OR LOCALIZED VERTICAL ELECTRICAL CONDUCTION ZONES.
FR2897982B1 (en) 2006-02-27 2008-07-11 Tracit Technologies Sa METHOD FOR MANUFACTURING PARTIALLY-LIKE STRUCTURES, COMPRISING AREAS CONNECTING A SURFACE LAYER AND A SUBSTRATE
FR3000601B1 (en) * 2012-12-28 2016-12-09 Commissariat Energie Atomique METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4956314A (en) * 1989-05-30 1990-09-11 Motorola, Inc. Differential etching of silicon nitride
JPH06132262A (en) * 1992-10-22 1994-05-13 Hitachi Ltd Thin film etching method
FR2700065B1 (en) * 1992-12-28 1995-02-10 Commissariat Energie Atomique Method of manufacturing accelerometers using silicon on insulator technology.
US5976945A (en) * 1997-11-20 1999-11-02 Vanguard International Semiconductor Corporation Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor
US6335292B1 (en) * 1999-04-15 2002-01-01 Micron Technology, Inc. Method of controlling striations and CD loss in contact oxide etch
FR2795554B1 (en) * 1999-06-28 2003-08-22 France Telecom HOLES LATERAL ENGRAVING METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

Also Published As

Publication number Publication date
EP1573802A1 (en) 2005-09-14
WO2004059725A1 (en) 2004-07-15
DE60324960D1 (en) 2009-01-08
ATE415703T1 (en) 2008-12-15
EP1573802B1 (en) 2008-11-26

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase