WO2003094242A1

WO2003094242A1 - Esd-robust power switch and method of using same

Info

Publication number: WO2003094242A1
Application number: PCT/IB2003/001091
Authority: WO
Inventors: Jan Dikken
Original assignee: Koninklijke Philips Electronics NV
Current assignee: Koninklijke Philips NV
Priority date: 2002-04-29
Filing date: 2003-03-20
Publication date: 2003-11-13
Anticipated expiration: 2004-10-29
Also published as: AU2003208560A1

Abstract

The power switch has a field effect transistor (FET) with: - an active area in a semiconductor body, - a channel formed in the active area, - a source diffusion zone and a drain diffusion zone alternating with each other in the active area, a source diffusion zone being separated from a drain diffusion zone by the channel. Each source diffusion zone has a sourcecontact and each drain diffusion zone has a drain contact. A gate is electrically insulated from the channel, said gate having a length and a width. The distance between a source contact and the gate is substantially the same as the distance between the draincontact and the gate, the drain contact being translated relative to the source contact over a distance in the direction of the width of the gate, current paths between the source contact and the drain contact having substantially the same series resistance. Due to the series resistance, the power switch is robust to high ESD voltages. The ESD-robust power switch has the advantage of being very compact.

Description

ESD-robust power switch and method of using same

The invention relates to a power switch comprising a field effect transistor (FET) including:

- an active area in a semiconductor body,

- a channel which is formed in said active area, - a source diffusion zone and a drain diffusion zone which alternate with each other in the active area, a source diffusion zone being separated from a drain diffusion zone by the channel, and each source diffusion zone having a source contact, and each drain diffusion zone having a drain contact,

- a gate having a longitudinal direction and a width direction, which gate is electrically insulated from the channel.

The invention also relates to a method of using the power switch in accordance with the invention.

US 5,955,763 discloses such a MOSFET which protects an integrated circuit

(IC) against electrostatic discharge (ESD)/electrostatic overstress (EOS). The integrated circuit comprises MOS transistors. To make sure that the voltage across the gate oxide of the MOS transistors does not exceed a specific value during an ESD pulse, the voltage is clamped. For this purpose use is made of an ESD protection which is based on a grounded gate NMOS. The drain of the NMOS is connected to the pin to be protected of the IC. A positive ESD pulse on its drain will cause the NMOS to go first into avalanche breakdown and subsequently into snap-back. "To go into snap-back" means that the parasitic NPN transistor, which is present in each NMOS, opens and thereby causes the drain voltage to be reduced. Very large NMOS switches that are connected to the pin of the IC, however, cannot be protected by ESD protections based on a grounded gate NMOS. The switches themselves must be rendered ESD-robust. In the case of the known MOSFET special layout measures have been taken to spread the current resulting from an ESD event throughout the transistor. To preclude that the current of several amperes passes through a very limited part of the transistor and causes the silicon to melt there, additional series resistance in the drain has been realized by enlarging the distance between the drain contacts and the gate.

A drawback of the known MOSFET is that due to the comparatively large distance from the drain contacts to the gate the MOSFET occupies much space. In addition the MOSFET has a high gate resistance as a result of which the device cannot switch rapidly and the gate voltage cannot be controlled.

To test the ESD robustness of a device, use is generally made of the Human Body Model (HBM) and the Charged Device Model (CDM). In the HBM, simulation takes place of the discharge that may occur when a person touches a device. The human body can be represented by a capacitor of 100 pF which is charged to a specified voltage. The capacitor is subsequently discharged over the device and over a resistor of 1500 Ohm.

CDM simulates a charged device that makes contact with a metal base area, which occurs typically in the case of automated handling equipment.

In general, the dominant failure mechanism of an NMOS protection device operating in snap-back is second breakdown. Second breakdown is a phenomenon that induces thermal runaway into the device when the decrease of the impact ionization current is negligible with respect to thermal generation of charge carriers. Second breakdown occurs in the case of a high current through the device as a result of self-heating. The time that is necessary to heat up the structure to the critical temperature at which second breakdown occurs depends on the device layout and on the stress power distribution over the device.

It is an object of the invention to provide a power switch of the type described in the opening paragraph, which is more compact and more robust to voltage peaks. In the case of the power switch in accordance with the invention, this object is achieved in that the drain contact is situated at a distance from the gate that is at least substantially equal to the distance from the source contact to the gate, and the drain contact is shifted with respect to the source contact over a distance in the width direction of the gate, current paths between the source contact and the drain contact being subject to an at least substantially equal series resistance.

To make sure that the current is distributed throughout the transistor, each part of the transistor must have its own series resistance. This series resistance makes sure that if a part of the transistor goes into snap-back and causes the drain voltage to be reduced, the voltage that can be built up in the case of an increasing current across the series resistance is sufficient so that the trigger voltage for the snap-back of another part of the transistor can be achieved again without the current density locally increasing to destructive values. The series resistance between the source and drain contacts can be accurately adjusted through the distance between the source contact and the drain contact. The series resistance between the source contact and the drain contact is built up of a component in the longitudinal direction of the gate and a component in the width direction of the gate. The longitudinal direction of the gate is defined as the direction from source to drain. The width direction is the direction transverse to the longitudinal direction. The distance from the drain contact to the gate may be the minimum permissible distance allowed by the design rules of a certain process. The small distance from the drain contact to the gate res.ults in much space being saved and in a very compact transistor.

In order not to adversely influence the switching behavior of the FET, the series resistance is only a small percentage of the on-resistance of the transistor. However, in order to withstand high voltage peaks and to be able to safely drain the associated ESD current to ground, the series resistance must be sufficiently high. In practice, the series resistance typically is of the order of 10% of the on-resistance of the transistor. As a result of the equal series resistances in the current paths between a source contact and a drain contact of each diffusion zone, the current is distributed more uniformly over the entire active area. The improved distribution of the ESD current leads to a more uniform distribution of the heat, as a result of which local heating is reduced. The series resistance precludes instability and destruction of the device by second breakdown. In comparison with the prior art, the FET is more suitable to deal with higher voltage peaks of typically 2000 - 8000 V (HBM) and is more suitable to drain a higher ESD current to ground.

In order to enable rapid switching of the transistor, the total gate structure is formed by a parallel connection of gates, the ends of the gates being electrically interconnected. A small gate resistance has the advantage of a short RC delay, enabling the FET to switch rapidly. In the case of a low gate resistance the charge is directly drained to ground and the gate voltage remains substantially 0 V. A low gate resistance additionally precludes the so-termed gate lifting. Due to the overlap capacitance between the drain and the gate there is a risk that the gate potential is lifted at large drain voltage changes. The potential of the gate can be lifted, for example, upon switching of another switching transistor (such as a PMOS transistor) in an output buffer. As a result of switching off a dN/dt develops on the FET which lifts the gate voltage. Ln general the gate is formed from a layer of highly doped polysilicon. The sheet resistance of the gate can be reduced typically by a factor of 50 by applying silicidized polysilicon instead of non-silicidized polysilicon.

Generally the ESD device is manufactured concurrently with the MOS or BiCMOS transistors of the IC. A substantial advantage of a silicidized gate is that during the silicidation of the ESD protection a special protection mask can be dispensed with. As a result a masking step can be saved. In addition the additional tolerances built in for the alignment of the mask over the gate and the drain are no longer necessary. Without this protection mask space and costs can be saved. As the voltage peaks to be dealt with by the FET are higher, more electrically parallel-connected channels are necessary, i order to substantially preserve the symmetry of the layout, enabling good scaling of the voltage, the surface of the source diffusion zone is equal to the surface of the drain diffusion zone. The mutual distance between the gates is constant. The source contact and the drain contact are shifted relative to each other in the longitudinal direction of the gate over a distance equal to the mutual distance between the gates. The symmetric layout enables proper scaling in combination with a comparatively small active surface of the FET. The symmetric layout enables proper scaling in combination with a comparatively small active surface of the FET. Particularly for small ICs having a surface of several millimeters, a reduction of the active surface of the FET yields a substantial reduction of the chip surface, resulting in lower costs per chip.

The source diffusion zones are electrically interconnected, for example by means of a metallization pattern. The metallization pattern is provided over the source contacts that form a row in the longitudinal direction or the width direction of the gate. As the source diffusion zones are electrically interconnected, an ESD event triggers a source-zone cascade. As a result snap-back does not occur locally but over a large surface. The current is distributed more uniformly over the surface of the FET.

To obtain an even more compact transistor, the gate is bent, at the location of a source or drain contact, around said contact. At the location of the contact the distance to the gate is preferably the shortest possible distance permitted by the design rules of the process. Typically, the minimum distance is the width of the spacer next to the gate.

In accordance with an advantageous method, the power switch in accordance with the invention can be electrically connected by means of an NMOS transistor in a grounded gate configuration, wherein the semiconductor body comprises a low-impedance substrate which is electrically connected to ground. In the case of an ESD voltage pulse, the potential of the drain can freely fluctuate relative to the substrate, as a result of which a substantial reduction of the parasitic drain-substrate capacitance is achieved.

These and other aspects of the power switch in accordance with the invention will be elucidated with reference to the embodiment(s) described hereinafter.

In the drawings:

Fig. 1 diagrammatically shows the position of the power switch in accordance with the invention on a chip; Fig. 2 is a plan view of a first embodiment of the power switch in accordance with the invention;

Fig. 3 shows zone A in Fig. 2 on an enlarged scale; Fig. 4 diagrammatically shows the power switch in accordance with the invention in a test setup according to the Human Body Model; Fig. 5 shows an embodiment of a conventional power switch with a finger structure;

Fig. 6 shows a second embodiment of the compact power switch in accordance with the invention;

Fig. 7 shows a third embodiment of the compact power switch in accordance with the invention;

Fig. 8 is a cross-sectional view through B-B in Fig. 2 and Fig. 6; Fig. 9 shows a method of connecting the NMOS in accordance with the invention;

Fig. 10 shows an avalanche breakdown characteristic; Fig. 11 graphically shows the influence of the width of the gate on the ESD current;

Fig. 12a shows a typical characteristic of the power switch in accordance with the first embodiment in the case of an ESD event;

Fig. 12b shows the characteristic of the corresponding leakage current of the power switch in accordance with the first embodiment.

The NMOS transistor shown in Fig. 1 is a power switch in an output buffer. The NMOS also serves to limit the voltage that may develop at the output of the integrated circuit as a result of an undesirable, high voltage peak. The NMOS transistor is ESD-robust. In the case of an ESD discharge the NMOS transistor can suitably be used to remove the ESD current via a known path. In the case of comparatively small ICs, such as DC-DC converters having a surface area of only a few mm, a considerable percentage of the surface (as high as 50%) is occupied by the ESD protection.

The power switch in accordance with the invention, as shown in Fig. 2, is a MOSFET 1. The FET 1 comprises an active area 2 in a semiconductor body 3, a channel 4 formed in the active area 2 and alternately a source 5 diffusion zone and a drain 6 diffusion zone in the active area 2. A source diffusion zone 5 is separated from a drain diffusion zone 6 by the channel 4. Each source diffusion zone 5 has a source contact 8 and each drain diffusion zone has a drain contact 9.

The gate 7 is electrically insulated from the channel 4 and has a length 12 and a width 13. The source contact 8 is at a distance 14 from the gate which is at least substantially equal to the distance from the drain contact 9 to the gate 7. The drain contact is translated over a distance 15 in the width direction of the gate with respect to the source contact 8. Current paths between the source contact 8 and the drain contact 9 are subject to an at least substantially equal series resistance.

In the embodiment shown in Fig. 2 the channel of the MOSFET has a length of 0.5 μm. The total gate structure 17 is formed by a parallel connection of gates 7, the ends 16 of the gates being electrically interconnected.

The overall width of the parallel-connected gates is 600 μm. The mutual distance 18 between the gates is constant with a period of 1.8 μm. The overall surface of the active area is 2043 squares. This corresponds to a surface of the MOSFET of 510 μm . Fig. 3 shows, on an enlarged scale, that a source 8 and drain contact 9 are shifted with respect to each other in the longitudinal direction of the gate over a period of the gate, i.e. 1.8 μm. In the embodiment shown, the distance 14 from a source or drain contact to the gate is 0.6 μm. The distance 15 between a source contact and a drain contact in the width direction is 4 μm in the embodiment shown. The source 8 contacts and drain 9 contacts each form a row 10, 11 in the longitudinal direction of the gate. The source contacts are interconnected with a metallization pattern. The drain contacts are also interconnected with a metallization pattern. The metallization patterns of the source and the drain form an interdigitated structure (not shown).

In a Human Body Model test setup shown in Fig. 4a, the NMOS transistor is tested for ESD robustness. A voltage of 2000-8000 V is applied across the 100 pF capacitance. The voltage is discharged across the 1.5 kOhm resistor and the NMOS transistor. At a certain voltage, i.e. the trigger voltage Ntr, the avalanche current is large enough, as a result of breakdown of the drain-substrate junction, to switch on the bipolar transistor. As soon as the parasitic bipolar transistor goes into conduction, snap-back occurs causing the voltage to decrease to the so-termed hold voltage Nπ- Fig. 6b diagrammatically shows the series resistances in the source and drain diffusion zones of different current paths. The sum of the series resistances between a source and a drain contact is, in the embodiment shown in Fig. 2, approximately 8 times the sheet resistance of the silicidized source and drain diffusion zones. It is schematically shown that, dependent upon the current path, the source diffusion resistance 27 may exceed the drain diffusion resistance 28. The essence of the invention is that the sum of the source diffusion resistance 27 and the drain diffusion resistance 28 is at least substantially equal for all current paths. As soon as the hold voltage V_H is reached, it does not matter, from an electrical point of view, whether the diffusion resistance is in the source diffusion zone or in the drain diffusion zone. The sum of the resistances in the silicidized diffusion zones corresponds to a series resistance of 8*2.3 Ohm = 18.4 Ohm. In the embodiment shown, there are 8*4 = 32 sections, so that the series resistance of the transistor is approximately 600 mOhm.

In the Human Body Model test, the ΝMOS transistor is robust to voltages > 2000 N. As regards ESD sensitivity, the transistor belongs to class 2 of the Human Body Model. The resistance of the transistor is 5 Ohm in the on-state and the series resistance is 600 mOhm. The total surface of the active area is 2043 squares.

The layout of the FET shown in Fig. 2 is much more compact than the conventional finger structure. Fig. 5 shows a conventional finger structure which is ESD- robust to voltage peaks between 2000 - 5000 V. The width of the channel of the transistor is 500 μm. The resistance of the transistor in the on-state is 6 Ohm and the series resistance is 600 mOhm.

In the conventional finger structure additional series resistance is created by means of an additional mask 30 to block the silicidation of the source, the gate and the drain. The protection mask overlaps the polysilicon gate by 4 μm on the drain side and by 1.7 μm on the source side. This not only takes up much space but also causes the resistance of the gate to be increased by a factor of 50. As a result, the gate of a large transistor may be locally lifted if the voltage on the drain exhibits a steeply increasing slope. This may lead to a large, undesirable current peak that may seriously interfere with the operation of the chip. This in turn requires additional layout measures leading to a further increase of the surface. To deal with voltage peaks in the range between 2000 - 5000 N, the surface of the conventional finger structure is 4145 squares.

The power switch in accordance with the invention, which has 2043 squares of active surface, is much more compact. Relative to the conventional structure, a 50% saving of surface is obtained.

The second embodiment of the power switch in Fig. 6 is even more compact than the first embodiment. At the location of a source or drain contact, the gate is bent around the contact. The minimum distance from the source contact and the drain contact to the gate is 0.6 μm. In advanced processes the distance from the source or drain contact may be smaller, for example 0.2 μm. The distance depends on the design rules of a specific CMOS process. By bending 19 the gate around the contacts the period between the gates can be further reduced to 1.2 μm. The gain in surface area of the FET in the second embodiment shown is a factor of 1.35 with respect to the first embodiment.

In the third embodiment shown in Fig. 7, around a contact 8, 9 the gates are bent 19 around said contact. The distance from the gates to the contact is equal to that in the second embodiment, i.e. 0.6 μm. The period of the gates is further reduced to 1.0 μm. The gain in surface area of the FET in the third embodiment shown is a factor of 1.62 with respect to the first embodiment.

Fig. 8 is a cross-sectional view of the ΝMOSFET. On a highly doped p-type substrate, an active area 2 is formed in the semiconductor body 3 which is surrounded by insulating material, such as SiO₂. The active area 2 is doped with boron. On the surface of the semiconductor body there is provided a gate dielectric of 10 nm SiO₂. Subsequently, a layer of polysilicon is deposited in a thickness of 250 nm. Said layer of polysilicon is patterned and forms the gate 7. The shallow source 23 and drain 24 diffusion zones forming an extension of the source 5 and the drain 6 are implanted with P ions in a dose of 4el3 at/cm² having an energy of 25 keN. The source 5 and drain 6 diffusion zones are implanted with As ions in a dose of 4el5 at/cm² at an energy of 100 keN. The sheet resistance of the non-silicidized n- type As area is 55 Ohm/square after outdiffusion.

The polysilicon gate 7 is doped concurrently with the source and drain diffusion zones. The sheet resistance of the As-doped polysilicon is 135 Ohm/square. After spacer formation next to the polysilicon gate 20, a Ti/TiΝ multilayer is provided in a thickness of 30 nm/25 nm. During a rapid thermal process (RTP) approximately 70 nm TiSi₂ is formed on the gate and the source and drain diffusion zones in 20 seconds at 730 °C in Ν₂. The sheet resistance of the silicidized polysilicon is 2.3 Ohm/square. The sheet resistance of the silicidized source and drain diffusion zones is 2.3 Ohm/square.

The contacts to the active area are made by means of W plugs in a manner known to those skilled in the art. The source contacts are interconnected by means of an Al metallization pattern. The drain contacts are also interconnected by means of an Al metallization pattern, the two metallization patterns forming a finger structure.

In operation, the NMOSFET is connected in a grounded NMOS configuration as shown in Fig. 9. It is remarkable that instead of a p-well contact as used in conventional structures, a highly doped p-type substrate of 0.01 Ohm/cm is connected to ground as the rear side contact. The contacting of the p-type substrate has substantial advantages in comparison with the p-well. In the first place, the space occupied by the p-well contacts is saved. What is more important is that also the parasitic capacitance of the drain to the substrate is absent. The potential of the drain zones can freely fluctuate with respect to the substrate. As a result of the comparatively large surface of the drain diffusion zones, this means that a substantial reduction of the parasitic drain-substrate capacitance is achieved.

The avalanche breakdown characteristic for the NMOSFET in accordance with the first embodiment is shown in Fig. 10. As a result of the high positive drain voltage, avalanche multiplication occurs in the depletion zone of the drain junction. As the surface concentration of the drain exceeds that in the bulk, typically le20 at/cm², breakdown occurs at the edge of the drain junction. The threshold voltage Ntr for breakdown as a result of avalanche multiplication is approximately 12 N. As a result of the substrate current the source-substrate diode becomes conducting. The parasitic bipolar transistor is turned on. As a result of the conduction by the bipolar transistor the electrons are led to the drain. The hold voltage N_H is approximately 6 N. After the npn is turned on and keeps the voltage at approximately 6 N, the voltage of the pad can increase to the 12 N trigger voltage as a result of the series resistance.

Fig. 11 shows that the ESD current depends substantially linearly on the width 13 of the channel. Breakdown at the surface of the inhibited drain-substrate junction (curve a) occurs sooner than breakdown caused by self-heating (curve b). Fig. 12a shows a typical characteristic of the ESD-robust power switch in accordance with the first embodiment. At a voltage pulse of 2500 V during several ns, it is clearly visible that the parasitic transistor goes into snap-back in all source and drain diffusion zones in the active area. Fig. 12b shows the corresponding leakage current of the ggΝMOS. If during the ESD event the current through the device under test (Idut) remains comparatively low, then the measured leakage current is low, typically several nano-amperes. Only at a current of approximately 1 A through the ggNMOS during the ESD event, permanent damage occurs in the transistor.

Claims

CLAIMS:

1. A power switch comprising a field effect transistor (FET) including:

- an active area in a semiconductor body,

- a channel which is formed in said active area,

- a source diffusion zone and a drain diffusion zone which alternate with each other in the active area, a source diffusion zone always being separated from a drain diffusion zone by the channel, and each source diffusion zone having a source contact, and each drain diffusion zone having a drain contact,

- a gate having a longitudinal direction and a width direction, which gate is electrically insulated from the channel, characterized in that the drain contact is situated at a distance from the gate that is at least substantially equal to the distance from the source contact to the gate, and the drain contact is shifted with respect to the source contact over a distance in the width direction of the gate, current paths between the source contact and the drain contact being subject to an at least substantially equal series resistance.

2. A power switch as claimed in claim 1, characterized in that a total gate structure is formed by a parallel connection of gates, the ends of the gates being electrically interconnected.

3. A power switch as claimed in claim 1, characterized in that the gate comprises a metal suicide.

4. A power switch as claimed in claim 2, characterized in that the gates are arranged equidistantly.

5. A power switch as claimed in claim 4, characterized in that the source contact and the drain contact are shifted relative to each other in the longitudinal direction of the gate over a distance equal to the mutual distance between the gates.

6. A power switch as claimed in claim 1, characterized in that the source contacts and the drain contacts each form a row in the longitudinal direction of the gate.

7. A power switch as claimed in claim 1, characterized in that at the location of a source or drain contact, the gate is bent around the contact.

8. A method of using the power switch as claimed in claims 1-7, wherein the FET is an NMOS which is electrically connected in a grounded gate configuration, and wherein the semiconductor body comprises a low-impedance substrate which is electrically connected to ground.