WO2002100142A1 - Wiring board and its production method - Google Patents
Wiring board and its production method Download PDFInfo
- Publication number
- WO2002100142A1 WO2002100142A1 PCT/JP2002/005162 JP0205162W WO02100142A1 WO 2002100142 A1 WO2002100142 A1 WO 2002100142A1 JP 0205162 W JP0205162 W JP 0205162W WO 02100142 A1 WO02100142 A1 WO 02100142A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wiring
- substrate
- wiring board
- hole
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
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Classifications
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- H10W70/635—
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
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- H10W70/095—
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- H10W90/701—
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/0949—Pad close to a hole, not surrounding the hole
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
- H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1581—Treating the backside of the PCB, e.g. for heating during soldering or providing a liquid coating on the backside
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
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- H10W72/07251—
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- H10W72/20—
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- H10W72/90—
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- H10W72/9415—
Definitions
- the present invention relates to a wiring board and a method for manufacturing the same.
- ceramic wiring boards have been widely used as multilayer wiring boards having through holes. That is, after forming through holes in a ceramic green sheet (hereinafter sometimes referred to as a green sheet) in which ceramic raw material powders are bound with an organic resin as a binder, a wiring pattern is formed by screen printing using a conductive paste. At the same time, the conductive paste is filled into the through holes connecting the wiring patterns on each sheet. Then, a predetermined number of green sheets on which a wiring pattern is formed are stacked, pressure-bonded, and fired to produce a ceramic wiring board.
- a ceramic green sheet hereinafter sometimes referred to as a green sheet
- a wiring pattern is formed by screen printing using a conductive paste.
- the conductive paste is filled into the through holes connecting the wiring patterns on each sheet.
- a predetermined number of green sheets on which a wiring pattern is formed are stacked, pressure-bonded, and fired to produce a ceramic wiring board.
- the ceramic wiring board undergoes firing and cooling steps during its manufacture. At this time, the binder is delaminated and pressed while removing the binder from the green sheet and the conductive paste. However, since their deformation rates are different, there is a problem that the wiring is likely to be deformed in a fine wiring pattern. In addition, the ceramic substrate and the wiring material also undergo thermal deformation in the process of cooling from the sintering temperature after the completion of the compression bonding, so that it was difficult to calculate the thermal deformation of the entire substrate.
- the binder volatilizes during firing of the ceramic substrate, the surface of the ceramic substrate becomes uneven, and it is difficult to form a fine wiring pattern as it is.
- a multilayer wiring substrate having a core substrate a glass substrate or a silicon substrate
- glass substrates or silicon substrates are not widely used as multilayer wiring substrates with through holes because the substrates are fragile.
- Japanese Patent Application No. Hei 8-5-274989 discloses a glass substrate on which a semiconductor chip is mounted.
- the glass substrate has a semiconductor chip mounted on one surface, and does not have a wiring layer composed of an insulating layer and a conductor layer formed on both surfaces of the glass substrate.
- Japanese Patent Application Laid-Open No. H10-224206 discloses a substrate in which a through hole is formed in a photosensitive glass using an exposure and development process.
- This board when a bare chip is mounted, has both a function as an inspection board at the time of panning and a function as an interposer (material connecting the bare chip and external terminals) for connection to a board such as a printed circuit board.
- this does not mean that a wiring layer composed of an insulating layer and a conductor layer is formed in multiple layers on a core substrate.
- the through holes are formed by sandblasting.
- Japanese Patent Application Laid-Open No. H11-2443267 discloses a wiring board in which wiring is formed on an insulating substrate having a through hole.
- the insulating substrate is formed by a ceramic sintered body such as a glass ceramic sintered body.
- the ceramic green sheet is subjected to an appropriate punching process. It is disclosed that it is manufactured by forming a predetermined shape and firing at a high temperature.
- the diameter of the through hole is gradually increased from the center of the substrate toward both ends of the opening.
- the insulating substrate is a glass ceramic, is not a glass substrate, and does not have a multilayer wiring layer composed of an insulating layer and a conductor layer formed on the insulating substrate.
- An object of the present invention is to provide a low-cost wiring board capable of high-density wiring.
- Another object of the present invention is to provide a multi-layer wiring board having a substrate having a through hole and a thin film wiring layer formed on the surface of the substrate, the wiring board having high reliability and capable of high-density wiring. At low cost.
- a method for manufacturing a wiring board comprising: a step of forming a wiring layer having a conductor layer and an insulating layer on a glass substrate in multiple layers; and a first step of forming a wiring layer formed on one surface of the glass substrate. Forming a hole, performing a sand blast on the glass substrate from a position where the first hole is formed, forming a second hole in the glass substrate, and an inner wall surface of the second hole. And forming a wiring on the outermost surface of the wiring layer.
- a method for manufacturing a wiring board comprising: forming a hole in a glass substrate by sand plast; forming a wiring on at least one surface of the glass substrate and an inner wall surface of the hole.
- FIG. 1 is a cross-sectional view of a wiring board in which wiring is formed on an insulating substrate having a through hole.
- FIG. 2 is a diagram showing one embodiment of the wiring board according to the present invention.
- FIG. 3 is a view showing one embodiment of a multi-chip module having a wiring board according to the present invention.
- FIG. 4 is a view showing a state where a semiconductor module is mounted on a mounting board.
- FIG. 5 is a perspective view showing one embodiment of the semiconductor module according to the present invention.
- Figure 6 is a photograph showing through holes formed in a glass substrate by sand plasting and photoetching.
- FIG. 7 is a diagram showing one embodiment of the wiring board according to the present invention.
- FIG. 8 is a diagram showing a state in which a multichip module having a wiring board according to the present invention is mounted on a mounting board.
- FIG. 9 is a diagram showing one embodiment of a wiring board according to the present invention.
- FIG. 10 is a diagram showing a state in which a multichip module having a wiring board according to the present invention is mounted on a mounting board.
- FIG. 11 is a view showing an embodiment of a manoret chip module having a wiring board according to the present invention.
- FIG. 12 is a diagram showing an example of a combination of semiconductor chips mounted on a multilayer wiring board.
- FIG. 13 is a flowchart of the manufacturing process of the wiring board according to the present invention.
- FIGS. 14a, 14b and 14c are views showing an example of the manufacturing process of the wiring board according to the present invention.
- FIGS. 15a and 15b are views showing an example of the manufacturing process of the wiring board according to the present invention.
- FIG. 16 is a diagram illustrating an example of a manufacturing process of the wiring board according to the present invention.
- FIG. 17 is a diagram showing the relationship between the wiring and the position at which particles by sandblasting strike.
- FIG. 18 is a flowchart of the manufacturing process of the wiring board according to the present invention.
- FIGS. 19, 19b, and 19c are views showing an example of the manufacturing process of the wiring board according to the present invention.
- 20a, 20b and 20c are views showing an example of the manufacturing process of the wiring board according to the present invention.
- FIG. 21 is a photograph showing a state where an unfilled portion is formed when the through hole is filled.
- 22a, 22b and 22c are views showing an example of the manufacturing process of the wiring board according to the present invention.
- FIGS. 23a and 23b are views showing an example of the manufacturing process of the wiring board according to the present invention.
- FIG. 24 is a schematic view of a through hole formed in a substrate by sand plast.
- FIG. 25 is a diagram showing through-holes formed in an insulating substrate to which members are applied by sandplast.
- FIGS. 26a, 26b, 26c and 26d are diagrams showing a method of forming a wiring in a through hole of a substrate.
- FIG. 27 is a diagram of an experimental result showing the relationship between the glass transition temperature (Tg) and the coefficient of linear expansion.
- FIG. 28 is a diagram illustrating a state in which a large number of wiring substrates are formed using a glass substrate or a ceramic substrate. ⁇
- FIG. 29 is a diagram showing one embodiment of the wiring board according to the present invention.
- FIGS. 30a, 30b, 30c, 30d, 30e, 30f, 308 and 311 are diagrams showing a method for manufacturing a gyroscope.
- Figures 31a, 31b, 31c, 31d, and 31e are views showing the formation of through holes in the substrate by the sand-plast method.
- FIG. 32 is a diagram showing one embodiment of the wiring board according to the present invention.
- FIG. 33 is a view showing one embodiment of the wiring board according to the present invention.
- FIG. 34 is a diagram showing one embodiment of the wiring board according to the present invention.
- FIG. 35 is a diagram showing the relationship between the wiring and the position at which particles by sandblasting strike.
- FIG. 1 is a cross-sectional view of a part of a wiring board in which a wiring 120 is formed on a substrate 1 (core substrate 1) having a through hole 100.
- FIG. 2 shows a multilayer wiring board having a substrate 1 having a through hole 100, a multilayer wiring layer 3, an insulating layer 5 for stress relaxation (stress relaxation layer 5), and the like.
- FIG. 6 is a sectional view showing a part of FIG.
- FIG. 3 is a cross-sectional view showing a part of a multi-chip module in which a semiconductor device 9 (hereinafter, also referred to as a semiconductor element or a semiconductor chip) or the like is mounted on a multilayer wiring board 6 as an electronic device using the multilayer wiring board.
- FIG. 3 is a cross-sectional view taken along aa ′ of FIG.
- FIG. 4 is a cross-sectional view showing a state in which the multichip module is mounted on a mounting board (user board) 10.
- FIG. 5 is a perspective view of an example of the multichip module.
- the multilayer wiring layer 3 includes a plurality of thin film wiring layers 2, and the thin film wiring layer 2 has a wiring 120 and an interlayer insulating layer 110.
- the wiring 120 includes the wiring inside the via and the wiring pad.
- the stress relaxation layer 5 is not always necessary, and may be formed as necessary.
- an insulating layer may be formed between the outermost wirings of the multilayer wiring layer 3 and the stress relaxation layer 5.
- the multilayer wiring substrate 6 itself may be a substrate having external connection terminals, for example, the solder bumps 7, or may be a substrate having no external connection terminals.
- a glass substrate or a silicon substrate is used as the substrate 1 (also referred to as a core substrate 1 or an insulating substrate 1). Since the silicon material itself is conductive (semiconductor to conductor), when a silicon substrate is used as the insulating substrate 1, it is necessary to form an insulating film on its surface.
- Glass or silicon substrates have better smoothness than conventional ceramic substrates Therefore, a finer wiring pattern can be formed on a glass substrate or a silicon substrate than on a conventional ceramic substrate.
- the thermal expansion coefficient of the glass or silicon substrate is about 3 ppm / ° C to about 5 ppm / ° C.Since the thermal expansion of the substrate is smaller than that of a conventional ceramic substrate, short-circuiting of wiring due to thermal expansion may occur. And fine wiring can be formed.
- the thermal expansion coefficient of a glass substrate or a silicon substrate is closer to that of the silicon of the semiconductor element (semiconductor chip) mounted on the substrate than the ceramic substrate, so that between the glass substrate or the silicon substrate and the semiconductor device, The stress generated due to the difference in thermal expansion coefficient between the substrate and the semiconductor element is small, and the connection reliability between the multilayer wiring substrate and the semiconductor device is improved.
- the thermal expansion coefficient is about 3 ppm / ° C, and the thermal expansion coefficient is almost equal to that of the semiconductor element 9. Does not occur.
- the silicon substrate has excellent thermal conductivity, so that the heat treatment in the manufacturing process is uniform and high yields can be obtained. Further, when used as a wiring board, it is advantageous from the viewpoint of heat radiation characteristics.
- the silicon material itself is conductive (semiconductor to conductor), when a silicon substrate is used as an insulating substrate, it is necessary to form an insulating film on the surface thereof.
- the insulating film include a thermal oxide film formed on the surface by heating in steam and an organic resin film.
- the thermal expansion coefficient is slightly larger than that of the silicon substrate, about 5.0, but the thermal stress generated between the semiconductor device and the multilayer wiring substrate is sufficiently small.
- glass has an insulating property
- the surface of the glass substrate or the inner surface of the through hole is filled with a conductive substance, or the wiring is formed by plating or the like. There is no need to form an insulating film again, and the manufacturing process can be simplified.
- suitable glass compositions for this embodiment include soda glass, low alkali glass, non-alkali glass, and ion-strengthened glass. It is appropriately selected in consideration of the above.
- alkali-free glass or low-strength glass is preferable. This is because a glass having a lower Li-ion content generally has a lower linear expansion coefficient. In other words, since the linear expansion coefficient of silicon in a semiconductor device is as small as about 3 pp mZ ° C, the glass having a lower Al-ion ratio has a closer linear expansion coefficient between the insulating substrate and the semiconductor device, and the semiconductor device 9 and the multilayer wiring substrate This is because the thermal stress during 6 becomes smaller.
- the connection reliability between the semiconductor device 9 and the multilayer wiring board 6 depends not only on the characteristics of the glass material but also on the connection structure between the two and the selection of the underfill material. The glass material is selected in consideration of the above.
- connection reliability between the entire semiconductor module 100 and the mounting substrate 100 soda glass having a large alkali content is preferable. Since the linear expansion coefficient of the mounting substrate 10 is as large as 10 to 20 ppm / ° C, the difference in linear expansion coefficient between the multilayer wiring substrate 6 and the mounting substrate 10 increases as the alkali content of the glass increases. This is because the thermal stress is small.
- the connection reliability between the multilayer wiring board 6 and the mounting board 10 depends not only on the characteristics of the glass material but also on the material and structure of the stress relieving layer provided on the surface of the multilayer wiring board 6. Thickness, area, etc.), so select the glass material in consideration of these factors.
- Low alkali glass which has an intermediate alkali ion content between soda lime and non-alkali glass, is preferred.
- the thickness of the insulating substrate 1 is preferably from 100 to 100 / m, more preferably from about 300 to 500 Atm. If the thickness of the insulating substrate 1 is 1000 Aim or more, the cost of through-hole processing increases, which is not practical. On the other hand, if it is less than l OO / zm, handling properties such as transport in the substrate manufacturing process are inferior, and when the through hole 100 is formed, the strength of the insulating substrate 1 may be reduced and the insulating substrate 1 may be damaged. Confuse.
- This insulating substrate 1 has a through hole 100 formed by sand plast. You.
- the through holes 100 allow interconnections formed on both sides of the substrate to be interconnected and maintained.
- sandblasting as shown in FIG. 31, a film having anti-sandplast resistance is formed on a glass substrate (a), and an opening is formed in the film by using a photolithography technique (b) to form a mask. . Thereafter, abrasive particles are sprayed on the mask layer (c) to form a through hole while crushing the glass in the opening in minute units (d). Thereafter, by removing the mask (e), the insulating substrate 1 having the through holes is formed.
- the diameter of the through hole 100 is often different between one opening end and the other opening end.
- through-holes through-holes of almost constant diameter are easily formed, whereas in sand blasting, the surface of the substrate where sand blasting has started (the processing start surface) is the other.
- the diameter of the through hole 100 gradually decreases toward the (processing end surface).
- the reason for this shape is that if the hole becomes deeper as the processing proceeds, the pressure of the air carrying the processing powder decreases (pressure loss) and the efficiency of the processing powder itself decreases. .
- crushed powder of the glass to be processed is also generated, and since the direction of movement is opposite to that of the processed powder, a collision occurs that erases the kinetic energy of the processed powder. It is easier. It is also possible to make the opening diameters of the through-holes formed in the multilayer wiring board 6 the same on both sides as long as sand-blasting is performed from both sides. However, in that case, it is necessary to control the processing end point.
- FIG. 6 shows a through hole 100 formed by sandplast and a through hole formed by photoetching.
- the wiring on the inner wall of the through hole 100 has strong adhesion strength.
- plated wiring can be precisely formed on the inner surface of the through hole 100 after the formation of the power supply film.
- In order to adjust the angle of the taper there are methods such as changing the particle size of the particles used for the sand plast as the processing progresses and adjusting the wind pressure. You.
- the shape of the through-hole may be widened from the center of the insulating substrate toward the outside by sand branding from both sides.
- the time required for forming the through hole is shorter than when the through hole is opened from one side, and the diameter of the through hole at the opening end can be reduced.
- an insulating substrate having a through-hole in which the direction of the taper is opposite can be formed. If the taper direction of the through holes is the same, the insulating substrate may warp due to stress.However, if the direction of the taper of the through hole is different, the warping of the insulating substrate can be prevented, and then fine wiring is placed on the insulating substrate. Can be formed.
- the multilayer wiring board according to the present embodiment can be used, for example, as an interposer of a multi-chip module.
- FIG. 4 shows that the semiconductor device 9 is mounted on the surface of the insulating substrate 1 where the through hole 100 has a small opening diameter (primary side of the substrate), and the surface with the large opening diameter (secondary side of the substrate) is The figure shows a semiconductor module mounted on a mounting board 10 on which a semiconductor module is mounted. This allows semiconductor devices to be mounted and connected at a narrow pitch on the primary side of the substrate.
- the secondary side opening diameter of the through hole 100 is from 100 to 100 / m, and is desirably about 1/10 to 10 times the thickness of the insulating substrate 1. If the secondary opening diameter exceeds about 10 times the thickness of the insulating substrate 1, the mechanical strength at that portion of the insulating substrate 1, for example, the bending strength cannot be maintained. Conversely, when the secondary opening diameter is smaller than about 1Z10, which is the thickness of the insulating substrate 1, approximately 90 degrees, at least 88 degrees, is required to form a hole penetrating to the primary side. Since a taper angle is required, it is likely to be difficult to form wiring on the wall of the through hole. In addition, it becomes difficult for the processing powder to reach the inside of the hole, and as a result, the speed of sandblasting is reduced.
- the secondary side opening diameter of the through hole is from 200 ⁇ m to 300 ⁇ m, and is about / to about 1 times the thickness of the insulating substrate 1.
- the through-hole interior The wiring layout for interconnecting the wiring and the solder bumps 7 is also easy.
- the opening diameter on the primary side is from 5 im to 300 / im, more preferably from 10 ⁇ m to 100 um, and the thickness of the insulating substrate 1 is about 1 Z 50 force to about 1 / 5 times.
- the wiring of the multilayer wiring layer 3 on the primary side needs to have a narrow pitch, and a smaller opening diameter is desirable. That is, if the opening diameter on the primary side of the through hole 100 is reduced, more wiring channels can pass between the through holes, and as a result, the wiring of the thin film wiring layer 2 having a smaller number of layers can be formed. This is because the bow I can be turned.
- a conductive material exists on the inner surface of the through hole 100 that enables electrical connection on both surfaces of the insulating substrate 1.
- the copper wiring 101 is formed by forming a power supply film, for example, Cr / Cu on the inner surface of the through hole 100 by sputtering or the like, and thereafter, by electroplating. Note that an insulating material may be filled after the copper wiring 101 is formed.
- the through hole 100 is filled with a conductive material by paste printing or the like.
- the solder material may be melted and poured.
- a thin film wiring layer 2 composed of a wiring 120 and an interlayer insulating layer 110 such as a polyimide or polybenzobutene is formed, and each interlayer insulating layer 110 (a thin film wiring layer) is formed. 2) needs to be thick enough to ensure wiring insulation between layers and between lines. In the present invention, it is generally in the range of about 5 to 50 m, but more preferably about 10 to 20 ⁇ m.
- the interlayer insulating layer 110 is made of a high heat resistant resin.
- the diameter of the opening of the through hole 100 is small, and on the side (primary side), two thin film wiring layers 2 are formed.
- One thin-film wiring layer 2 is formed on the side (secondary side) where the diameter of the opening of 100 is large.
- the number of the thin film wiring layers 2 formed on both surfaces of the insulating substrate 1 is arbitrary, and can be freely set according to the design of the semiconductor module.
- the thin film wiring layers 2 may be formed one by one and laminated. That is, a wiring pattern is formed on the insulating substrate 1, and then the interlayer insulating layer 110 is formed. At this time, if a wiring is formed by a semi-additive plating process using a photolithography technique, high-density wiring can be achieved. Also, the wiring may be formed using a method such as screen printing. Then, a wiring pattern is formed on the interlayer insulating layer 110 formed as necessary, and a re-formed interlayer insulating layer 110 is formed. ⁇
- the insulating substrate 1 is a glass substrate or a silicon substrate, has a smoother property than the ceramic substrate, has a smaller thermal expansion coefficient, and has a thermal expansion coefficient close to that of the semiconductor device 9. Therefore, a fine wiring pattern can be formed on the substrate.
- the wiring pitch on a glass substrate is about 2 to 200 ⁇ . If the wiring pitch exceeds 200 micrometer, the number of layers cannot be reduced effectively. If the wiring pitch is less than 2 micrometers, the electrical resistance of the wiring will increase.
- the coefficient of thermal expansion of the glass substrate used in this example is about 5 pp mZ ° C, while the coefficient of thermal expansion of the interlayer insulating layer 110 made of a resin such as polyimide / polybenzocyclobutene is several 10 ppm. / ° C, thermal stress is generated due to the difference in thermal expansion coefficient.
- the interlayer insulating layer 110 is manufactured without considering the relative ratio of the thickness of the glass substrate 1 to the thickness of the interlayer insulating layer 110, the multilayer wiring board 6 will be warped or bent due to the density of the wiring pattern.
- the relationship between the thickness of the glass substrate and the thickness of the interlayer insulating layer 110 is adjusted so as to be about 30 to 50 times the thickness. Can be kept small.
- the coefficient of thermal expansion is smaller than that of polyimide-polybenzocyclobutene, which is advantageous from the viewpoint of suppressing substrate warpage.
- a fine wiring pattern can be formed on the substrate. Further, since fine wiring can be formed on a glass or silicon substrate, the number of thin film wiring layers 2 on the insulating substrate 1 can be reduced as compared with a conventional ceramic substrate, and the multilayer wiring substrate can be thinned.
- the wiring (first wiring) formed immediately above the insulating substrate 1 exchanges signals between the user substrate and the semiconductor device 9.
- the second wiring formed on the first interlayer insulating layer is the power supply line or the duland line
- the third wiring formed on the second interlayer insulating layer is the semiconductor wiring. It may be formed as a signal line for exchanging signals between the body devices 9 (LSI).
- the multilayer wiring layer 3 into at least a two-layer structure, three wiring layers can be formed, and signal lines between the semiconductor device 9 and the user substrate 10 and signals between the semiconductor devices 9 are formed. Wiring, power supply wiring and ground wiring can be separated, high-speed and fine wiring patterns can be formed, and it is also effective in preventing signal noise and the like. Needless to say, due to restrictions on wiring patterns, it is not necessary to form all of the wiring for exchanging signals between the semiconductor devices 9 (LSI) on the second interlayer insulating layer. It suffices that the number of wirings for exchanging signals between the devices 9 (LSIs) be larger on the outermost surface of the multilayer wiring board than on other wiring layers.
- a power line or a ground line is formed in the wiring (first wiring) formed immediately above the insulating substrate 1, and the second wiring formed on the first interlayer insulating layer 110 is formed. If the signal wiring for exchanging signals between the user board and the semiconductor device 9 and the signal lines for exchanging signals between the semiconductor devices 9 (LSI) are arranged together in the wiring, the multilayer wiring is formed.
- Layer 3 can be a single layer.
- the multilayer wiring layer 3 is a single layer, or whether two or more layers are required depends on the logic scale of the semiconductor device 9, its layout, required high-speed signal characteristics, and the like.
- the role of wiring formed on each interlayer insulating layer is changed, it is effective to change the wiring width and wiring shape for each layer.
- the stress relaxation layer 5 is formed on the secondary side of the board mounted on the user board.
- the insulating substrate 1 is made of low-strength glass, its linear expansion coefficient is about 5 ppm / ° C, while the linear expansion coefficient of the semiconductor chip 9 is about 3 pp mZ ° C.
- the linear expansion coefficient of the whole module is almost equal to the linear expansion coefficient of the glass substrate, and is about 5 ppmZ ° C. Therefore, thermal stress generated between the insulating substrate 1 and the semiconductor device 9 is small.
- the linear expansion coefficient of the mounting substrate 10 on which the semiconductor module 100 About 10 to 20 ppm ⁇ C. In the case of the most common glass epoxy substrate, it is about 15 to 18 pp mZ. C. Therefore, the thermal stress generated between the semiconductor module 100 and the mounting substrate 10 is large.
- the thick insulating layer 5 stress relieving layer
- the thickness of the stress relaxation layer 5 is from about 1/10 to about 1/2 of the thickness of the insulating substrate 1, or the diagonal length of the insulating substrate. On the other hand, it is preferably about 1/300 to about 1/20.
- the thickness of the insulating substrate 1 is about 100 ⁇ m to about 100 ⁇ m
- the thickness of the stress relaxation layer 5 is preferably about 100 to 500 ⁇ m
- the insulating substrate 1 When the thickness is about 300 micrometers to about 500 micrometers, it is about 30 to 250 micrometers. The thickness and physical properties of the stress relaxation layer will be described later.
- the stress relieving layer 5 is formed on the insulating substrate 1 or by screen printing using a mask, but a spray coating / dispense, a force render / co-photolithography technique or the like may be used.
- the stress relaxation layer when mask printing (screen printing) is performed on the stress relaxation layer 5, the stress relaxation layer can be formed at a desired position. Also, an inclined portion can be formed at the end of the stress relaxation layer. Depending on the material of the stress relaxation layer, etc., it is possible to prevent the inclined portion from being formed, and it is also possible to control the angle of the inclined portion.
- the stress relieving layer is formed by stamping
- an insulating material for stress relieving is applied to a stamping die, and the shape of the insulating material is cured to transfer the shape of the stress relieving layer onto the substrate. It is possible to select an insulating material that does not change. In this case, there is a feature that the shape of the end portion is more likely to be constant than in the printing method.
- the spray coating and the dispensing method do not use a print mask or a stamping mold
- the shape at the time of forming the stress relaxation layer has a degree of freedom, and if the nozzle shape is selected appropriately, the print mask and stamping mold do not It is possible to form a stress relaxation layer that is difficult to form.
- the thickness of the stress relaxation layer can be adjusted by adjusting the spray amount, and the range of the thickness adjustment can be widened. The method of attaching a semi-cured or uncured resin sheet allows the formation of a thick film stress relaxation layer and uses a sheet-like insulating resin in advance, so the surface of the stress relaxation layer has excellent flatness. .
- the stress relaxation layer may be formed by combining these methods instead of using these methods alone.
- a through hole 100 is also formed in the stress relaxation layer 5.
- This through hole 100 is formed by not only sand blasting but also laser processing or photo etching.
- the stress relaxation layer 5 is formed in a place where the through hole is not formed in the wiring board, and the surface of the stress relaxation layer is formed. (Including inclined surfaces) to form wiring.
- screen printing in which printing is performed using a metal mask or the like, is effective.
- the stress relieving layer 5 is not an essential component of the multilayer wiring board 6, and the stress relieving layer 5 may be formed on the multilayer wiring board 6 as long as the thermal stress generated by the semiconductor module 100 and the user board 10 is within an allowable range. There is no need to form 5.
- thermal stress occurs between the semiconductor module 100 and the user substrate 100, reliability may be ensured by using an underfill instead of the stress relaxation layer 5.
- an underfill may be used if the user desires higher reliability.
- the material of the interlayer insulating layer 110 is used.
- the linear expansion coefficient can be changed in the thickness direction of the multilayer wiring board 6. That is, on the primary side of the insulating substrate 1, an inter-layer insulating layer is formed of a material having a small coefficient of linear expansion to approximate the coefficient of linear expansion of the semiconductor device to be mounted.
- an interlayer insulating layer is formed of a material having a large coefficient of linear expansion so that the coefficient of linear expansion approaches the substrate on which it is mounted.
- the thin film wiring layers 2 are formed one by one and laminated, it is possible to easily change the linear expansion coefficient of the thin film wiring layers as necessary. it can.
- the thermal stress between the semiconductor device 9 and the mounting substrate 10 can be reduced by the multi-layer wiring substrate without specially providing the stress relaxation layer 5, and the connection reliability can be ensured.
- the insulating substrate 1, which is the core substrate of the multilayer wiring board is not limited to a glass or silicon substrate, but may be a conventional ceramic substrate or a metal core substrate. Is also good.
- the through holes may be formed not only by sandblasting but also by laser processing or photolithographic etching.
- a multilayer wiring board having no insulating substrate 1 and laminated thin film wiring layers having different linear expansion coefficients may be used.
- the multilayer wiring board can reduce the thermal stress between the semiconductor device 9 and the mounting board 10 to secure the connection reliability. Since the thickness of the insulating substrate 1 can be omitted, a thinner and multilayer wiring substrate can be realized. Therefore, by using such a multilayer wiring board, a thinner electronic device can be realized.
- a semiconductor chip such as LSI is mounted on the primary side of the multilayer wiring board 6.
- the semiconductor device 9 may be a semiconductor device such as a semiconductor chip, a BGA, a CSP, a wafer-level CSP, or a lead-type semiconductor device such as a QFP or a TSOP. Further, the semiconductor device 9 itself may have a layer for relaxing a stress generated between the semiconductor device and a substrate on which the semiconductor device is mounted.
- an insulating layer 50 (underfill layer) may be filled between the semiconductor device 9 and the substrate on which the semiconductor device 9 is mounted.
- the semiconductor chips 9 to be mounted are not limited to the same type, and for example, a plurality of different types of semiconductor chips may be mounted on the multilayer wiring board 6 as shown in FIG.
- A may be a microcomputer
- B may be a flash memory
- C may be a DRAM
- D may be a combination of individual components such as capacitors.
- FIG. 11 shows a cross section a—a ′ of FIG.
- semiconductor packages such as QFPCSP and passive parts such as resistors and capacitors It may contain one or more products. It is desirable that the semiconductor chips, semiconductor packages, and passive components used here are of the surface mount type. If different types of semiconductor chips are mounted on the multilayer wiring board 6, the wiring required to connect the different semiconductor chips is made in the uppermost layer of the multilayer wiring layer 3, and the lower wiring layer is ground wiring or The signal wiring is formed. Furthermore, only the wires that need to be finally electrically connected to the user board may be connected through the through holes 100 of the insulating board 1.
- the combination of different semiconductor chips includes DRAM and microcomputer, DRAM and microcomputer and DSP, DRAM and microcomputer and ROM, DRAM and flash memory, DRAM and SRAM and flash memory, ASIC and DRAM. and so on.
- a combination of a microcomputer with a built-in flash, an ASIC, and a DRAM is used.
- a microcomputer and flash memory, a microcomputer with built-in flash and DRAM, or a combination of microcomputer, flash memory and DRAM are suitable. Flash memory is used to reduce power consumption, but if flash memory alone does not have enough memory capacity, use a highly integrated DRAM. Chips may be stacked as needed.
- Mobile terminals for example, mobile phones use the same configuration as digital still cameras, but mobile phones require lower power consumption than digital still cameras. Often set equal to or greater than capacity! / ,.
- the semiconductor element 9 (semiconductor chip) and the multilayer wiring board 6 are connected by external connection terminals such as bumps 300.
- the semiconductor element 9 having the bump 300 is mounted on the multilayer wiring board 6 and connected by reflow.
- bumps 300 may be formed on the multilayer wiring board 6.
- bare chip semiconductor element that is not packaged
- the bump 300 may be made of a wire such as gold formed into a convex shape by an ultrasonic bonding device, or a metal such as tin, lead, copper, silver, bismuth, zinc, and indium, alone or in combination of two or more.
- the mixed alloy can be used as the solder bump 300 Wear.
- a resin containing a conductive material such as silver or gold can be used as the bump 300.
- Solder bumps 300 are prepared by mixing fine particles of solder with a material such as rosin, printing them on the electrodes of a semiconductor device using an appropriate mask, and then heating the solder to a temperature higher than the melting temperature of the solder. It can also be formed by melting.
- the paste-like resin material is printed on an electrode of a semiconductor device using an appropriate mask, and is cured or semi-cured by heating. Bump formation is also possible by a method. Furthermore, an oxide film on the surface of the electrode is removed, a flux having an appropriate tackiness is applied on the electrode, and a solder pole having an appropriate particle size is aligned on the electrode using a mask or the like, and the solder is removed by a reflow oven or the like. Bumps can also be formed by heating above the melting temperature. Of course, these can also be applied to the formation of the external connection terminal 7.
- the electrodes provided on the semiconductor device 9 to be connected to the bumps 300 are made of aluminum or copper electrodes formed in a process called a pre-process, or after the pre-process, and further from the electrodes such as wafer level CSP, copper is applied to the surface of the semiconductor device. It is possible to use an electrode formed after rewiring is performed using such wiring. By performing a surface treatment such as nickel and gold on the surface of the electrode, the wettability between the bump and the electrode surface is improved, and the bump material remains in the electrode during a heating step such as mounting a semiconductor module on an external substrate, which will be described later. The diffusion can prevent a decrease in bonding strength between the bump and the electrode portion.
- the solder is a so-called lead-free solder such as Sn—Zn, Sn—Ag, or Sn—Ag—Cu, for example, Sn—3.0.
- OA g—0.5 Cu may be used.
- solder bump since lead-free solder is harder than conventionally used lead solder, it is difficult to reduce thermal stress generated between the semiconductor device 9 and the multilayer wiring board 6 by the solder bump.
- the semiconductor device 9 and the multilayer wiring substrate 6 can be used. Connection reliability can be ensured.
- the physical property values of the interlayer insulating layer for example, the coefficient of thermal expansion and the elastic coefficient are changed in the thickness direction of the multilayer wiring board. Specifically, the interlayer insulating layer on the outermost surface on the primary side and the multilayer wiring board By reducing the thermal stress generated by approaching the coefficient of thermal expansion of the semiconductor chip 9 mounted on the board 6 and reducing the generated thermal stress, even when lead-free solder is used, the Connection reliability can be ensured.
- the melting point of the solder bump used for the connection on the primary side must be higher than that of the solder on the secondary side when the solder is used for the connection on the secondary side. In other words, on the primary side and the secondary side, it is necessary to change the temperature of the solder connection and establish a temperature hierarchy.
- An external connection terminal 7 is formed on the secondary side of the multilayer wiring board 6 to establish connection with the user board 10.
- the external connection terminal 7 may be made of a resin or the like containing conductive particles in addition to the solder hole, similarly to the bump 300. Depending on the connection method with the external board, it can be used without forming balls or terminals.
- solder bumps are formed as external connection terminals 7, the distance between adjacent bumps (bump pitch) is about 500 ⁇ m to 800 im, but the pitch of the connection terminals on the user board is inevitable. Is restricted to. In general, as the connection terminal pitch becomes narrower, the price of the user board increases, so the connection pitch is determined in consideration of the cost of the entire module.
- a typical connection pitch is about 500 to 800 mm as described above, but there are cases where the connection pitch exceeds 100 mm.
- the diameter of the solder bump 7 is appropriately selected according to the bump pitch, but the diameter of the solder bump is at most about 0% of the bump pitch.
- ⁇ 3 such as Sn—Zn system, Sn—Ag system, or Sn—Ag—Cu system, and free solder, for example, Sn— 3.
- OA g-0.5 Cu may be used.
- lead-free solder is harder than conventional lead solder, so when using lead-free solder, the thermal stress generated between the multi-chip module and the mounting board 1 It is difficult to ease yourself.
- a stress relaxation layer is provided, By changing the coefficient of thermal expansion of the interlayer insulating layer in the thickness direction of the multilayer wiring board to relieve the stress, even when lead-free solder is used, the multi-chip module and the mounting board 10 Connection reliability can be ensured.
- the multilayer wiring board 6 in the present embodiment not only plays a role as an interposer of the semiconductor chip but also occurs between the semiconductor device 9 (semiconductor chip, LSI, etc.) and the multilayer wiring board 6 and the mounting board 10. Relieve thermal stress. Furthermore, if the thermal stress generated between the semiconductor module 100 and the user substrate 100 can be reduced by means such as a stress relaxation layer, the semiconductor module 100 may be mounted on the user substrate 100. Need not be filled with underfill.
- an underfill may be formed between the semiconductor module and the mounting board 10 (user board).
- the resin used as the underfill may be epoxy resin, phenol resin, silicone resin, etc.
- a filler such as silicon dioxide and aluminum aluminum oxide, a coupling agent, a coloring agent, a flame retardant, and the like may be added to a mixture of two or more kinds as necessary.
- a glass substrate or a silicon substrate having a through hole is used as a semiconductor module
- wiring can be formed at a high density on an insulating substrate. Therefore, since the number of thin film wiring layers can be reduced, the multilayer wiring board can be formed thin, and the semiconductor module can be reduced in thickness and size.
- the fact that the number of thin film wiring layers 2 is small means that the wiring length from the semiconductor chip 9 such as LSI to the user substrate 10 becomes shorter, so that higher-speed signals can be exchanged.
- the multi-chip module has a mechanism to relieve stress, it is possible to omit the underfill when mounting this multi-chip module on the user's board, and to reduce the work of the user who manufactures the electronic device. Can also be reduced.
- a thick insulating layer serving as a stress relieving layer is formed on a glass or silicon substrate serving as an insulating substrate, and a through hole is formed in the insulating layer by sand plasting.
- the multilayer wiring substrate 6 can be manufactured in a wafer state, or the substrate can be manufactured in a square thin plate shape.
- FIG. 28 shows a state in which a large number of pieces are taken using a glass substrate or a silicon substrate 301.
- a plurality of module circuits are formed on a glass substrate or a silicon substrate, and predetermined semiconductor devices 9 (semiconductor chips), resistors, capacitors, etc. are mounted, and solder balls as external connection terminals are mounted. Accordingly, the space between the semiconductor device and the substrate is filled with resin. Thereafter, each module portion can be cut out individually by a method similar to the dicing of a silicon wafer to obtain a desired semiconductor device. In the following, for the sake of simplicity, description will be made using a part of the structure of the multilayer wiring board.
- FIG. 13 is a flowchart illustrating the manufacturing method according to the present embodiment.
- the process for forming the external connection terminals (secondary bumps 7) on the secondary side of the multilayer wiring board is the method of manufacturing the multilayer wiring board.
- the secondary side bump does not necessarily have to be formed.
- FIG. 14, FIG. 15, and FIG. 16 are process diagrams illustrating a method for manufacturing a multilayer wiring board according to the present invention.
- a glass substrate or a silicon substrate is prepared as the insulating substrate 1 used for the wiring substrate. If necessary, perform surface treatment and cleaning of the front and end surfaces. Appropriate edge surface treatment can reduce manufacturing defects.
- Figs. 14, 15, and 16 show that in the case of a silicon substrate, the insulating film formed on the surface is integrated into an insulating substrate. Board 1 is displayed.
- a wiring 120 is formed on the surface of the insulating substrate 1.
- a semi-additive method can be used.
- the wiring material is preferably Cu, Al, Ag, and Au from the viewpoint of conductivity, but Cu is desirable in consideration of corrosiveness, migration resistance, and price. Since Cu is a ductile material, it can be used as a mask for sandblasting.
- an interlayer insulating layer 110 is formed on the wiring pattern.
- the thickness of the interlayer insulating layer 110 is generally in the range of about 5 to 50 m, but is more preferably about 10 to 20 ⁇ m.
- a polyamide resin, a polyimide resin, a polybenzocyclobutene resin, a polybenzoxazole resin, or the like can be used as the interlayer insulating layer 110.
- the thin film wiring layers 2 are formed one by one on the insulating substrate 1, the number and thickness of the thin film wiring layers can be changed as necessary.
- the thickness of the wiring layer and the thickness and material of the interlayer insulating material by utilizing the formation of each layer one by one. For example, by using materials having different dielectric properties for the insulating material A of the insulating layer between the ground layer and the signal layer and the insulating material B between the lines of the signal layer, the ground layer and the signal layer and the signal layer can be connected to each other. It is possible to adjust the strength of the electrical coupling of the wiring, and it is possible to respond to high-speed wiring. Also, by changing the material of each interlayer insulating layer, the coefficient of linear expansion can be changed in the thickness direction of the substrate.
- Fig. 14b two wiring layers are formed on the surface (primary side) of the insulating substrate 1 on which the semiconductor chip is mounted, and 1 layer is formed on the surface (secondary side) on which the semiconductor module is mounted.
- the wiring forming method may be different between the primary side and the secondary side of the insulating substrate.
- the secondary side of the insulating board is connected to the mounting board (user board), so wiring with a narrower pitch than the primary side is not required. Therefore, for example, the photolithography
- the secondary side wiring may be formed by printing due to the adhesion.
- Fig. 17 and Fig. 35 show the wiring pattern on the secondary side on the insulating substrate 1.
- c Of the pads shown in Fig. 17 and Fig. The barrel portion is indicated by oblique lines.
- the pad in advance so as to surround the position where the through hole 100 is formed, it is possible to reduce the occurrence of microcracks on the surface of the insulating substrate 1 by sandblasting. The strength of the insulating substrate can be maintained.
- a thick insulating layer 5 is formed on the surface (secondary side) of the insulating substrate 1 on which the semiconductor module is mounted on the user substrate by stencil printing / photolithography or the like.
- the insulating layer 5 plays a role of a stress relaxation layer, and can relieve a thermal stress caused by a difference in linear expansion coefficient between the semiconductor module and the mounting substrate 10.
- a method such as laser trimming after screen printing using a stencil mask.
- through-holes 100 connecting the wiring layers on both surfaces of the insulating substrate 1 are formed by the steps shown in FIGS. 15A and 15B.
- the material (hardness) of the stress relaxation layer 5 and the insulating substrate 1 are different, and it is difficult to form a through hole 100 in the stress relaxation layer 5 by sand blast. Therefore, a hole (dent) is formed in the stress relaxation layer 5 by laser processing or the like, and then a through hole 100 is formed in the insulating substrate 1 by sand blast.
- the following is a typical example of a method for forming a mask for forming the through hole 100 in the multilayer arrangement and the substrate 6.
- the first method is a method using a photolithography technique. Specifically, a blast resist serving as a mask during sandblasting is formed on the stress relaxation layer, and the blast resist and the stress relaxation layer are opened by photolithography. This opened blast resist becomes a mask for forming a through hole in the stress relaxation layer by the sand plast. In this method, both the blast resist and the stress relieving layer can be simultaneously opened. However, both the blast resist and the stress relieving layer must be photosensitive materials.
- the second method is a method using laser processing.
- a blast resist is formed on the stress relaxation layer, and the blast resist and the stress relaxation layer are formed.
- the sum layer is collectively opened by laser processing.
- the second method can be used irrespective of the photosensitivity of the blast resist and the stress relaxation layer. Further, since the plast resist used in the second method does not necessarily need resolution characteristics, a material having more excellent blast resistance than the first method can be selected.
- a photosensitive blast resist is formed on the stress relaxation layer, and an opening pattern is formed in the blast resist by photolithography.
- the stress relaxation layer is etched through the opening of the plast resist to form a hole (dent) in the stress / relaxation layer 5.
- the blast resist needs to have heat resistance and sand plast resistance.
- (1) apply a photosensitive resin having sand blast resistance to the thin film wiring layer 2, or (2) A method in which a photosensitive resin having sandplast resistance in the form of a dry film is attached to the photosensitive resin.
- the mask pattern can be formed by screen printing depending on the opening diameter of the through holes, the hole pitch, and the positional accuracy. In such a case, if necessary, fine adjustment of the positional accuracy and the processing accuracy can be performed by additional processing using a photolithographic laser.
- the shape shown in FIG. 15A is obtained by the above-described first to third methods. At this time, the formed recessed portion may reach the insulating substrate 1, but does not necessarily have to reach.
- the conditions for forming the through-holes 100 must be appropriately selected according to the characteristics of the substrate material, particularly the elastic modulus and rupture toughness of the substrate, but when the specific gravity is 2.0 to 10.0, the bulk material is bent. It is desirable to use processed granules having a strength of 0.1 to 2. OGP a! The processing speed tends to increase as the grain size of the processed grains increases, but on the contrary, the problem of crack opening cracking and chipping described later tends to occur.
- the particle size (#) of the processing powder is determined in consideration of the substrate material, the processing size (thickness, diameter) of the through hole, the desired processing speed, and the like. It is desirable to be within the range. In this embodiment, # 500, # 600, # 700, # 800, Any of # 900, # 10000, # 1100, # 1200, or a combination thereof was used as appropriate. Although the processed powder is circulated and reused, it collides with each other and shatters during use. Therefore, it is advisable to appropriately size the powder so that the particle size is maintained in the above range. In addition, crushed powder from the through-hole portion of the substrate is also mixed in. If necessary, this is removed.
- the sandblasting machine used for forming the through-holes in the present embodiment has a circulation / reuse mechanism and a spheroid mechanism. It is practical to use a sandplast machine that is set up so that the recycle and spheroids are automatically operated in parallel with the processing of through holes.
- resin processing residue may remain on the surface of the insulating substrate 1, but the resin processing residue may be removed during the sandblasting performed on the insulating substrate 1. Is done. Normally, when holes are formed in a resin by laser processing, resin residues (smears) that cause a reduction in wiring connection reliability are formed, and a process of desmearing by chemical treatment or the like is required. In the manufacturing process of the present embodiment, since the dent portion formed by the laser processing is sandblasted, the smear can be removed at the sandblasting stage, and there is no need to perform a chemical desmear process.
- the through hole 100 is formed by sand plast, the diameter of the through hole 100 is formed to be different from one opening end to the other opening end. With this, the power supply film is easily formed on the inner surface of the through hole 100 by a film forming method such as sputtering and electroless plating.
- the sandblast penetrates the insulating substrate 1 Later, it is possible to prevent the primary-side interlayer insulating layer 110 (thin film layer, second layer 2) from being cut by sandblasting.
- the mask is removed by etching or the like.
- microcracks generated around the through hole 100 of the insulating substrate 1 in the process of forming the through hole 100 are removed.
- micro cracks generated in the insulating substrate 1 are roughly classified into two types, so-called median cracks and lateral cracks.
- Median crack Cracks are cracks extending in the depth direction with respect to the side wall surface of the through hole, while lateral cracks extend in the creepage direction with respect to the side wall surface of the through hole.
- the rate of occurrence of lateral cracks and median cracks is (1) hardness of processed grains, (2) shape of processed grains, (3) grain size of processed grains, (4) processed grains. It depends on the number of times the object collides with the workpiece in a unit time, (5) the angle at which the processed particles collide with the workpiece, and (6) the pressure of the gas transporting the processed particles. . Therefore, it is preferable to use a plast machine having a nozzle capable of adjusting the number of collisions per unit time, the collision angle, the pressure of the carrier gas, and the like. By selecting an appropriate blasting machine and processing conditions, both processing efficiency and substrate strength can be achieved.
- the cracks in the microphone opening can be removed.
- a method for heating the periphery of the through hole include a method such as laser annealing.
- the entire glass substrate is heated and the mouth cracks are self-fused and then cooled slowly, Since the strain accumulated in the substrate is released, the failure rate due to substrate cracking can be reduced.
- wiring is performed on the inner wall surface of the through hole 100 and the outermost surface of the multilayer wiring board. Is formed.
- a power supply film is formed on the inner wall of the through hole 100 by a method such as sputtering CVD or vapor deposition.
- a method such as sputtering CVD or vapor deposition.
- the power supply film for example, a multilayer film of chromium Z copper is preferable, but any known and commonly used film configuration as a plating power supply film such as a titanium / copper multilayer film may be used.
- the function of chromium is to ensure adhesion between the substrate and copper, and its film thickness is about 75 nanometers, and at most about 0.5 micrometer.
- the thickness of the copper of the power supply film is about 0.5 ⁇ m, up to 1 ⁇ m.
- FIG. 2 shows the state before the formation of the inter-wiring insulating film (inter-wiring insulating film) on the outermost surface of the substrate.
- the second method uses a subtractive method for forming wiring.
- the same method as in the first method up to the point where a multilayer film made of chromium / copper etc. is formed by sputtering as the wiring force.After that, plating is performed on the entire surface, and then etching resist is formed on the front and back of the insulating substrate. An etching mask pattern is formed by a lithography technique. After wiring is formed by etching, the resist is removed and an inter-line insulating film is formed.
- the inside of the through hole is filled with a conductive material. For example, paste printing or the like is used for filling the conductive material.
- a sputter film Prior to filling the conductive material, a sputter film may be formed on the inner wall of the through hole in the same manner as in the above two methods. Forming a sputtered film on the inner wall surface has the following effects: (1) improving the filling property by improving the smoothness of the inner wall surface; and (2) improving the adhesion between the filler and the insulating substrate.
- the sputter film to be formed should have a large amount of copper / copper as in the first and second methods. It may be a layer film or a single layer film. If solder is used as the conductive material, laminate a film of chromium or titanium to ensure adhesion to the insulating substrate and a film of copper, nickel, or gold to ensure solder wettability. Desirably, it is a membrane. After filling the conductive material inside the through-hole, wiring is formed on the substrate surface by the semi-additive method or the subtractive method. Note that, depending on the wiring pattern, filling of the through-holes and formation of the wiring pattern may be achieved in a batch by paste printing.
- a conductive wiring of a through hole connecting the front and back of the substrate and a wiring on the substrate surface (secondary side) are formed.
- the wiring on the substrate surface is laminated in a required number of layers, but is preferably copper wiring from the viewpoint of electric resistance. If necessary, a heterogeneous metal may be formed on the copper surface from the viewpoint of adhesion reliability, insulation reliability, and the like.
- the insulating substrate 1 is a glass substrate, since glass is a material having an insulating property, there is no problem if wiring or the like is formed so as to directly contact the inner wall of the through-hole. From the viewpoints of migration resistance, moisture resistance, and the like, an insulating layer may be formed so as to cover the surface of the inner wall surface of the through hole.
- the insulating substrate 1 is a silicon substrate, since the silicon has conductivity, the inner wall surface of the through-hole should be covered before forming the wiring for connecting the front and back of the wiring substrate 1. It is necessary to provide an insulating layer on the surface.
- the multilayer wiring board 6 having the through holes 100 can be formed.
- the multilayer wiring board may be shipped in a state in which multiple boards can be obtained, or the multilayer wiring board may be diced and individually shipped.
- dicing may be performed after mounting a semiconductor chip or the like to form a multi-chip module.
- a semiconductor module 9 is formed by mounting a semiconductor device 9 and a capacitor on a multilayer wiring board 6 using an external connection terminal 300 such as a solder pump or the like and an anisotropic conductive sheet (ACF). .
- external connection terminal 300 such as a solder pump or the like and an anisotropic conductive sheet (ACF).
- ACF anisotropic conductive sheet
- solder bars for secondary connection
- solder bumps are formed on the primary side of the wiring board in accordance with the external terminal pitch of the semiconductor device 9.
- the bump pitch is generally in the range of about 50 to 500 ⁇ .
- the bump size is adjusted to be about 15 to 80%, preferably about 30 to 65% with respect to the bump pitch.
- the semiconductor device 9 is mounted on the multilayer wiring board 6 using the formed primary bumps.
- the pitch of the primary side bumps is about 50 to 500 ⁇ m.
- an underfill agent is filled between the wiring substrate 6 and the semiconductor device 9 or potting is performed on the upper portion of the semiconductor device 9.
- a material may be applied. If the bump size is as small as 200 micrometers or less, the mechanical strength may decrease due to the reduction in the volume of the bump. In this case, the underfill agent and the potting material must be used alone. Or, if used in combination, problems such as reduced reliability will not occur.
- bumps 7 (secondary side bumps) for mounting the semiconductor module on the mounting board 10 are formed.
- the wiring of the semiconductor device 9 is electrically connected to the primary-side bump 7, and a fine pitch is realized by the multilayer wiring board 6.
- the bump 7 (secondary bump) for mounting the semiconductor module on the mounting substrate 10 is formed after the formation of the primary bump.
- the primary side bump may be formed after the secondary side bump is formed.
- the melting point of the solder bump 7 (secondary side bump) becomes When the melting point is lower than the melting point of the bump, perform the secondary connection after the primary connection. That is, after forming the solder bumps 300 and mounting the semiconductor chip 9, it is preferable to form the solder bumps 7 and mount the semiconductor module on the mounting board 10.
- FIG. 3 although two semiconductor devices 9 are shown, the number of the semiconductor devices 9 is arbitrary, and a plurality of semiconductor devices 9 (semiconductor chips and the like) are mounted on the multilayer wiring board 6 to form a so-called multi-chip It goes without saying that modules can be formed.
- the through-holes 100 are opened by the sandplast, it is not necessary to use a high-cost photosensitive glass as a substrate material.
- a multilayer wiring board can be manufactured.
- FIG. 18 is a flowchart illustrating the manufacturing method according to the present embodiment.
- the main difference from the first embodiment is the order of the process of forming the through holes 100 in the insulating substrate 1.
- a glass substrate or a silicon substrate is prepared as the insulating substrate 1 used for the wiring substrate, and if necessary, the surface and the end surface are subjected to surface conditioning treatment, cleaning treatment, and surface insulation treatment. I'll do it.
- through holes 100 are formed only in the insulating substrate 1 by sandblasting as in the first embodiment. Due to this sand blast, microcracks are generated on the insulating substrate 1.
- microcracks generated on the insulating substrate 1 are removed by the same method as in the first embodiment.
- a hole 120 is formed on the through-hole 100 of the insulating substrate 1 and the insulating substrate 1. Similar to the first embodiment, the wiring can be formed by using a semi-additive method or a subtractive method.
- a power supply film is formed on the inner surface of the through hole 100 and the three surfaces of the front and back surfaces (the primary surface and the secondary surface) of the insulating substrate 1.
- the power supply film may be formed from both sides of the substrate at the same time, or may be formed on the primary surface and the secondary surface one by one. From the viewpoint of simultaneous formation on three surfaces, the electroless plating method is more efficient.
- the power supply film is formed by sputtering, the film is formed on the front and back of the substrate, especially when the power supply film is formed on the secondary surface.
- the formation of the power supply film on the inner wall of the through hole can be achieved.
- the power supply film include a chromium film and a multilayer film of copper as in the first embodiment. There are the following two methods for forming wiring after forming the power supply film.
- the first is a semi-additive process.
- a resist is formed on the front and back surfaces (primary and secondary surfaces) of the insulating substrate 1, and a resist pattern that is the reverse pattern of the desired plating wiring is formed by photolithography technology, and then the wiring is formed by plating To form
- the inner wall of the through-hole 100 and the front and back of the substrate can be collectively plated.
- the pattern separation process as usual, the pattern can be separated at a stroke between the wiring on the inner wall of the through hole and the wiring on the front and back of the substrate.
- the wiring material include Cu, Al, Ag, Au, and Ni.
- the second method is a subtractive process.
- the inner wall of the through-hole 100 and the front and back surfaces of the substrate can be collectively plated.
- An etching resist is formed on the plating film, and a resist pattern serving as a reverse pattern of a desired distribution is formed by a photolithography technique. Thereafter, the wiring is separated by etching.
- the wiring material is Cu, A1, Ag, Au, Ni, etc., as in the first method.
- the through-hole 100 is filled with a filler.
- the filler need not necessarily be a conductive material, but may be an insulating material. It is desirable that the material has a high filling property that can be filled by a simple filling method such as paste printing. If it is not possible to fill the through hole 100 with one printing, it is necessary to print several times.
- Figure 21 shows an unfilled part (hereinafter referred to as unfilled void 200) in the center of through-hole 100 when paste printing was performed 5 times to fill through-hole 100. This shows the appearance.
- unfilled void 200 an unfilled part in the center of through-hole 100 when paste printing was performed 5 times to fill through-hole 100.
- the inside of the void is changed. Since the expansion and contraction of air occurs, The wire may be easily broken, or the strain may accumulate inside the insulating substrate, and the strength of the insulating substrate 1 may be reduced.
- unfilled voids 200 are formed in the first printing process, a part of the pressure on the paste will escape in the form of void compression during the second and subsequent printing, resulting in insufficient printing pressure. As a result, complete filling is not possible. Since the pressure loss is large near the primary end face of the insulating substrate 1 where the diameter of the opening is small, if the printing pressure is insufficient, an unfilled portion 201 may be formed near the primary end face. .
- an interlayer insulating film such as polyimide / polybenzobutene or a line insulating film above the through hole including the unfilled void 200. This is because the void expands when heated in the process of curing the insulating film, and under the influence, the insulating layer present on the substrate surface and being cured is deformed.
- Another solution is to apply a conductive material or the like to the hollow of the unfilled portion 201 generated near the primary end face before forming the wiring on the insulating substrate 1. By doing so, even if there is an unfilled portion 201, the surface on the insulating substrate 1 becomes flat. What is necessary is just to use silver paste etc. as a conductive material, and to print this in the hollow of the unfilled part 201.
- a multilayer wiring layer 3 composed of a thin film wiring layer 2 having a wiring 120 and an interlayer insulating layer 110 is placed on an insulating substrate 1 filled with through holes 100.
- the wiring forming process itself is essentially the same as in the first embodiment.
- a stress relaxation layer 5 is formed as necessary, and a hole (via hole) is formed in the stress relaxation layer 5 by photo-etching or laser processing.
- the process of forming the stress relaxation layer 5 is essentially the same as that of the first embodiment.
- wiring is formed on the holes of the formed multilayer wiring layer 3 and the stress relaxation layer 5 and on the surface thereof to complete the multilayer wiring board 6.
- the steps from the bump formation to the module formation after the completion of the multilayer wiring board 6 are essentially the same as those in the first embodiment.
- the insulating substrate 1 is filled with the insulating substance, the strength of the insulating substrate 1 and the multilayer wiring board 6 is increased as compared with the case where the through holes 100 are not filled.
- the wiring formation on the inner wall of the through hole 100 and the front and back surfaces of the substrate can be processed at one time, the number of steps of exposure, development, and plating can be greatly reduced.
- a glass substrate or a silicon substrate is prepared as the insulating substrate 1 used for the wiring substrate, and if necessary, the surface or the end surface is trimmed, the surface is cleaned, and the surface is insulated. I have done.
- FIG. 22A through holes 100 are formed in the insulating substrate 1 by sandblasting. Subsequently, microcracks generated on the insulating substrate 1 are removed. Subsequently, as shown in FIG. 22B, wiring is formed on the through hole 100 of the insulating substrate 1 and the insulating substrate 1. Wiring can be formed using the semi-additive method, the subtractive method, or the like in the same manner as in the first and second embodiments.
- the front and back surfaces of the through hole 100 inner surface insulating substrate 1 (primary surface, secondary surface) The same as in Example 2 in that a power supply film is formed on the three surfaces.
- the difference between the second embodiment and this embodiment is that the order of filling the through hole 100 of the insulating substrate 1 with an insulating substance and forming the interlayer insulating layer 110 (thin film wiring layer 2) on the insulating substrate 1 is different. It is in.
- Example 2 the primary side end of the through hole 100 was left open when the wiring on the substrate surface was formed, and the inside of the through hole was filled in that state.
- the opening end on the primary side of the insulating substrate 1 is closed by wiring. If the diameter of the through-hole is small, increasing the thickness of the plating allows the narrower end of the through-hole (primary opening) to be covered with the coating. Piercing After closing the through hole opening end, the multilayer wiring layer 3 is formed.
- the through hole 100 whose primary side opening end is closed is filled.
- the filling may be performed by paste printing of an insulating substance, or the filling of a conductive material may be performed.
- a stress relaxation layer 5 is formed if necessary, and holes are formed in the stress and relaxation layer 5 by photoetching or laser calorie.
- wiring is formed on the holes and on the surfaces of the formed multilayer wiring layer 3 and stress relaxation layer 5 in FIG. 23B to complete the multilayer wiring board 6.
- the insulating hole 1 Since the wiring on the secondary side on the insulating substrate 1 closes the opening of the through hole 100, after forming the multi-layer wiring layer 3, the insulating hole 1 The substance can be filled. As a result, it is possible to effectively suppress the formation of the unfilled portion 201 near the primary end face of the insulating substrate 1. As a result, the flatness of the interlayer insulating layer formed in the next step can be ensured, and it becomes easier to form wiring with high density.
- FIG. 6 shows an enlarged photograph of a through hole formed in a substrate by using sandblasting.
- FIG. 24 shows a schematic diagram of the force.
- the back side (primary side) of the side on which the sand is blown by the sandblasting of the insulating substrate (hereinafter, secondary side) is opened.
- the hole has a constricted shape at the tip. That is, assuming that the secondary side opening diameter is dl, the primary side opening diameter is d3, and immediately before the primary side opening diameter is d2, dl>d3> d2.
- this constricted shape has a size of only a few micrometers at the processing tip, but considering that the thickness of the power supply film is less than 1 micrometer, The concave shape of several micrometers has a great effect on the formation of the feed film.
- the formation of the power supply film on the inner surface of the through-hole is likely to be insufficient by a method such as sputtering CVD or vapor deposition. Therefore, it becomes difficult to form a copper wiring by plating at that location.
- Cr, Ti, and the like which are formed by sputtering in order to ensure the adhesion between the substrate and the wiring, tend to hardly wrap around.
- a malleable metal such as copper
- even a sputtered film can go around a few micrometers, but the adhesion film such as Cr, which should be originally formed underneath, is not precisely formed. Insufficient wiring adhesion is likely to occur.
- the constriction at the tip of the opening is due to a median crack formed during sand blasting, as indicated by the fact that it is formed in the depth direction with respect to the wall surface of the through hole.
- a first method there is a method in which after forming a through-hole, the substrate is polished or ground to a thickness where the constricted shape is formed, and the constricted shape is removed to flatten the substrate.
- CMP chemical mechanical polishing
- a third method as shown in Fig. 25, another member is applied to the primary side of the substrate, or a film or the like is attached to the primary side substrate, and after the through hole reaches the substrate, the member is used. Or there is a method of removing the film.
- the member to be applied or adhered to the secondary side of the substrate is desirably a material having a bending elastic modulus equal to or higher than that of the insulating substrate 1, but is not limited thereto. It is also desirable that the primary side be in close contact with no gap.
- a reinforcing film may be provided on the secondary surface of the insulating substrate 1 by using sputtering or the like.
- the member to be applied may be, for example, wiring formed on a substrate.
- sputtering is performed on the through-holes of the substrate while the constricted shape remains, by sputtering from both the primary side and the secondary side of the substrate.
- chromium is sputtered from the secondary direction of the substrate, then the substrate is turned over, chromium is sputtered from the primary direction, and then copper is There is a method in which the substrate is turned over once again and copper is sputtered from the secondary direction of the substrate.
- the power supply film (Cu / Cr) can be uniformly formed inside the through hole without removing the constricted shape of the substrate.
- a highly reliable metal wiring can be formed in a through hole formed by sandblasting.
- the above five methods are effective when plating wiring is applied to a through-hole formed by sandblasting.
- the substrate on which the through-hole is formed is not limited to a glass or silicon substrate. Material, for example ceramic substrate This is also effective when plating wiring is formed in the through hole formed in the substrate.
- the thickness of the stress relaxation layer 5 depends on the size of the semiconductor module, the elastic modulus of the stress relaxation layer 5, the thickness and the diagonal length of the insulating substrate 1, and cannot be unambiguously determined.
- an acceptable stress relaxation layer 5 was obtained. It has been found that the film thickness range is preferably from 10 to 500 micrometers, more preferably from 30 to 250 micrometers. This corresponds to a thickness of about 1/10 to 1/2 of the thickness of the insulating substrate 1.
- the film thickness is less than 30 micrometers, the desired stress relaxation cannot be obtained, and if the film thickness exceeds 250 micrometers, the internal stress of the stress relaxation layer 5 itself is reduced. As a result, the insulating substrate 1 may be warped and the substrate may be damaged, or the wiring may be disconnected.
- the stress relaxation layer 5 is formed of a resin material having an elastic coefficient significantly smaller than that of the insulating substrate 1, for example, from 0.1 GPa to 10 GPa at room temperature. If the stress relaxation layer 5 has an elastic coefficient in this range, a reliable multilayer wiring board 6 can be provided. That is, in the case of the stress relaxation layer 5 having an elastic coefficient of less than 0.1 GPa, it is difficult to support the weight of the insulating substrate 1 itself, and the characteristics are not stable when used as the semiconductor module 100. Problems are easy to occur. On the other hand, if the stress relaxation layer 5 having an elastic modulus exceeding 10 GPa is used, the insulation substrate 1 may be warped due to the internal stress of the stress relaxation layer 5 5 itself, and the insulation substrate 1 may be broken. is there.
- the material for forming the stress relaxation layer 5 used here is a paste-like polyimide, but is not necessarily limited to this.
- the paste-like polyimide is composed of a polyimide precursor, a solvent, and a large number of polyimide fine particles dispersed therein.
- the fine particles Specifically, fine particles having an average particle size of 1 to 2 micrometer and having a particle size distribution with a maximum particle size of about 10 micrometer were used. Since the polyimide precursor used in this example becomes the same material as the polyimide microparticles when cured, when the paste-like polyimide hardens, a uniform stress relaxation made of one type of material occurs.
- the sum layer 5 is formed.
- polyimide was used as the material for forming the stress relaxation layer 5, but in this embodiment, in addition to polyimide, amide imide resin, ester imide resin, ether imide resin, silicone resin, acrylic resin, polyester resin, and these are modified. It is also possible to use a resin which has been used. When a resin other than polyimide is used, a treatment for imparting compatibility to the surface of the polyimide microparticles described above, or a modification of the resin composition so as to improve the affinity with the polyimide microparticles should be performed. Is desirable.
- resins having an imide bond such as polyimide, amide imide, ester imide, and ether imide
- thermomechanical properties such as high-temperature strength
- thermomechanical properties such as high-temperature strength
- Silicone resin Polyacrylic resin, polyester resin, amide imide, ester imid, ether imide, etc.Resin with a portion condensed by a bond other than imide bond is slightly inferior in thermo-mechanical properties but advantageous in terms of processability and resin price
- polyesterimide resin is generally easier to handle because it has a lower curing temperature than polyimide.
- the material for forming the stress relaxation layer 5 is, for example, a resin such as epoxy, phenol, polyimide, or silicone, alone or in combination of two or more resins. And the like can be blended and used. In the present embodiment, these resins are appropriately used in consideration of price, thermo-mechanical properties, and the like from among these resins.
- the thixotropic properties of the paste can be controlled by adjusting the composition of the fine particles. Can be improved.
- the thixotropy characteristic of the paste suitable in the examples of the present application is a so-called thixotropy index obtained from the ratio of the viscosity at a rotation speed of 1 rpm and the viscosity at a rotation speed of 10 rpm measured using a rotational viscometer. Is preferably in the range of 10.0 to 10.0. In the case of a paste in which the thixotropy index has a temperature dependency, high performance can be obtained by printing in a temperature region where the thixotropy index is in the range of 1.0 to 10.0.
- a predetermined film thickness can be obtained by repeating printing and curing of the material a plurality of times. For example, if a metal mask with a thickness of 65 ⁇ m is used using a paste with a solid concentration of 30 to 40%, it is possible to obtain a film thickness of about 50 ⁇ m after curing by two printings. I can do it.
- the material for the stress relaxation layer 5 it is desirable to use a material having a curing temperature of 100 ° C. to 250 ° C. for the material for the stress relaxation layer 5. If the curing temperature is lower than this, it is difficult to control within the semiconductor module manufacturing process, and if the curing temperature is higher than this, there is a concern that the stress of the isolated substrate 1 will increase due to heat shrinkage during curing and cooling. .
- the glass transition temperature (T g) of the heat resistance is preferably more than 150 ° C. and not more than 400 ° C. or less, more preferably T g is more than 180 ° C. Preferably, T g is 200 ° C. or higher.
- Figure 27 shows the experimental results showing the relationship between the glass transition temperature (T g) and the coefficient of linear expansion. From this, it can be seen that cracks did not occur when the glass transition temperature (T g) was 200 ° C. or higher.
- the preferred linear expansion coefficient of the stress relaxation layer 5 material in this embodiment is in the range of 3 ppm / ° C to 300 ppmZ ° C. It is desirable. More preferably, it is in the range of 3 ppmZ ° C to 200 ppmZ ° C, and the most desirable linear expansion coefficient is in the range of 3 ppmZ ° C to 150 ppm / ° C.
- the coefficient of linear expansion When the coefficient of linear expansion is large, it is desirable that the above-mentioned elastic coefficient is small. More specifically, the bullet It is recommended that the value of the product of the coefficient of thermal expansion (GPa) and the coefficient of linear expansion (ppm / ° C) be within a specific range.
- the desirable range of this value varies depending on the size, thickness, and mounting form of the substrate, but generally, it is desirable that this value is generally in the range of 50 to 100,000.
- the thermal decomposition temperature (T d) is desirably about 300 ° C. or higher, and more desirably, 350 ° C. or higher. If the Tg or Td is below these values, there is a risk that the resin will be deformed, deteriorated or decomposed during a thermal process in the process, for example, a sputter / sputter etch process. From the viewpoint of chemical resistance, it is desirable that resin aging such as discoloration and deformation does not occur when immersed in a 30% aqueous sulfuric acid solution or a 10% aqueous sodium hydroxide solution for 24 hours or more.
- the solubility parameter (SP value) is desirably 5 to 30 (cal / cm3) 1Z2.
- the material for the stress relaxation layer 5 is a material obtained by modifying some components to the base resin, it is desirable that most of the composition fall within the range of the solubility parameter. More specifically, it is desirable that a component having a solubility parameter (SP value) of less than 5 or more than 30 does not exceed 50% by weight.
- the wiring board mainly made of glass and silicon, the multilayer wiring board using the same, and the multichip module using the same have been described in detail.
- a wiring board and a method of manufacturing the wiring board according to the present invention are controlled by using a displacement sensor or the like to control the position and orientation of a moving object by detecting acceleration or angular velocity and a method of manufacturing the same. The case where the method is used will be described.
- FIG. 30a the surface of the device wafer 400 is etched.
- the device wafer 400 which has been etched onto a first substrate for protecting the device wafer 400, for example, a glass substrate, is joined (Ob in FIG. 3).
- the device wafer 400 is re-etched to form devices such as fine vibration elements. (Figure 30c).
- a second substrate 420 such as a glass substrate supporting the device wafer 400 is etched to form a concave portion (FIG. 30d). Subsequently, the device wafer on which the vibrating element and the like are formed and the second substrate 420 are joined (FIG. 30e).
- a through-hole 430 is formed in the first substrate 410 by sand blast (FIG. 30f).
- a through hole is formed in the first substrate, a depression (hole) may be formed at a position of the first substrate to be diced in a later individualization step.
- the surface of the first substrate 410 and the through holes (contact holes) of the first substrate 410 are formed.
- a conductor metal as shown in Fig. 30g is deposited and patterned inside the 400 to form wiring.
- microsensor micro gyro
- Fig. 3 Oh the microsensor formed on the second glass substrate 420 is diced and individualized. This completes the package for the microphone port sensor.
- the wiring on the inner wall surface of the through hole may be formed before bonding to the device wafer, and the package substrate on which the wiring pattern is formed may be bonded to the device wafer.
- the wiring on the inner wall surface of the through-hole may be formed by sputtering from both sides of the substrate as described in the above embodiment.
- a constricted portion may be formed at the opening end of the through-hole as described above. Therefore, the package substrate is polished after the through-hole is formed.
- Well is ,.
- a layer for reducing thermal stress may be provided.
- the micro gyro can be made smaller.
- the through-hole is formed by sandblasting, the adhesion between the metal material forming the wiring and the package substrate is increased due to minute unevenness in the through-hole, and a short circuit or the like can be prevented. Also the book In the embodiment, short-circuiting of the wiring and the like can be prevented by removing the constricted portion of the through-hole which is not formed or the formed constricted portion by polishing.
- the first and second it is possible to maintain a vacuum state in the cavity where the vibrating element is located between the substrate and the device wafer.
- displacement sensors and inertial sensors are used in vehicle stability control systems, automotive systems, napige systems, camera shake prevention for cameras and small video cameras, etc. Used as a sensor required for
- the present invention has been specifically described based on the embodiments.
- the present invention is not limited to the embodiments, and various changes can be made without departing from the gist of the present invention.
- a wiring board having high reliability and capable of high-density wiring can be manufactured.
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001163641A JP4012375B2 (ja) | 2001-05-31 | 2001-05-31 | 配線基板およびその製造方法 |
| JP2001-163641 | 2001-05-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2002100142A1 true WO2002100142A1 (en) | 2002-12-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2002/005162 Ceased WO2002100142A1 (en) | 2001-05-31 | 2002-05-28 | Wiring board and its production method |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP4012375B2 (ja) |
| TW (1) | TW550983B (ja) |
| WO (1) | WO2002100142A1 (ja) |
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| EP3905323B1 (en) | 2019-08-23 | 2024-08-14 | Absolics Inc. | Packaging substrate and semiconductor device comprising same |
| JP7010314B2 (ja) * | 2020-02-03 | 2022-01-26 | 大日本印刷株式会社 | 貫通電極基板 |
| JP7327535B2 (ja) * | 2020-02-25 | 2023-08-16 | 大日本印刷株式会社 | 貫通電極基板 |
| WO2021182554A1 (ja) * | 2020-03-12 | 2021-09-16 | リンテック株式会社 | 保護膜形成用シート |
| JP7538247B2 (ja) * | 2020-11-27 | 2024-08-21 | 京セラ株式会社 | 印刷配線板および印刷配線板の製造方法 |
| KR20250101308A (ko) * | 2023-12-27 | 2025-07-04 | 앱솔릭스 인코포레이티드 | 패키징 기판이 배치된 기판의 제조 방법 |
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- 2001-05-31 JP JP2001163641A patent/JP4012375B2/ja not_active Expired - Fee Related
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- 2002-05-28 WO PCT/JP2002/005162 patent/WO2002100142A1/ja not_active Ceased
- 2002-05-30 TW TW091111588A patent/TW550983B/zh not_active IP Right Cessation
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| JPH0567878A (ja) * | 1991-09-06 | 1993-03-19 | Hitachi Ltd | 混成回路基板及びその製造方法 |
| EP0599595A2 (en) * | 1992-11-25 | 1994-06-01 | Matsushita Electric Industrial Co., Ltd. | Ceramic electronic device and method of producing the same |
| JPH08335778A (ja) * | 1995-06-08 | 1996-12-17 | Kyocera Corp | 多層薄膜配線基板 |
| JP2000024923A (ja) * | 1998-07-09 | 2000-01-25 | Seiko Epson Corp | 微細穴・溝加工方法 |
| JP2000100988A (ja) * | 1998-09-18 | 2000-04-07 | Sumitomo Metal Electronics Devices Inc | Pgaパッケージ |
| JP2001036250A (ja) * | 1999-07-16 | 2001-02-09 | Mitsubishi Electric Corp | 多層配線基板の製造方法、多層配線基板およびそれを用いた半導体装置 |
| JP2001044597A (ja) * | 1999-07-29 | 2001-02-16 | Mitsubishi Gas Chem Co Inc | 炭酸ガスレーザー孔あけ性に優れた銅張板 |
| JP2001111197A (ja) * | 1999-10-14 | 2001-04-20 | Mitsubishi Electric Corp | セラミックス基板の製造方法 |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2543065A4 (en) * | 2010-03-03 | 2018-01-24 | Georgia Tech Research Corporation | Through-package-via (tpv) structures on inorganic interposer and methods for fabricating same |
| US10672718B2 (en) | 2010-03-03 | 2020-06-02 | Georgia Tech Research Corporation | Through-package-via (TPV) structures on inorganic interposer and methods for fabricating same |
| EP3806140A4 (en) * | 2018-05-25 | 2021-08-04 | Toppan Printing Co., Ltd. | GLASS CIRCUIT BOARD AND METHOD OF MANUFACTURING THEREOF |
| CN112652608A (zh) * | 2019-10-09 | 2021-04-13 | 财团法人工业技术研究院 | 多芯片封装件及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4012375B2 (ja) | 2007-11-21 |
| JP2002359446A (ja) | 2002-12-13 |
| TW550983B (en) | 2003-09-01 |
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