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WO2002033565A3 - Structure d'interconnexion adaptable autorisant un traitement parallele et l'acces a une memoire parallele - Google Patents

Structure d'interconnexion adaptable autorisant un traitement parallele et l'acces a une memoire parallele Download PDF

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Publication number
WO2002033565A3
WO2002033565A3 PCT/US2001/050543 US0150543W WO0233565A3 WO 2002033565 A3 WO2002033565 A3 WO 2002033565A3 US 0150543 W US0150543 W US 0150543W WO 0233565 A3 WO0233565 A3 WO 0233565A3
Authority
WO
WIPO (PCT)
Prior art keywords
parallel
several
memory access
interconnect structure
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/050543
Other languages
English (en)
Other versions
WO2002033565A2 (fr
Inventor
John Hess
Coke S Reed
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Interactic Holdings LLC
Original Assignee
Interactic Holdings LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interactic Holdings LLC filed Critical Interactic Holdings LLC
Priority to EP01987920A priority Critical patent/EP1360595A2/fr
Priority to CA2426422A priority patent/CA2426422C/fr
Priority to AU2002229127A priority patent/AU2002229127A1/en
Priority to MXPA03003528A priority patent/MXPA03003528A/es
Priority to JP2002536883A priority patent/JP4128447B2/ja
Publication of WO2002033565A2 publication Critical patent/WO2002033565A2/fr
Anticipated expiration legal-status Critical
Publication of WO2002033565A3 publication Critical patent/WO2002033565A3/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

Selon la présente invention, de multiples processeurs peuvent accéder aux mêmes données en parallèle en mettant en oeuvre diverses techniques innovatrices. Tout d'abord, plusieurs processeurs à distance peuvent effectuer une requête de lecture depuis un même emplacement de données et les requêtes peuvent être satisfaites dans des périodes de temps se chevauchant. Ensuite, plusieurs processeurs peuvent accéder à un élément de données qui est situé au même emplacement et peut lire, écrire ou réaliser plusieurs opérations aux mêmes moments se chevauchant d'élément de données, puis un paquet de données peut être diffusé sélectivement vers plusieurs emplacements et plusieurs paquets peuvent être diffusés sélectivement vers plusieurs ensembles d'emplacements cibles.
PCT/US2001/050543 2000-10-19 2001-10-19 Structure d'interconnexion adaptable autorisant un traitement parallele et l'acces a une memoire parallele Ceased WO2002033565A2 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP01987920A EP1360595A2 (fr) 2000-10-19 2001-10-19 Structure d'interconnexion adaptable autorisant un traitement parallele et l'acces a une memoire parallele
CA2426422A CA2426422C (fr) 2000-10-19 2001-10-19 Structure d'interconnexion adaptable autorisant un traitement parallele et l'acces a une memoire parallele
AU2002229127A AU2002229127A1 (en) 2000-10-19 2001-10-19 Scaleable interconnect structure for parallel computing and parallel memory access
MXPA03003528A MXPA03003528A (es) 2000-10-19 2001-10-19 Estructura de interconexion escalable para operaciones de computo paralelas y acceso paralelo a memoria.
JP2002536883A JP4128447B2 (ja) 2000-10-19 2001-10-19 並列演算及び並列メモリーアクセスのためのスケーラブルなインターコネクト構造

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69360300A 2000-10-19 2000-10-19
US09/693,603 2000-10-19

Publications (2)

Publication Number Publication Date
WO2002033565A2 WO2002033565A2 (fr) 2002-04-25
WO2002033565A3 true WO2002033565A3 (fr) 2003-08-21

Family

ID=24785344

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/050543 Ceased WO2002033565A2 (fr) 2000-10-19 2001-10-19 Structure d'interconnexion adaptable autorisant un traitement parallele et l'acces a une memoire parallele

Country Status (7)

Country Link
EP (1) EP1360595A2 (fr)
JP (1) JP4128447B2 (fr)
CN (1) CN100341014C (fr)
AU (1) AU2002229127A1 (fr)
CA (1) CA2426422C (fr)
MX (1) MXPA03003528A (fr)
WO (1) WO2002033565A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10168923B2 (en) 2016-04-26 2019-01-01 International Business Machines Corporation Coherency management for volatile and non-volatile memory in a through-silicon via (TSV) module

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8605099B2 (en) 2008-03-31 2013-12-10 Intel Corporation Partition-free multi-socket memory system architecture
CN101833439B (zh) * 2010-04-20 2013-04-10 清华大学 基于分合思想的并行计算硬件结构
CN102542525B (zh) * 2010-12-13 2014-02-12 联想(北京)有限公司 一种信息处理设备以及信息处理方法
US10236043B2 (en) * 2016-06-06 2019-03-19 Altera Corporation Emulated multiport memory element circuitry with exclusive-OR based control circuitry
FR3083350B1 (fr) * 2018-06-29 2021-01-01 Vsora Acces memoire de processeurs
US10872038B1 (en) * 2019-09-30 2020-12-22 Facebook, Inc. Memory organization for matrix processing
US12183412B2 (en) 2020-09-25 2024-12-31 Altera Corporation Method and apparatus for enabling multiple return material authorizations (RMAs) on an integrated circuit device
WO2025024736A1 (fr) * 2023-07-27 2025-01-30 Ascenium, Inc. Architecture de traitement parallèle avec support de déplacement de bloc
CN117294412B (zh) * 2023-11-24 2024-02-13 合肥六角形半导体有限公司 基于单比特位移的多通道串转并自动对齐电路及方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4977582A (en) * 1988-03-31 1990-12-11 At&T Bell Laboratories Synchronization of non-continuous digital bit streams
EP0804005A2 (fr) * 1996-04-25 1997-10-29 Compaq Computer Corporation Commutateur de réseau
WO1998033304A1 (fr) * 1997-01-24 1998-07-30 Interactic Holdings, Llc Commutateur a faible latence a geometrie variable, utilisable dans une structure d'interconnexion
EP0459757B1 (fr) * 1990-05-29 1999-07-28 Advanced Micro Devices, Inc. Adaptateur de réseau

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4977582A (en) * 1988-03-31 1990-12-11 At&T Bell Laboratories Synchronization of non-continuous digital bit streams
EP0459757B1 (fr) * 1990-05-29 1999-07-28 Advanced Micro Devices, Inc. Adaptateur de réseau
EP0804005A2 (fr) * 1996-04-25 1997-10-29 Compaq Computer Corporation Commutateur de réseau
WO1998033304A1 (fr) * 1997-01-24 1998-07-30 Interactic Holdings, Llc Commutateur a faible latence a geometrie variable, utilisable dans une structure d'interconnexion
US6289021B1 (en) * 1997-01-24 2001-09-11 Interactic Holdings, Llc Scaleable low-latency switch for usage in an interconnect structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10168923B2 (en) 2016-04-26 2019-01-01 International Business Machines Corporation Coherency management for volatile and non-volatile memory in a through-silicon via (TSV) module

Also Published As

Publication number Publication date
MXPA03003528A (es) 2005-01-25
EP1360595A2 (fr) 2003-11-12
CA2426422A1 (fr) 2002-04-25
JP2004531783A (ja) 2004-10-14
WO2002033565A2 (fr) 2002-04-25
CN100341014C (zh) 2007-10-03
CA2426422C (fr) 2012-04-10
CN1489732A (zh) 2004-04-14
AU2002229127A1 (en) 2002-04-29
JP4128447B2 (ja) 2008-07-30

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